1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/mmu_context.h>
21 #ifdef CONFIG_X86_LOCAL_APIC
22 #include <asm/mpspec.h>
24 #include <mach_apic.h>
27 #include <asm/pgtable.h>
28 #include <asm/processor.h>
30 #include <asm/atomic.h>
31 #include <asm/proto.h>
32 #include <asm/sections.h>
33 #include <asm/setup.h>
34 #include <asm/genapic.h>
38 /* We need valid kernel segments for data and code in long mode too
39 * IRET will check the segment types kkeil 2000/10/28
40 * Also sysret mandates a special GDT layout
42 /* The TLS descriptors are currently at a different place compared to i386.
43 Hopefully nobody expects them at a fixed place (Wine?) */
44 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
45 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
46 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
47 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
48 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
49 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
50 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
52 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
54 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
56 /* Current gdt points %fs at the "master" per-cpu area: after this,
57 * it's on the real one. */
58 void switch_to_new_gdt(void)
60 struct desc_ptr gdt_descr;
62 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
63 gdt_descr.size = GDT_SIZE - 1;
67 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
69 static void __cpuinit default_init(struct cpuinfo_x86 *c)
74 static struct cpu_dev __cpuinitdata default_cpu = {
75 .c_init = default_init,
76 .c_vendor = "Unknown",
78 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
80 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
84 if (c->extended_cpuid_level < 0x80000004)
87 v = (unsigned int *) c->x86_model_id;
88 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
89 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
90 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
91 c->x86_model_id[48] = 0;
96 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
98 unsigned int n, dummy, ebx, ecx, edx;
100 n = c->extended_cpuid_level;
102 if (n >= 0x80000005) {
103 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
104 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
105 "D cache %dK (%d bytes/line)\n",
106 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
107 c->x86_cache_size = (ecx>>24) + (edx>>24);
108 /* On K8 L1 TLB is inclusive, so don't count it */
112 if (n >= 0x80000006) {
113 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
114 ecx = cpuid_ecx(0x80000006);
115 c->x86_cache_size = ecx >> 16;
116 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
118 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
119 c->x86_cache_size, ecx & 0xFF);
123 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
126 u32 eax, ebx, ecx, edx;
127 int index_msb, core_bits;
129 cpuid(1, &eax, &ebx, &ecx, &edx);
132 if (!cpu_has(c, X86_FEATURE_HT))
134 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
137 smp_num_siblings = (ebx & 0xff0000) >> 16;
139 if (smp_num_siblings == 1) {
140 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
141 } else if (smp_num_siblings > 1) {
143 if (smp_num_siblings > NR_CPUS) {
144 printk(KERN_WARNING "CPU: Unsupported number of "
145 "siblings %d", smp_num_siblings);
146 smp_num_siblings = 1;
150 index_msb = get_count_order(smp_num_siblings);
151 c->phys_proc_id = phys_pkg_id(index_msb);
153 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
155 index_msb = get_count_order(smp_num_siblings);
157 core_bits = get_count_order(c->x86_max_cores);
159 c->cpu_core_id = phys_pkg_id(index_msb) &
160 ((1 << core_bits) - 1);
163 if ((c->x86_max_cores * smp_num_siblings) > 1) {
164 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
166 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
173 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
175 char *v = c->x86_vendor_id;
179 for (i = 0; i < X86_VENDOR_NUM; i++) {
181 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
182 (cpu_devs[i]->c_ident[1] &&
183 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
185 this_cpu = cpu_devs[i];
192 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
193 printk(KERN_ERR "CPU: Your system may be unstable.\n");
195 c->x86_vendor = X86_VENDOR_UNKNOWN;
198 static void __init early_cpu_support_print(void)
201 struct cpu_dev *cpu_devx;
203 printk("KERNEL supported cpus:\n");
204 for (i = 0; i < X86_VENDOR_NUM; i++) {
205 cpu_devx = cpu_devs[i];
208 for (j = 0; j < 2; j++) {
209 if (!cpu_devx->c_ident[j])
211 printk(" %s %s\n", cpu_devx->c_vendor,
212 cpu_devx->c_ident[j]);
217 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
219 void __init early_cpu_init(void)
221 struct cpu_vendor_dev *cvdev;
223 for (cvdev = __x86cpuvendor_start ;
224 cvdev < __x86cpuvendor_end ;
226 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
227 early_cpu_support_print();
228 early_identify_cpu(&boot_cpu_data);
231 /* Do some early cpuid on the boot CPU to get some parameter that are
232 needed before check_bugs. Everything advanced is in identify_cpu
234 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
238 c->loops_per_jiffy = loops_per_jiffy;
239 c->x86_cache_size = -1;
240 c->x86_vendor = X86_VENDOR_UNKNOWN;
241 c->x86_model = c->x86_mask = 0; /* So far unknown... */
242 c->x86_vendor_id[0] = '\0'; /* Unset */
243 c->x86_model_id[0] = '\0'; /* Unset */
244 c->x86_clflush_size = 64;
245 c->x86_cache_alignment = c->x86_clflush_size;
246 c->x86_max_cores = 1;
247 c->x86_coreid_bits = 0;
248 c->extended_cpuid_level = 0;
249 memset(&c->x86_capability, 0, sizeof c->x86_capability);
251 /* Get vendor name */
252 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
253 (unsigned int *)&c->x86_vendor_id[0],
254 (unsigned int *)&c->x86_vendor_id[8],
255 (unsigned int *)&c->x86_vendor_id[4]);
259 /* Initialize the standard set of capabilities */
260 /* Note that the vendor-specific code below might override */
262 /* Intel-defined flags: level 0x00000001 */
263 if (c->cpuid_level >= 0x00000001) {
265 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
266 &c->x86_capability[0]);
267 c->x86 = (tfms >> 8) & 0xf;
268 c->x86_model = (tfms >> 4) & 0xf;
269 c->x86_mask = tfms & 0xf;
271 c->x86 += (tfms >> 20) & 0xff;
273 c->x86_model += ((tfms >> 16) & 0xF) << 4;
274 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
275 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
277 /* Have CPUID level 0 only - unheard of */
281 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
283 c->phys_proc_id = c->initial_apicid;
285 /* AMD-defined flags: level 0x80000001 */
286 xlvl = cpuid_eax(0x80000000);
287 c->extended_cpuid_level = xlvl;
288 if ((xlvl & 0xffff0000) == 0x80000000) {
289 if (xlvl >= 0x80000001) {
290 c->x86_capability[1] = cpuid_edx(0x80000001);
291 c->x86_capability[6] = cpuid_ecx(0x80000001);
293 if (xlvl >= 0x80000004)
294 get_model_name(c); /* Default name */
297 /* Transmeta-defined flags: level 0x80860001 */
298 xlvl = cpuid_eax(0x80860000);
299 if ((xlvl & 0xffff0000) == 0x80860000) {
300 /* Don't set x86_cpuid_level here for now to not confuse. */
301 if (xlvl >= 0x80860001)
302 c->x86_capability[2] = cpuid_edx(0x80860001);
305 c->extended_cpuid_level = cpuid_eax(0x80000000);
306 if (c->extended_cpuid_level >= 0x80000007)
307 c->x86_power = cpuid_edx(0x80000007);
309 if (c->extended_cpuid_level >= 0x80000008) {
310 u32 eax = cpuid_eax(0x80000008);
312 c->x86_virt_bits = (eax >> 8) & 0xff;
313 c->x86_phys_bits = eax & 0xff;
316 /* Assume all 64-bit CPUs support 32-bit syscall */
317 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
319 if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
320 cpu_devs[c->x86_vendor]->c_early_init)
321 cpu_devs[c->x86_vendor]->c_early_init(c);
323 validate_pat_support(c);
325 /* early_param could clear that, but recall get it set again */
327 clear_cpu_cap(c, X86_FEATURE_APIC);
331 * This does the hard work of actually picking apart the CPU stuff...
333 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
337 early_identify_cpu(c);
339 init_scattered_cpuid_features(c);
341 c->apicid = phys_pkg_id(0);
344 * Vendor-specific initialization. In this section we
345 * canonicalize the feature flags, meaning if there are
346 * features a certain CPU supports which CPUID doesn't
347 * tell us, CPUID claiming incorrect flags, or other bugs,
348 * we handle them here.
350 * At the end of this section, c->x86_capability better
351 * indicate the features this CPU genuinely supports!
353 if (this_cpu->c_init)
359 * On SMP, boot_cpu_data holds the common feature set between
360 * all CPUs; so make sure that we indicate which features are
361 * common between the CPUs. The first time this routine gets
362 * executed, c == &boot_cpu_data.
364 if (c != &boot_cpu_data) {
365 /* AND the already accumulated flags with these */
366 for (i = 0; i < NCAPINTS; i++)
367 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
370 /* Clear all flags overriden by options */
371 for (i = 0; i < NCAPINTS; i++)
372 c->x86_capability[i] &= ~cleared_cpu_caps[i];
374 #ifdef CONFIG_X86_MCE
377 select_idle_routine(c);
380 numa_add_cpu(smp_processor_id());
385 void __cpuinit identify_boot_cpu(void)
387 identify_cpu(&boot_cpu_data);
390 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
392 BUG_ON(c == &boot_cpu_data);
397 static __init int setup_noclflush(char *arg)
399 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
402 __setup("noclflush", setup_noclflush);
404 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
406 if (c->x86_model_id[0])
407 printk(KERN_CONT "%s", c->x86_model_id);
409 if (c->x86_mask || c->cpuid_level >= 0)
410 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
412 printk(KERN_CONT "\n");
415 static __init int setup_disablecpuid(char *arg)
418 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
419 setup_clear_cpu_cap(bit);
424 __setup("clearcpuid=", setup_disablecpuid);
426 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
428 struct x8664_pda **_cpu_pda __read_mostly;
429 EXPORT_SYMBOL(_cpu_pda);
431 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
433 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
435 unsigned long __supported_pte_mask __read_mostly = ~0UL;
436 EXPORT_SYMBOL_GPL(__supported_pte_mask);
438 static int do_not_nx __cpuinitdata;
441 Control non executable mappings for 64bit processes.
446 static int __init nonx_setup(char *str)
450 if (!strncmp(str, "on", 2)) {
451 __supported_pte_mask |= _PAGE_NX;
453 } else if (!strncmp(str, "off", 3)) {
455 __supported_pte_mask &= ~_PAGE_NX;
459 early_param("noexec", nonx_setup);
461 int force_personality32;
464 Control non executable heap for 32bit processes.
465 To control the stack too use noexec=off
467 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
468 off PROT_READ implies PROT_EXEC
470 static int __init nonx32_setup(char *str)
472 if (!strcmp(str, "on"))
473 force_personality32 &= ~READ_IMPLIES_EXEC;
474 else if (!strcmp(str, "off"))
475 force_personality32 |= READ_IMPLIES_EXEC;
478 __setup("noexec32=", nonx32_setup);
480 void pda_init(int cpu)
482 struct x8664_pda *pda = cpu_pda(cpu);
484 /* Setup up data that may be needed in __get_free_pages early */
487 /* Memory clobbers used to order PDA accessed */
489 wrmsrl(MSR_GS_BASE, pda);
492 pda->cpunumber = cpu;
494 pda->kernelstack = (unsigned long)stack_thread_info() -
495 PDA_STACKOFFSET + THREAD_SIZE;
496 pda->active_mm = &init_mm;
500 /* others are initialized in smpboot.c */
501 pda->pcurrent = &init_task;
502 pda->irqstackptr = boot_cpu_stack;
504 pda->irqstackptr = (char *)
505 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
506 if (!pda->irqstackptr)
507 panic("cannot allocate irqstack for cpu %d", cpu);
509 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
510 pda->nodenumber = cpu_to_node(cpu);
513 pda->irqstackptr += IRQSTACKSIZE-64;
516 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
518 __attribute__((section(".bss.page_aligned")));
520 extern asmlinkage void ignore_sysret(void);
522 /* May not be marked __init: used by software suspend */
523 void syscall_init(void)
526 * LSTAR and STAR live in a bit strange symbiosis.
527 * They both write to the same internal register. STAR allows to
528 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
530 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
531 wrmsrl(MSR_LSTAR, system_call);
532 wrmsrl(MSR_CSTAR, ignore_sysret);
534 #ifdef CONFIG_IA32_EMULATION
535 syscall32_cpu_init();
538 /* Flags to clear on syscall */
539 wrmsrl(MSR_SYSCALL_MASK,
540 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
543 void __cpuinit check_efer(void)
547 rdmsrl(MSR_EFER, efer);
548 if (!(efer & EFER_NX) || do_not_nx)
549 __supported_pte_mask &= ~_PAGE_NX;
552 unsigned long kernel_eflags;
555 * Copies of the original ist values from the tss are only accessed during
556 * debugging, no special alignment required.
558 DEFINE_PER_CPU(struct orig_ist, orig_ist);
561 * cpu_init() initializes state that is per-CPU. Some data is already
562 * initialized (naturally) in the bootstrap process, such as the GDT
563 * and IDT. We reload them nevertheless, this function acts as a
564 * 'CPU state barrier', nothing should get across.
565 * A lot of state is already set up in PDA init.
567 void __cpuinit cpu_init(void)
569 int cpu = stack_smp_processor_id();
570 struct tss_struct *t = &per_cpu(init_tss, cpu);
571 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
573 char *estacks = NULL;
574 struct task_struct *me;
577 /* CPU 0 is initialised in head64.c */
581 estacks = boot_exception_stacks;
585 if (cpu_test_and_set(cpu, cpu_initialized))
586 panic("CPU#%d already initialized!\n", cpu);
588 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
590 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
593 * Initialize the per-CPU GDT with the boot GDT,
594 * and set up the GDT descriptor:
598 load_idt((const struct desc_ptr *)&idt_descr);
600 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
603 wrmsrl(MSR_FS_BASE, 0);
604 wrmsrl(MSR_KERNEL_GS_BASE, 0);
610 * set up and load the per-CPU TSS
612 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
613 static const unsigned int order[N_EXCEPTION_STACKS] = {
614 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
615 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
618 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
620 panic("Cannot allocate exception stack %ld %d\n",
623 estacks += PAGE_SIZE << order[v];
624 orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
627 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
629 * <= is required because the CPU will access up to
630 * 8 bits beyond the end of the IO permission bitmap.
632 for (i = 0; i <= IO_BITMAP_LONGS; i++)
633 t->io_bitmap[i] = ~0UL;
635 atomic_inc(&init_mm.mm_count);
636 me->active_mm = &init_mm;
639 enter_lazy_tlb(&init_mm, me);
641 load_sp0(t, ¤t->thread);
642 set_tss_desc(cpu, t);
644 load_LDT(&init_mm.context);
648 * If the kgdb is connected no debug regs should be altered. This
649 * is only applicable when KGDB and a KGDB I/O module are built
650 * into the kernel and you are using early debugging with
651 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
653 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
654 arch_kgdb_ops.correct_hw_break();
658 * Clear all 6 debug registers:
661 set_debugreg(0UL, 0);
662 set_debugreg(0UL, 1);
663 set_debugreg(0UL, 2);
664 set_debugreg(0UL, 3);
665 set_debugreg(0UL, 6);
666 set_debugreg(0UL, 7);
668 /* If the kgdb is connected no debug regs should be altered. */
674 raw_local_save_flags(kernel_eflags);