1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
31 #include <asm/pgtable.h>
32 #include <asm/processor.h>
34 #include <asm/atomic.h>
35 #include <asm/proto.h>
36 #include <asm/sections.h>
37 #include <asm/setup.h>
41 static struct cpu_dev *this_cpu __cpuinitdata;
44 /* We need valid kernel segments for data and code in long mode too
45 * IRET will check the segment types kkeil 2000/10/28
46 * Also sysret mandates a special GDT layout
48 /* The TLS descriptors are currently at a different place compared to i386.
49 Hopefully nobody expects them at a fixed place (Wine?) */
50 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
51 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
52 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
53 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
54 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
55 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
56 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
60 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
61 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
62 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
63 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
65 * Segments used for calling PnP BIOS have byte granularity.
66 * They code segments and data segments have fixed 64k limits,
67 * the transfer segment sizes are set at run time.
70 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
72 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
74 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
76 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
78 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
80 * The APM segments have byte granularity and their bases
81 * are set at run time. All have 64k limits.
84 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
86 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
88 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
90 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
91 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
96 static int cachesize_override __cpuinitdata = -1;
97 static int disable_x86_serial_nr __cpuinitdata = 1;
99 static int __init cachesize_setup(char *str)
101 get_option(&str, &cachesize_override);
104 __setup("cachesize=", cachesize_setup);
107 * Naming convention should be: <Name> [(<Codename>)]
108 * This table only is used unless init_<vendor>() below doesn't set it;
109 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
113 /* Look up CPU names by table lookup. */
114 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
116 struct cpu_model_info *info;
118 if (c->x86_model >= 16)
119 return NULL; /* Range check */
124 info = this_cpu->c_models;
126 while (info && info->family) {
127 if (info->family == c->x86)
128 return info->model_names[c->x86_model];
131 return NULL; /* Not found */
134 static int __init x86_fxsr_setup(char *s)
136 setup_clear_cpu_cap(X86_FEATURE_FXSR);
137 setup_clear_cpu_cap(X86_FEATURE_XMM);
140 __setup("nofxsr", x86_fxsr_setup);
142 static int __init x86_sep_setup(char *s)
144 setup_clear_cpu_cap(X86_FEATURE_SEP);
147 __setup("nosep", x86_sep_setup);
149 /* Standard macro to see if a specific flag is changeable */
150 static inline int flag_is_changeable_p(u32 flag)
164 : "=&r" (f1), "=&r" (f2)
167 return ((f1^f2) & flag) != 0;
170 /* Probe for the CPUID instruction */
171 static int __cpuinit have_cpuid_p(void)
173 return flag_is_changeable_p(X86_EFLAGS_ID);
176 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
178 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
179 /* Disable processor serial number */
180 unsigned long lo, hi;
181 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
183 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
184 printk(KERN_NOTICE "CPU serial number disabled.\n");
185 clear_cpu_cap(c, X86_FEATURE_PN);
187 /* Disabling the serial number may affect the cpuid level */
188 c->cpuid_level = cpuid_eax(0);
192 static int __init x86_serial_nr_setup(char *s)
194 disable_x86_serial_nr = 0;
197 __setup("serialnumber", x86_serial_nr_setup);
199 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
201 /* Current gdt points %fs at the "master" per-cpu area: after this,
202 * it's on the real one. */
203 void switch_to_new_gdt(void)
205 struct desc_ptr gdt_descr;
207 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
208 gdt_descr.size = GDT_SIZE - 1;
209 load_gdt(&gdt_descr);
210 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
213 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
215 static void __cpuinit default_init(struct cpuinfo_x86 *c)
217 /* Not much we can do here... */
218 /* Check if at least it has cpuid */
219 if (c->cpuid_level == -1) {
220 /* No cpuid. It must be an ancient CPU */
222 strcpy(c->x86_model_id, "486");
223 else if (c->x86 == 3)
224 strcpy(c->x86_model_id, "386");
228 static struct cpu_dev __cpuinitdata default_cpu = {
229 .c_init = default_init,
230 .c_vendor = "Unknown",
231 .c_x86_vendor = X86_VENDOR_UNKNOWN,
234 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
239 if (c->extended_cpuid_level < 0x80000004)
242 v = (unsigned int *) c->x86_model_id;
243 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
244 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
245 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
246 c->x86_model_id[48] = 0;
248 /* Intel chips right-justify this string for some dumb reason;
249 undo that brain damage */
250 p = q = &c->x86_model_id[0];
256 while (q <= &c->x86_model_id[48])
257 *q++ = '\0'; /* Zero-pad the rest */
263 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
265 unsigned int n, dummy, ebx, ecx, edx, l2size;
267 n = c->extended_cpuid_level;
269 if (n >= 0x80000005) {
270 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
271 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
272 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
273 c->x86_cache_size = (ecx>>24) + (edx>>24);
276 if (n < 0x80000006) /* Some chips just has a large L1. */
279 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
282 /* do processor-specific cache resizing */
283 if (this_cpu->c_size_cache)
284 l2size = this_cpu->c_size_cache(c, l2size);
286 /* Allow user to override all this if necessary. */
287 if (cachesize_override != -1)
288 l2size = cachesize_override;
291 return; /* Again, no L2 cache is possible */
293 c->x86_cache_size = l2size;
295 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
299 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
302 u32 eax, ebx, ecx, edx;
303 int index_msb, core_bits;
305 if (!cpu_has(c, X86_FEATURE_HT))
308 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
311 cpuid(1, &eax, &ebx, &ecx, &edx);
313 smp_num_siblings = (ebx & 0xff0000) >> 16;
315 if (smp_num_siblings == 1) {
316 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
317 } else if (smp_num_siblings > 1) {
319 if (smp_num_siblings > NR_CPUS) {
320 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
322 smp_num_siblings = 1;
326 index_msb = get_count_order(smp_num_siblings);
327 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
330 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
332 index_msb = get_count_order(smp_num_siblings);
334 core_bits = get_count_order(c->x86_max_cores);
336 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
337 ((1 << core_bits) - 1);
341 if ((c->x86_max_cores * smp_num_siblings) > 1) {
342 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
344 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
350 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
352 char *v = c->x86_vendor_id;
356 for (i = 0; i < X86_VENDOR_NUM; i++) {
360 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
361 (cpu_devs[i]->c_ident[1] &&
362 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
363 this_cpu = cpu_devs[i];
364 c->x86_vendor = this_cpu->c_x86_vendor;
371 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
372 printk(KERN_ERR "CPU: Your system may be unstable.\n");
375 c->x86_vendor = X86_VENDOR_UNKNOWN;
376 this_cpu = &default_cpu;
379 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
381 /* Get vendor name */
382 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
383 (unsigned int *)&c->x86_vendor_id[0],
384 (unsigned int *)&c->x86_vendor_id[8],
385 (unsigned int *)&c->x86_vendor_id[4]);
388 /* Intel-defined flags: level 0x00000001 */
389 if (c->cpuid_level >= 0x00000001) {
390 u32 junk, tfms, cap0, misc;
391 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
392 c->x86 = (tfms >> 8) & 0xf;
393 c->x86_model = (tfms >> 4) & 0xf;
394 c->x86_mask = tfms & 0xf;
396 c->x86 += (tfms >> 20) & 0xff;
398 c->x86_model += ((tfms >> 16) & 0xf) << 4;
399 if (cap0 & (1<<19)) {
400 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
401 c->x86_cache_alignment = c->x86_clflush_size;
406 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
411 /* Intel-defined flags: level 0x00000001 */
412 if (c->cpuid_level >= 0x00000001) {
413 u32 capability, excap;
414 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
415 c->x86_capability[0] = capability;
416 c->x86_capability[4] = excap;
419 /* AMD-defined flags: level 0x80000001 */
420 xlvl = cpuid_eax(0x80000000);
421 c->extended_cpuid_level = xlvl;
422 if ((xlvl & 0xffff0000) == 0x80000000) {
423 if (xlvl >= 0x80000001) {
424 c->x86_capability[1] = cpuid_edx(0x80000001);
425 c->x86_capability[6] = cpuid_ecx(0x80000001);
430 * Do minimum CPU detection early.
431 * Fields really needed: vendor, cpuid_level, family, model, mask,
433 * The others are not touched to avoid unwanted side effects.
435 * WARNING: this function is only called on the BP. Don't add code here
436 * that is supposed to run on all CPUs.
438 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
440 c->x86_clflush_size = 32;
441 c->x86_cache_alignment = c->x86_clflush_size;
446 memset(&c->x86_capability, 0, sizeof c->x86_capability);
448 c->extended_cpuid_level = 0;
456 if (this_cpu->c_early_init)
457 this_cpu->c_early_init(c);
459 validate_pat_support(c);
462 void __init early_cpu_init(void)
464 struct cpu_dev **cdev;
467 printk("KERNEL supported cpus:\n");
468 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
469 struct cpu_dev *cpudev = *cdev;
472 if (count >= X86_VENDOR_NUM)
474 cpu_devs[count] = cpudev;
477 for (j = 0; j < 2; j++) {
478 if (!cpudev->c_ident[j])
480 printk(" %s %s\n", cpudev->c_vendor,
485 early_identify_cpu(&boot_cpu_data);
489 * The NOPL instruction is supposed to exist on all CPUs with
490 * family >= 6, unfortunately, that's not true in practice because
491 * of early VIA chips and (more importantly) broken virtualizers that
492 * are not easy to detect. Hence, probe for it based on first
495 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
497 const u32 nopl_signature = 0x888c53b1; /* Random number */
498 u32 has_nopl = nopl_signature;
500 clear_cpu_cap(c, X86_FEATURE_NOPL);
503 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
505 " .section .fixup,\"ax\"\n"
512 if (has_nopl == nopl_signature)
513 set_cpu_cap(c, X86_FEATURE_NOPL);
517 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
522 c->extended_cpuid_level = 0;
530 if (c->cpuid_level >= 0x00000001) {
531 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
533 c->apicid = phys_pkg_id(c->initial_apicid, 0);
534 c->phys_proc_id = c->initial_apicid;
536 c->apicid = c->initial_apicid;
540 if (c->extended_cpuid_level >= 0x80000004)
541 get_model_name(c); /* Default name */
543 init_scattered_cpuid_features(c);
548 * This does the hard work of actually picking apart the CPU stuff...
550 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
554 c->loops_per_jiffy = loops_per_jiffy;
555 c->x86_cache_size = -1;
556 c->x86_vendor = X86_VENDOR_UNKNOWN;
557 c->cpuid_level = -1; /* CPUID not detected */
558 c->x86_model = c->x86_mask = 0; /* So far unknown... */
559 c->x86_vendor_id[0] = '\0'; /* Unset */
560 c->x86_model_id[0] = '\0'; /* Unset */
561 c->x86_max_cores = 1;
562 c->x86_clflush_size = 32;
563 memset(&c->x86_capability, 0, sizeof c->x86_capability);
565 if (!have_cpuid_p()) {
567 * First of all, decide if this is a 486 or higher
568 * It's a 486 if we can modify the AC flag
570 if (flag_is_changeable_p(X86_EFLAGS_AC))
578 if (this_cpu->c_identify)
579 this_cpu->c_identify(c);
582 * Vendor-specific initialization. In this section we
583 * canonicalize the feature flags, meaning if there are
584 * features a certain CPU supports which CPUID doesn't
585 * tell us, CPUID claiming incorrect flags, or other bugs,
586 * we handle them here.
588 * At the end of this section, c->x86_capability better
589 * indicate the features this CPU genuinely supports!
591 if (this_cpu->c_init)
594 /* Disable the PN if appropriate */
595 squash_the_stupid_serial_number(c);
598 * The vendor-specific functions might have changed features. Now
599 * we do "generic changes."
602 /* If the model name is still unset, do table lookup. */
603 if (!c->x86_model_id[0]) {
605 p = table_lookup_model(c);
607 strcpy(c->x86_model_id, p);
610 sprintf(c->x86_model_id, "%02x/%02x",
611 c->x86, c->x86_model);
615 * On SMP, boot_cpu_data holds the common feature set between
616 * all CPUs; so make sure that we indicate which features are
617 * common between the CPUs. The first time this routine gets
618 * executed, c == &boot_cpu_data.
620 if (c != &boot_cpu_data) {
621 /* AND the already accumulated flags with these */
622 for (i = 0; i < NCAPINTS; i++)
623 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
626 /* Clear all flags overriden by options */
627 for (i = 0; i < NCAPINTS; i++)
628 c->x86_capability[i] &= ~cleared_cpu_caps[i];
630 /* Init Machine Check Exception if available. */
633 select_idle_routine(c);
636 void __init identify_boot_cpu(void)
638 identify_cpu(&boot_cpu_data);
643 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
645 BUG_ON(c == &boot_cpu_data);
656 static struct msr_range msr_range_array[] __cpuinitdata = {
657 { 0x00000000, 0x00000418},
658 { 0xc0000000, 0xc000040b},
659 { 0xc0010000, 0xc0010142},
660 { 0xc0011000, 0xc001103b},
663 static void __cpuinit print_cpu_msr(void)
668 unsigned index_min, index_max;
670 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
671 index_min = msr_range_array[i].min;
672 index_max = msr_range_array[i].max;
673 for (index = index_min; index < index_max; index++) {
674 if (rdmsrl_amd_safe(index, &val))
676 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
681 static int show_msr __cpuinitdata;
682 static __init int setup_show_msr(char *arg)
686 get_option(&arg, &num);
692 __setup("show_msr=", setup_show_msr);
694 static __init int setup_noclflush(char *arg)
696 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
699 __setup("noclflush", setup_noclflush);
701 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
705 if (c->x86_vendor < X86_VENDOR_NUM)
706 vendor = this_cpu->c_vendor;
707 else if (c->cpuid_level >= 0)
708 vendor = c->x86_vendor_id;
710 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
711 printk(KERN_CONT "%s ", vendor);
713 if (c->x86_model_id[0])
714 printk(KERN_CONT "%s", c->x86_model_id);
716 printk(KERN_CONT "%d86", c->x86);
718 if (c->x86_mask || c->cpuid_level >= 0)
719 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
721 printk(KERN_CONT "\n");
724 if (c->cpu_index < show_msr)
732 static __init int setup_disablecpuid(char *arg)
735 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
736 setup_clear_cpu_cap(bit);
741 __setup("clearcpuid=", setup_disablecpuid);
743 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
745 /* Make sure %fs is initialized properly in idle threads */
746 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
748 memset(regs, 0, sizeof(struct pt_regs));
749 regs->fs = __KERNEL_PERCPU;
754 * cpu_init() initializes state that is per-CPU. Some data is already
755 * initialized (naturally) in the bootstrap process, such as the GDT
756 * and IDT. We reload them nevertheless, this function acts as a
757 * 'CPU state barrier', nothing should get across.
759 void __cpuinit cpu_init(void)
761 int cpu = smp_processor_id();
762 struct task_struct *curr = current;
763 struct tss_struct *t = &per_cpu(init_tss, cpu);
764 struct thread_struct *thread = &curr->thread;
766 if (cpu_test_and_set(cpu, cpu_initialized)) {
767 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
768 for (;;) local_irq_enable();
771 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
773 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
774 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
776 load_idt(&idt_descr);
780 * Set up and load the per-CPU TSS and LDT
782 atomic_inc(&init_mm.mm_count);
783 curr->active_mm = &init_mm;
786 enter_lazy_tlb(&init_mm, curr);
789 set_tss_desc(cpu, t);
791 load_LDT(&init_mm.context);
793 #ifdef CONFIG_DOUBLEFAULT
794 /* Set up doublefault TSS pointer in the GDT */
795 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
799 asm volatile ("mov %0, %%gs" : : "r" (0));
801 /* Clear all 6 debug registers: */
810 * Force FPU initialization:
813 current_thread_info()->status = TS_XSAVE;
815 current_thread_info()->status = 0;
817 mxcsr_feature_mask_init();
820 * Boot processor to setup the FP and extended state context info.
822 if (!smp_processor_id())
823 init_thread_xstate();
828 #ifdef CONFIG_HOTPLUG_CPU
829 void __cpuinit cpu_uninit(void)
831 int cpu = raw_smp_processor_id();
832 cpu_clear(cpu, cpu_initialized);
835 per_cpu(cpu_tlbstate, cpu).state = 0;
836 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;