1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
31 #include <asm/pgtable.h>
32 #include <asm/processor.h>
34 #include <asm/atomic.h>
35 #include <asm/proto.h>
36 #include <asm/sections.h>
37 #include <asm/setup.h>
41 static struct cpu_dev *this_cpu __cpuinitdata;
44 /* We need valid kernel segments for data and code in long mode too
45 * IRET will check the segment types kkeil 2000/10/28
46 * Also sysret mandates a special GDT layout
48 /* The TLS descriptors are currently at a different place compared to i386.
49 Hopefully nobody expects them at a fixed place (Wine?) */
50 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
51 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
52 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
53 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
54 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
55 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
56 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
60 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
61 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
62 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
63 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
65 * Segments used for calling PnP BIOS have byte granularity.
66 * They code segments and data segments have fixed 64k limits,
67 * the transfer segment sizes are set at run time.
70 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
72 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
74 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
76 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
78 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
80 * The APM segments have byte granularity and their bases
81 * are set at run time. All have 64k limits.
84 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
86 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
88 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
90 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
91 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
97 static int cachesize_override __cpuinitdata = -1;
98 static int disable_x86_serial_nr __cpuinitdata = 1;
100 static int __init cachesize_setup(char *str)
102 get_option(&str, &cachesize_override);
105 __setup("cachesize=", cachesize_setup);
108 * Naming convention should be: <Name> [(<Codename>)]
109 * This table only is used unless init_<vendor>() below doesn't set it;
110 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
114 /* Look up CPU names by table lookup. */
115 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
117 struct cpu_model_info *info;
119 if (c->x86_model >= 16)
120 return NULL; /* Range check */
125 info = this_cpu->c_models;
127 while (info && info->family) {
128 if (info->family == c->x86)
129 return info->model_names[c->x86_model];
132 return NULL; /* Not found */
135 static int __init x86_fxsr_setup(char *s)
137 setup_clear_cpu_cap(X86_FEATURE_FXSR);
138 setup_clear_cpu_cap(X86_FEATURE_XMM);
141 __setup("nofxsr", x86_fxsr_setup);
143 static int __init x86_sep_setup(char *s)
145 setup_clear_cpu_cap(X86_FEATURE_SEP);
148 __setup("nosep", x86_sep_setup);
150 /* Standard macro to see if a specific flag is changeable */
151 static inline int flag_is_changeable_p(u32 flag)
165 : "=&r" (f1), "=&r" (f2)
168 return ((f1^f2) & flag) != 0;
171 /* Probe for the CPUID instruction */
172 static int __cpuinit have_cpuid_p(void)
174 return flag_is_changeable_p(X86_EFLAGS_ID);
177 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
179 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
180 /* Disable processor serial number */
181 unsigned long lo, hi;
182 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
184 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
185 printk(KERN_NOTICE "CPU serial number disabled.\n");
186 clear_cpu_cap(c, X86_FEATURE_PN);
188 /* Disabling the serial number may affect the cpuid level */
189 c->cpuid_level = cpuid_eax(0);
193 static int __init x86_serial_nr_setup(char *s)
195 disable_x86_serial_nr = 0;
198 __setup("serialnumber", x86_serial_nr_setup);
200 /* Probe for the CPUID instruction */
201 static inline int have_cpuid_p(void)
207 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
209 /* Current gdt points %fs at the "master" per-cpu area: after this,
210 * it's on the real one. */
211 void switch_to_new_gdt(void)
213 struct desc_ptr gdt_descr;
215 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
216 gdt_descr.size = GDT_SIZE - 1;
217 load_gdt(&gdt_descr);
219 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
223 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
225 static void __cpuinit default_init(struct cpuinfo_x86 *c)
228 display_cacheinfo(c);
230 /* Not much we can do here... */
231 /* Check if at least it has cpuid */
232 if (c->cpuid_level == -1) {
233 /* No cpuid. It must be an ancient CPU */
235 strcpy(c->x86_model_id, "486");
236 else if (c->x86 == 3)
237 strcpy(c->x86_model_id, "386");
242 static struct cpu_dev __cpuinitdata default_cpu = {
243 .c_init = default_init,
244 .c_vendor = "Unknown",
245 .c_x86_vendor = X86_VENDOR_UNKNOWN,
248 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
253 if (c->extended_cpuid_level < 0x80000004)
256 v = (unsigned int *) c->x86_model_id;
257 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
258 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
259 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
260 c->x86_model_id[48] = 0;
262 /* Intel chips right-justify this string for some dumb reason;
263 undo that brain damage */
264 p = q = &c->x86_model_id[0];
270 while (q <= &c->x86_model_id[48])
271 *q++ = '\0'; /* Zero-pad the rest */
277 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
279 unsigned int n, dummy, ebx, ecx, edx, l2size;
281 n = c->extended_cpuid_level;
283 if (n >= 0x80000005) {
284 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
285 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
286 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
287 c->x86_cache_size = (ecx>>24) + (edx>>24);
289 /* On K8 L1 TLB is inclusive, so don't count it */
294 if (n < 0x80000006) /* Some chips just has a large L1. */
297 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
301 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
303 /* do processor-specific cache resizing */
304 if (this_cpu->c_size_cache)
305 l2size = this_cpu->c_size_cache(c, l2size);
307 /* Allow user to override all this if necessary. */
308 if (cachesize_override != -1)
309 l2size = cachesize_override;
312 return; /* Again, no L2 cache is possible */
315 c->x86_cache_size = l2size;
317 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
321 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
324 u32 eax, ebx, ecx, edx;
325 int index_msb, core_bits;
327 if (!cpu_has(c, X86_FEATURE_HT))
330 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
333 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
336 cpuid(1, &eax, &ebx, &ecx, &edx);
338 smp_num_siblings = (ebx & 0xff0000) >> 16;
340 if (smp_num_siblings == 1) {
341 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
342 } else if (smp_num_siblings > 1) {
344 if (smp_num_siblings > NR_CPUS) {
345 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
347 smp_num_siblings = 1;
351 index_msb = get_count_order(smp_num_siblings);
353 c->phys_proc_id = phys_pkg_id(index_msb);
355 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
358 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
360 index_msb = get_count_order(smp_num_siblings);
362 core_bits = get_count_order(c->x86_max_cores);
365 c->cpu_core_id = phys_pkg_id(index_msb) &
366 ((1 << core_bits) - 1);
368 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
369 ((1 << core_bits) - 1);
374 if ((c->x86_max_cores * smp_num_siblings) > 1) {
375 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
377 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
383 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
385 char *v = c->x86_vendor_id;
389 for (i = 0; i < X86_VENDOR_NUM; i++) {
393 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
394 (cpu_devs[i]->c_ident[1] &&
395 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
396 this_cpu = cpu_devs[i];
397 c->x86_vendor = this_cpu->c_x86_vendor;
404 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
405 printk(KERN_ERR "CPU: Your system may be unstable.\n");
408 c->x86_vendor = X86_VENDOR_UNKNOWN;
409 this_cpu = &default_cpu;
412 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
414 /* Get vendor name */
415 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
416 (unsigned int *)&c->x86_vendor_id[0],
417 (unsigned int *)&c->x86_vendor_id[8],
418 (unsigned int *)&c->x86_vendor_id[4]);
421 /* Intel-defined flags: level 0x00000001 */
422 if (c->cpuid_level >= 0x00000001) {
423 u32 junk, tfms, cap0, misc;
424 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
425 c->x86 = (tfms >> 8) & 0xf;
426 c->x86_model = (tfms >> 4) & 0xf;
427 c->x86_mask = tfms & 0xf;
429 c->x86 += (tfms >> 20) & 0xff;
431 c->x86_model += ((tfms >> 16) & 0xf) << 4;
432 if (cap0 & (1<<19)) {
433 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
434 c->x86_cache_alignment = c->x86_clflush_size;
439 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
444 /* Intel-defined flags: level 0x00000001 */
445 if (c->cpuid_level >= 0x00000001) {
446 u32 capability, excap;
447 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
448 c->x86_capability[0] = capability;
449 c->x86_capability[4] = excap;
452 /* AMD-defined flags: level 0x80000001 */
453 xlvl = cpuid_eax(0x80000000);
454 c->extended_cpuid_level = xlvl;
455 if ((xlvl & 0xffff0000) == 0x80000000) {
456 if (xlvl >= 0x80000001) {
457 c->x86_capability[1] = cpuid_edx(0x80000001);
458 c->x86_capability[6] = cpuid_ecx(0x80000001);
463 /* Transmeta-defined flags: level 0x80860001 */
464 xlvl = cpuid_eax(0x80860000);
465 if ((xlvl & 0xffff0000) == 0x80860000) {
466 /* Don't set x86_cpuid_level here for now to not confuse. */
467 if (xlvl >= 0x80860001)
468 c->x86_capability[2] = cpuid_edx(0x80860001);
471 if (c->extended_cpuid_level >= 0x80000007)
472 c->x86_power = cpuid_edx(0x80000007);
474 if (c->extended_cpuid_level >= 0x80000008) {
475 u32 eax = cpuid_eax(0x80000008);
477 c->x86_virt_bits = (eax >> 8) & 0xff;
478 c->x86_phys_bits = eax & 0xff;
483 * Do minimum CPU detection early.
484 * Fields really needed: vendor, cpuid_level, family, model, mask,
486 * The others are not touched to avoid unwanted side effects.
488 * WARNING: this function is only called on the BP. Don't add code here
489 * that is supposed to run on all CPUs.
491 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
494 c->x86_clflush_size = 64;
496 c->x86_clflush_size = 32;
498 c->x86_cache_alignment = c->x86_clflush_size;
503 memset(&c->x86_capability, 0, sizeof c->x86_capability);
505 c->extended_cpuid_level = 0;
513 if (this_cpu->c_early_init)
514 this_cpu->c_early_init(c);
516 validate_pat_support(c);
519 void __init early_cpu_init(void)
521 struct cpu_dev **cdev;
524 printk("KERNEL supported cpus:\n");
525 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
526 struct cpu_dev *cpudev = *cdev;
529 if (count >= X86_VENDOR_NUM)
531 cpu_devs[count] = cpudev;
534 for (j = 0; j < 2; j++) {
535 if (!cpudev->c_ident[j])
537 printk(" %s %s\n", cpudev->c_vendor,
542 early_identify_cpu(&boot_cpu_data);
546 * The NOPL instruction is supposed to exist on all CPUs with
547 * family >= 6, unfortunately, that's not true in practice because
548 * of early VIA chips and (more importantly) broken virtualizers that
549 * are not easy to detect. Hence, probe for it based on first
552 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
554 const u32 nopl_signature = 0x888c53b1; /* Random number */
555 u32 has_nopl = nopl_signature;
557 clear_cpu_cap(c, X86_FEATURE_NOPL);
560 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
562 " .section .fixup,\"ax\"\n"
569 if (has_nopl == nopl_signature)
570 set_cpu_cap(c, X86_FEATURE_NOPL);
574 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
579 c->extended_cpuid_level = 0;
587 if (c->cpuid_level >= 0x00000001) {
588 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
590 c->apicid = phys_pkg_id(c->initial_apicid, 0);
591 c->phys_proc_id = c->initial_apicid;
593 c->apicid = c->initial_apicid;
597 if (c->extended_cpuid_level >= 0x80000004)
598 get_model_name(c); /* Default name */
600 init_scattered_cpuid_features(c);
605 * This does the hard work of actually picking apart the CPU stuff...
607 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
611 c->loops_per_jiffy = loops_per_jiffy;
612 c->x86_cache_size = -1;
613 c->x86_vendor = X86_VENDOR_UNKNOWN;
614 c->cpuid_level = -1; /* CPUID not detected */
615 c->x86_model = c->x86_mask = 0; /* So far unknown... */
616 c->x86_vendor_id[0] = '\0'; /* Unset */
617 c->x86_model_id[0] = '\0'; /* Unset */
618 c->x86_max_cores = 1;
619 c->x86_clflush_size = 32;
620 memset(&c->x86_capability, 0, sizeof c->x86_capability);
622 if (!have_cpuid_p()) {
624 * First of all, decide if this is a 486 or higher
625 * It's a 486 if we can modify the AC flag
627 if (flag_is_changeable_p(X86_EFLAGS_AC))
635 if (this_cpu->c_identify)
636 this_cpu->c_identify(c);
639 * Vendor-specific initialization. In this section we
640 * canonicalize the feature flags, meaning if there are
641 * features a certain CPU supports which CPUID doesn't
642 * tell us, CPUID claiming incorrect flags, or other bugs,
643 * we handle them here.
645 * At the end of this section, c->x86_capability better
646 * indicate the features this CPU genuinely supports!
648 if (this_cpu->c_init)
651 /* Disable the PN if appropriate */
652 squash_the_stupid_serial_number(c);
655 * The vendor-specific functions might have changed features. Now
656 * we do "generic changes."
659 /* If the model name is still unset, do table lookup. */
660 if (!c->x86_model_id[0]) {
662 p = table_lookup_model(c);
664 strcpy(c->x86_model_id, p);
667 sprintf(c->x86_model_id, "%02x/%02x",
668 c->x86, c->x86_model);
672 * On SMP, boot_cpu_data holds the common feature set between
673 * all CPUs; so make sure that we indicate which features are
674 * common between the CPUs. The first time this routine gets
675 * executed, c == &boot_cpu_data.
677 if (c != &boot_cpu_data) {
678 /* AND the already accumulated flags with these */
679 for (i = 0; i < NCAPINTS; i++)
680 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
683 /* Clear all flags overriden by options */
684 for (i = 0; i < NCAPINTS; i++)
685 c->x86_capability[i] &= ~cleared_cpu_caps[i];
687 /* Init Machine Check Exception if available. */
690 select_idle_routine(c);
693 void __init identify_boot_cpu(void)
695 identify_cpu(&boot_cpu_data);
700 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
702 BUG_ON(c == &boot_cpu_data);
713 static struct msr_range msr_range_array[] __cpuinitdata = {
714 { 0x00000000, 0x00000418},
715 { 0xc0000000, 0xc000040b},
716 { 0xc0010000, 0xc0010142},
717 { 0xc0011000, 0xc001103b},
720 static void __cpuinit print_cpu_msr(void)
725 unsigned index_min, index_max;
727 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
728 index_min = msr_range_array[i].min;
729 index_max = msr_range_array[i].max;
730 for (index = index_min; index < index_max; index++) {
731 if (rdmsrl_amd_safe(index, &val))
733 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
738 static int show_msr __cpuinitdata;
739 static __init int setup_show_msr(char *arg)
743 get_option(&arg, &num);
749 __setup("show_msr=", setup_show_msr);
751 static __init int setup_noclflush(char *arg)
753 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
756 __setup("noclflush", setup_noclflush);
758 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
762 if (c->x86_vendor < X86_VENDOR_NUM)
763 vendor = this_cpu->c_vendor;
764 else if (c->cpuid_level >= 0)
765 vendor = c->x86_vendor_id;
767 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
768 printk(KERN_CONT "%s ", vendor);
770 if (c->x86_model_id[0])
771 printk(KERN_CONT "%s", c->x86_model_id);
773 printk(KERN_CONT "%d86", c->x86);
775 if (c->x86_mask || c->cpuid_level >= 0)
776 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
778 printk(KERN_CONT "\n");
781 if (c->cpu_index < show_msr)
789 static __init int setup_disablecpuid(char *arg)
792 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
793 setup_clear_cpu_cap(bit);
798 __setup("clearcpuid=", setup_disablecpuid);
800 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
803 struct x8664_pda **_cpu_pda __read_mostly;
804 EXPORT_SYMBOL(_cpu_pda);
806 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
808 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
810 unsigned long __supported_pte_mask __read_mostly = ~0UL;
811 EXPORT_SYMBOL_GPL(__supported_pte_mask);
813 static int do_not_nx __cpuinitdata;
816 Control non executable mappings for 64bit processes.
821 static int __init nonx_setup(char *str)
825 if (!strncmp(str, "on", 2)) {
826 __supported_pte_mask |= _PAGE_NX;
828 } else if (!strncmp(str, "off", 3)) {
830 __supported_pte_mask &= ~_PAGE_NX;
834 early_param("noexec", nonx_setup);
836 int force_personality32;
839 Control non executable heap for 32bit processes.
840 To control the stack too use noexec=off
842 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
843 off PROT_READ implies PROT_EXEC
845 static int __init nonx32_setup(char *str)
847 if (!strcmp(str, "on"))
848 force_personality32 &= ~READ_IMPLIES_EXEC;
849 else if (!strcmp(str, "off"))
850 force_personality32 |= READ_IMPLIES_EXEC;
853 __setup("noexec32=", nonx32_setup);
855 void pda_init(int cpu)
857 struct x8664_pda *pda = cpu_pda(cpu);
859 /* Setup up data that may be needed in __get_free_pages early */
862 /* Memory clobbers used to order PDA accessed */
864 wrmsrl(MSR_GS_BASE, pda);
867 pda->cpunumber = cpu;
869 pda->kernelstack = (unsigned long)stack_thread_info() -
870 PDA_STACKOFFSET + THREAD_SIZE;
871 pda->active_mm = &init_mm;
875 /* others are initialized in smpboot.c */
876 pda->pcurrent = &init_task;
877 pda->irqstackptr = boot_cpu_stack;
878 pda->irqstackptr += IRQSTACKSIZE - 64;
880 if (!pda->irqstackptr) {
881 pda->irqstackptr = (char *)
882 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
883 if (!pda->irqstackptr)
884 panic("cannot allocate irqstack for cpu %d",
886 pda->irqstackptr += IRQSTACKSIZE - 64;
889 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
890 pda->nodenumber = cpu_to_node(cpu);
894 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
895 DEBUG_STKSZ] __page_aligned_bss;
897 extern asmlinkage void ignore_sysret(void);
899 /* May not be marked __init: used by software suspend */
900 void syscall_init(void)
903 * LSTAR and STAR live in a bit strange symbiosis.
904 * They both write to the same internal register. STAR allows to
905 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
907 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
908 wrmsrl(MSR_LSTAR, system_call);
909 wrmsrl(MSR_CSTAR, ignore_sysret);
911 #ifdef CONFIG_IA32_EMULATION
912 syscall32_cpu_init();
915 /* Flags to clear on syscall */
916 wrmsrl(MSR_SYSCALL_MASK,
917 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
920 void __cpuinit check_efer(void)
924 rdmsrl(MSR_EFER, efer);
925 if (!(efer & EFER_NX) || do_not_nx)
926 __supported_pte_mask &= ~_PAGE_NX;
929 unsigned long kernel_eflags;
932 * Copies of the original ist values from the tss are only accessed during
933 * debugging, no special alignment required.
935 DEFINE_PER_CPU(struct orig_ist, orig_ist);
939 /* Make sure %fs is initialized properly in idle threads */
940 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
942 memset(regs, 0, sizeof(struct pt_regs));
943 regs->fs = __KERNEL_PERCPU;
949 * cpu_init() initializes state that is per-CPU. Some data is already
950 * initialized (naturally) in the bootstrap process, such as the GDT
951 * and IDT. We reload them nevertheless, this function acts as a
952 * 'CPU state barrier', nothing should get across.
953 * A lot of state is already set up in PDA init for 64 bit
956 void __cpuinit cpu_init(void)
958 int cpu = stack_smp_processor_id();
959 struct tss_struct *t = &per_cpu(init_tss, cpu);
960 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
962 char *estacks = NULL;
963 struct task_struct *me;
966 /* CPU 0 is initialised in head64.c */
970 estacks = boot_exception_stacks;
974 if (cpu_test_and_set(cpu, cpu_initialized))
975 panic("CPU#%d already initialized!\n", cpu);
977 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
979 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
982 * Initialize the per-CPU GDT with the boot GDT,
983 * and set up the GDT descriptor:
987 load_idt((const struct desc_ptr *)&idt_descr);
989 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
992 wrmsrl(MSR_FS_BASE, 0);
993 wrmsrl(MSR_KERNEL_GS_BASE, 0);
997 if (cpu != 0 && x2apic)
1001 * set up and load the per-CPU TSS
1003 if (!orig_ist->ist[0]) {
1004 static const unsigned int order[N_EXCEPTION_STACKS] = {
1005 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1006 [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1008 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1010 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1012 panic("Cannot allocate exception "
1013 "stack %ld %d\n", v, cpu);
1015 estacks += PAGE_SIZE << order[v];
1016 orig_ist->ist[v] = t->x86_tss.ist[v] =
1017 (unsigned long)estacks;
1021 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1023 * <= is required because the CPU will access up to
1024 * 8 bits beyond the end of the IO permission bitmap.
1026 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1027 t->io_bitmap[i] = ~0UL;
1029 atomic_inc(&init_mm.mm_count);
1030 me->active_mm = &init_mm;
1033 enter_lazy_tlb(&init_mm, me);
1035 load_sp0(t, ¤t->thread);
1036 set_tss_desc(cpu, t);
1038 load_LDT(&init_mm.context);
1042 * If the kgdb is connected no debug regs should be altered. This
1043 * is only applicable when KGDB and a KGDB I/O module are built
1044 * into the kernel and you are using early debugging with
1045 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1047 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1048 arch_kgdb_ops.correct_hw_break();
1052 * Clear all 6 debug registers:
1055 set_debugreg(0UL, 0);
1056 set_debugreg(0UL, 1);
1057 set_debugreg(0UL, 2);
1058 set_debugreg(0UL, 3);
1059 set_debugreg(0UL, 6);
1060 set_debugreg(0UL, 7);
1062 /* If the kgdb is connected no debug regs should be altered. */
1068 raw_local_save_flags(kernel_eflags);
1076 void __cpuinit cpu_init(void)
1078 int cpu = smp_processor_id();
1079 struct task_struct *curr = current;
1080 struct tss_struct *t = &per_cpu(init_tss, cpu);
1081 struct thread_struct *thread = &curr->thread;
1083 if (cpu_test_and_set(cpu, cpu_initialized)) {
1084 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1085 for (;;) local_irq_enable();
1088 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1090 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1091 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1093 load_idt(&idt_descr);
1094 switch_to_new_gdt();
1097 * Set up and load the per-CPU TSS and LDT
1099 atomic_inc(&init_mm.mm_count);
1100 curr->active_mm = &init_mm;
1103 enter_lazy_tlb(&init_mm, curr);
1105 load_sp0(t, thread);
1106 set_tss_desc(cpu, t);
1108 load_LDT(&init_mm.context);
1110 #ifdef CONFIG_DOUBLEFAULT
1111 /* Set up doublefault TSS pointer in the GDT */
1112 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1116 asm volatile ("mov %0, %%gs" : : "r" (0));
1118 /* Clear all 6 debug registers: */
1127 * Force FPU initialization:
1130 current_thread_info()->status = TS_XSAVE;
1132 current_thread_info()->status = 0;
1134 mxcsr_feature_mask_init();
1137 * Boot processor to setup the FP and extended state context info.
1139 if (!smp_processor_id())
1140 init_thread_xstate();
1145 #ifdef CONFIG_HOTPLUG_CPU
1146 void __cpuinit cpu_uninit(void)
1148 int cpu = raw_smp_processor_id();
1149 cpu_clear(cpu, cpu_initialized);
1151 /* lazy TLB state */
1152 per_cpu(cpu_tlbstate, cpu).state = 0;
1153 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;