1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
25 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
26 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
27 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
28 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
29 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
31 * Segments used for calling PnP BIOS have byte granularity.
32 * They code segments and data segments have fixed 64k limits,
33 * the transfer segment sizes are set at run time.
36 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
38 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
40 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
42 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
44 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
46 * The APM segments have byte granularity and their bases
47 * are set at run time. All have 64k limits.
50 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
52 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
54 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
56 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
57 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
59 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
61 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
63 static int cachesize_override __cpuinitdata = -1;
64 static int disable_x86_serial_nr __cpuinitdata = 1;
66 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
68 static void __cpuinit default_init(struct cpuinfo_x86 *c)
70 /* Not much we can do here... */
71 /* Check if at least it has cpuid */
72 if (c->cpuid_level == -1) {
73 /* No cpuid. It must be an ancient CPU */
75 strcpy(c->x86_model_id, "486");
77 strcpy(c->x86_model_id, "386");
81 static struct cpu_dev __cpuinitdata default_cpu = {
82 .c_init = default_init,
83 .c_vendor = "Unknown",
85 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
87 static int __init cachesize_setup(char *str)
89 get_option(&str, &cachesize_override);
92 __setup("cachesize=", cachesize_setup);
94 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
99 if (c->extended_cpuid_level < 0x80000004)
102 v = (unsigned int *) c->x86_model_id;
103 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
104 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
105 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
106 c->x86_model_id[48] = 0;
108 /* Intel chips right-justify this string for some dumb reason;
109 undo that brain damage */
110 p = q = &c->x86_model_id[0];
116 while (q <= &c->x86_model_id[48])
117 *q++ = '\0'; /* Zero-pad the rest */
124 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
126 unsigned int n, dummy, ecx, edx, l2size;
128 n = c->extended_cpuid_level;
130 if (n >= 0x80000005) {
131 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
132 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
133 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
134 c->x86_cache_size = (ecx>>24)+(edx>>24);
137 if (n < 0x80000006) /* Some chips just has a large L1. */
140 ecx = cpuid_ecx(0x80000006);
143 /* do processor-specific cache resizing */
144 if (this_cpu->c_size_cache)
145 l2size = this_cpu->c_size_cache(c, l2size);
147 /* Allow user to override all this if necessary. */
148 if (cachesize_override != -1)
149 l2size = cachesize_override;
152 return; /* Again, no L2 cache is possible */
154 c->x86_cache_size = l2size;
156 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
161 * Naming convention should be: <Name> [(<Codename>)]
162 * This table only is used unless init_<vendor>() below doesn't set it;
163 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
167 /* Look up CPU names by table lookup. */
168 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
170 struct cpu_model_info *info;
172 if (c->x86_model >= 16)
173 return NULL; /* Range check */
178 info = this_cpu->c_models;
180 while (info && info->family) {
181 if (info->family == c->x86)
182 return info->model_names[c->x86_model];
185 return NULL; /* Not found */
189 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
191 char *v = c->x86_vendor_id;
195 for (i = 0; i < X86_VENDOR_NUM; i++) {
197 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
198 (cpu_devs[i]->c_ident[1] &&
199 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
201 this_cpu = cpu_devs[i];
208 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
209 printk(KERN_ERR "CPU: Your system may be unstable.\n");
211 c->x86_vendor = X86_VENDOR_UNKNOWN;
212 this_cpu = &default_cpu;
216 static int __init x86_fxsr_setup(char *s)
218 setup_clear_cpu_cap(X86_FEATURE_FXSR);
219 setup_clear_cpu_cap(X86_FEATURE_XMM);
222 __setup("nofxsr", x86_fxsr_setup);
225 static int __init x86_sep_setup(char *s)
227 setup_clear_cpu_cap(X86_FEATURE_SEP);
230 __setup("nosep", x86_sep_setup);
233 /* Standard macro to see if a specific flag is changeable */
234 static inline int flag_is_changeable_p(u32 flag)
248 : "=&r" (f1), "=&r" (f2)
251 return ((f1^f2) & flag) != 0;
255 /* Probe for the CPUID instruction */
256 static int __cpuinit have_cpuid_p(void)
258 return flag_is_changeable_p(X86_EFLAGS_ID);
261 void __init cpu_detect(struct cpuinfo_x86 *c)
263 /* Get vendor name */
264 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
265 (unsigned int *)&c->x86_vendor_id[0],
266 (unsigned int *)&c->x86_vendor_id[8],
267 (unsigned int *)&c->x86_vendor_id[4]);
270 if (c->cpuid_level >= 0x00000001) {
271 u32 junk, tfms, cap0, misc;
272 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
273 c->x86 = (tfms >> 8) & 15;
274 c->x86_model = (tfms >> 4) & 15;
276 c->x86 += (tfms >> 20) & 0xff;
278 c->x86_model += ((tfms >> 16) & 0xF) << 4;
279 c->x86_mask = tfms & 15;
280 if (cap0 & (1<<19)) {
281 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
282 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
287 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
292 /* Intel-defined flags: level 0x00000001 */
293 if (c->cpuid_level >= 0x00000001) {
294 u32 capability, excap;
295 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
296 c->x86_capability[0] = capability;
297 c->x86_capability[4] = excap;
300 /* AMD-defined flags: level 0x80000001 */
301 xlvl = cpuid_eax(0x80000000);
302 c->extended_cpuid_level = xlvl;
303 if ((xlvl & 0xffff0000) == 0x80000000) {
304 if (xlvl >= 0x80000001) {
305 c->x86_capability[1] = cpuid_edx(0x80000001);
306 c->x86_capability[6] = cpuid_ecx(0x80000001);
311 * Do minimum CPU detection early.
312 * Fields really needed: vendor, cpuid_level, family, model, mask,
314 * The others are not touched to avoid unwanted side effects.
316 * WARNING: this function is only called on the BP. Don't add code here
317 * that is supposed to run on all CPUs.
319 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
321 c->x86_cache_alignment = 32;
322 c->x86_clflush_size = 32;
327 c->extended_cpuid_level = 0;
329 memset(&c->x86_capability, 0, sizeof c->x86_capability);
337 if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
338 cpu_devs[c->x86_vendor]->c_early_init)
339 cpu_devs[c->x86_vendor]->c_early_init(c);
341 validate_pat_support(c);
345 * The NOPL instruction is supposed to exist on all CPUs with
346 * family >= 6, unfortunately, that's not true in practice because
347 * of early VIA chips and (more importantly) broken virtualizers that
348 * are not easy to detect. Hence, probe for it based on first
351 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
353 const u32 nopl_signature = 0x888c53b1; /* Random number */
354 u32 has_nopl = nopl_signature;
356 clear_cpu_cap(c, X86_FEATURE_NOPL);
359 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
361 " .section .fixup,\"ax\"\n"
368 if (has_nopl == nopl_signature)
369 set_cpu_cap(c, X86_FEATURE_NOPL);
373 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
378 c->extended_cpuid_level = 0;
386 if (c->cpuid_level >= 0x00000001) {
387 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
389 c->apicid = phys_pkg_id(c->initial_apicid, 0);
390 c->phys_proc_id = c->initial_apicid;
392 c->apicid = c->initial_apicid;
396 if (c->extended_cpuid_level >= 0x80000004)
397 get_model_name(c); /* Default name */
399 init_scattered_cpuid_features(c);
403 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
405 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
406 /* Disable processor serial number */
407 unsigned long lo, hi;
408 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
410 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
411 printk(KERN_NOTICE "CPU serial number disabled.\n");
412 clear_cpu_cap(c, X86_FEATURE_PN);
414 /* Disabling the serial number may affect the cpuid level */
415 c->cpuid_level = cpuid_eax(0);
419 static int __init x86_serial_nr_setup(char *s)
421 disable_x86_serial_nr = 0;
424 __setup("serialnumber", x86_serial_nr_setup);
429 * This does the hard work of actually picking apart the CPU stuff...
431 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
435 c->loops_per_jiffy = loops_per_jiffy;
436 c->x86_cache_size = -1;
437 c->x86_vendor = X86_VENDOR_UNKNOWN;
438 c->cpuid_level = -1; /* CPUID not detected */
439 c->x86_model = c->x86_mask = 0; /* So far unknown... */
440 c->x86_vendor_id[0] = '\0'; /* Unset */
441 c->x86_model_id[0] = '\0'; /* Unset */
442 c->x86_max_cores = 1;
443 c->x86_clflush_size = 32;
444 memset(&c->x86_capability, 0, sizeof c->x86_capability);
446 if (!have_cpuid_p()) {
448 * First of all, decide if this is a 486 or higher
449 * It's a 486 if we can modify the AC flag
451 if (flag_is_changeable_p(X86_EFLAGS_AC))
459 if (this_cpu->c_identify)
460 this_cpu->c_identify(c);
463 * Vendor-specific initialization. In this section we
464 * canonicalize the feature flags, meaning if there are
465 * features a certain CPU supports which CPUID doesn't
466 * tell us, CPUID claiming incorrect flags, or other bugs,
467 * we handle them here.
469 * At the end of this section, c->x86_capability better
470 * indicate the features this CPU genuinely supports!
472 if (this_cpu->c_init)
475 /* Disable the PN if appropriate */
476 squash_the_stupid_serial_number(c);
479 * The vendor-specific functions might have changed features. Now
480 * we do "generic changes."
483 /* If the model name is still unset, do table lookup. */
484 if (!c->x86_model_id[0]) {
486 p = table_lookup_model(c);
488 strcpy(c->x86_model_id, p);
491 sprintf(c->x86_model_id, "%02x/%02x",
492 c->x86, c->x86_model);
496 * On SMP, boot_cpu_data holds the common feature set between
497 * all CPUs; so make sure that we indicate which features are
498 * common between the CPUs. The first time this routine gets
499 * executed, c == &boot_cpu_data.
501 if (c != &boot_cpu_data) {
502 /* AND the already accumulated flags with these */
503 for (i = 0 ; i < NCAPINTS ; i++)
504 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
507 /* Clear all flags overriden by options */
508 for (i = 0; i < NCAPINTS; i++)
509 c->x86_capability[i] &= ~cleared_cpu_caps[i];
511 /* Init Machine Check Exception if available. */
514 select_idle_routine(c);
517 void __init identify_boot_cpu(void)
519 identify_cpu(&boot_cpu_data);
524 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
526 BUG_ON(c == &boot_cpu_data);
533 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
535 u32 eax, ebx, ecx, edx;
536 int index_msb, core_bits;
538 cpuid(1, &eax, &ebx, &ecx, &edx);
540 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
543 smp_num_siblings = (ebx & 0xff0000) >> 16;
545 if (smp_num_siblings == 1) {
546 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
547 } else if (smp_num_siblings > 1) {
549 if (smp_num_siblings > NR_CPUS) {
550 printk(KERN_WARNING "CPU: Unsupported number of the "
551 "siblings %d", smp_num_siblings);
552 smp_num_siblings = 1;
556 index_msb = get_count_order(smp_num_siblings);
557 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
559 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
562 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
564 index_msb = get_count_order(smp_num_siblings) ;
566 core_bits = get_count_order(c->x86_max_cores);
568 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
569 ((1 << core_bits) - 1);
571 if (c->x86_max_cores > 1)
572 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
578 static __init int setup_noclflush(char *arg)
580 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
583 __setup("noclflush", setup_noclflush);
585 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
589 if (c->x86_vendor < X86_VENDOR_NUM)
590 vendor = this_cpu->c_vendor;
591 else if (c->cpuid_level >= 0)
592 vendor = c->x86_vendor_id;
594 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
595 printk("%s ", vendor);
597 if (!c->x86_model_id[0])
598 printk("%d86", c->x86);
600 printk("%s", c->x86_model_id);
602 if (c->x86_mask || c->cpuid_level >= 0)
603 printk(" stepping %02x\n", c->x86_mask);
608 static __init int setup_disablecpuid(char *arg)
611 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
612 setup_clear_cpu_cap(bit);
617 __setup("clearcpuid=", setup_disablecpuid);
619 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
621 void __init early_cpu_init(void)
623 struct cpu_vendor_dev *cvdev;
625 for (cvdev = __x86cpuvendor_start; cvdev < __x86cpuvendor_end; cvdev++)
626 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
628 early_identify_cpu(&boot_cpu_data);
631 /* Make sure %fs is initialized properly in idle threads */
632 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
634 memset(regs, 0, sizeof(struct pt_regs));
635 regs->fs = __KERNEL_PERCPU;
639 /* Current gdt points %fs at the "master" per-cpu area: after this,
640 * it's on the real one. */
641 void switch_to_new_gdt(void)
643 struct desc_ptr gdt_descr;
645 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
646 gdt_descr.size = GDT_SIZE - 1;
647 load_gdt(&gdt_descr);
648 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
652 * cpu_init() initializes state that is per-CPU. Some data is already
653 * initialized (naturally) in the bootstrap process, such as the GDT
654 * and IDT. We reload them nevertheless, this function acts as a
655 * 'CPU state barrier', nothing should get across.
657 void __cpuinit cpu_init(void)
659 int cpu = smp_processor_id();
660 struct task_struct *curr = current;
661 struct tss_struct *t = &per_cpu(init_tss, cpu);
662 struct thread_struct *thread = &curr->thread;
664 if (cpu_test_and_set(cpu, cpu_initialized)) {
665 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
666 for (;;) local_irq_enable();
669 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
671 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
672 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
674 load_idt(&idt_descr);
678 * Set up and load the per-CPU TSS and LDT
680 atomic_inc(&init_mm.mm_count);
681 curr->active_mm = &init_mm;
684 enter_lazy_tlb(&init_mm, curr);
687 set_tss_desc(cpu, t);
689 load_LDT(&init_mm.context);
691 #ifdef CONFIG_DOUBLEFAULT
692 /* Set up doublefault TSS pointer in the GDT */
693 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
697 asm volatile ("mov %0, %%gs" : : "r" (0));
699 /* Clear all 6 debug registers: */
708 * Force FPU initialization:
710 current_thread_info()->status = 0;
712 mxcsr_feature_mask_init();
715 #ifdef CONFIG_HOTPLUG_CPU
716 void __cpuinit cpu_uninit(void)
718 int cpu = raw_smp_processor_id();
719 cpu_clear(cpu, cpu_initialized);
722 per_cpu(cpu_tlbstate, cpu).state = 0;
723 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;