1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
24 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
25 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
26 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
27 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
28 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
30 * Segments used for calling PnP BIOS have byte granularity.
31 * They code segments and data segments have fixed 64k limits,
32 * the transfer segment sizes are set at run time.
35 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
37 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
39 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
41 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
43 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
45 * The APM segments have byte granularity and their bases
46 * are set at run time. All have 64k limits.
49 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
51 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
53 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
55 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
56 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
58 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
60 static int cachesize_override __cpuinitdata = -1;
61 static int disable_x86_fxsr __cpuinitdata;
62 static int disable_x86_serial_nr __cpuinitdata = 1;
63 static int disable_x86_sep __cpuinitdata;
65 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
67 extern int disable_pse;
69 static void __cpuinit default_init(struct cpuinfo_x86 * c)
71 /* Not much we can do here... */
72 /* Check if at least it has cpuid */
73 if (c->cpuid_level == -1) {
74 /* No cpuid. It must be an ancient CPU */
76 strcpy(c->x86_model_id, "486");
78 strcpy(c->x86_model_id, "386");
82 static struct cpu_dev __cpuinitdata default_cpu = {
83 .c_init = default_init,
84 .c_vendor = "Unknown",
86 static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu;
88 static int __init cachesize_setup(char *str)
90 get_option (&str, &cachesize_override);
93 __setup("cachesize=", cachesize_setup);
95 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
100 if (cpuid_eax(0x80000000) < 0x80000004)
103 v = (unsigned int *) c->x86_model_id;
104 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
105 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
106 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
107 c->x86_model_id[48] = 0;
109 /* Intel chips right-justify this string for some dumb reason;
110 undo that brain damage */
111 p = q = &c->x86_model_id[0];
117 while ( q <= &c->x86_model_id[48] )
118 *q++ = '\0'; /* Zero-pad the rest */
125 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
127 unsigned int n, dummy, ecx, edx, l2size;
129 n = cpuid_eax(0x80000000);
131 if (n >= 0x80000005) {
132 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
133 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
134 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
135 c->x86_cache_size=(ecx>>24)+(edx>>24);
138 if (n < 0x80000006) /* Some chips just has a large L1. */
141 ecx = cpuid_ecx(0x80000006);
144 /* do processor-specific cache resizing */
145 if (this_cpu->c_size_cache)
146 l2size = this_cpu->c_size_cache(c,l2size);
148 /* Allow user to override all this if necessary. */
149 if (cachesize_override != -1)
150 l2size = cachesize_override;
153 return; /* Again, no L2 cache is possible */
155 c->x86_cache_size = l2size;
157 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
161 /* Naming convention should be: <Name> [(<Codename>)] */
162 /* This table only is used unless init_<vendor>() below doesn't set it; */
163 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
165 /* Look up CPU names by table lookup. */
166 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
168 struct cpu_model_info *info;
170 if ( c->x86_model >= 16 )
171 return NULL; /* Range check */
176 info = this_cpu->c_models;
178 while (info && info->family) {
179 if (info->family == c->x86)
180 return info->model_names[c->x86_model];
183 return NULL; /* Not found */
187 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
189 char *v = c->x86_vendor_id;
193 for (i = 0; i < X86_VENDOR_NUM; i++) {
195 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
196 (cpu_devs[i]->c_ident[1] &&
197 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
200 this_cpu = cpu_devs[i];
207 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
208 printk(KERN_ERR "CPU: Your system may be unstable.\n");
210 c->x86_vendor = X86_VENDOR_UNKNOWN;
211 this_cpu = &default_cpu;
215 static int __init x86_fxsr_setup(char * s)
217 /* Tell all the other CPUs to not use it... */
218 disable_x86_fxsr = 1;
221 * ... and clear the bits early in the boot_cpu_data
222 * so that the bootup process doesn't try to do this
225 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
226 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
229 __setup("nofxsr", x86_fxsr_setup);
232 static int __init x86_sep_setup(char * s)
237 __setup("nosep", x86_sep_setup);
240 /* Standard macro to see if a specific flag is changeable */
241 static inline int flag_is_changeable_p(u32 flag)
255 : "=&r" (f1), "=&r" (f2)
258 return ((f1^f2) & flag) != 0;
262 /* Probe for the CPUID instruction */
263 static int __cpuinit have_cpuid_p(void)
265 return flag_is_changeable_p(X86_EFLAGS_ID);
268 void __init cpu_detect(struct cpuinfo_x86 *c)
270 /* Get vendor name */
271 cpuid(0x00000000, &c->cpuid_level,
272 (int *)&c->x86_vendor_id[0],
273 (int *)&c->x86_vendor_id[8],
274 (int *)&c->x86_vendor_id[4]);
277 if (c->cpuid_level >= 0x00000001) {
278 u32 junk, tfms, cap0, misc;
279 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
280 c->x86 = (tfms >> 8) & 15;
281 c->x86_model = (tfms >> 4) & 15;
283 c->x86 += (tfms >> 20) & 0xff;
285 c->x86_model += ((tfms >> 16) & 0xF) << 4;
286 c->x86_mask = tfms & 15;
288 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
292 /* Do minimum CPU detection early.
293 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
294 The others are not touched to avoid unwanted side effects.
296 WARNING: this function is only called on the BP. Don't add code here
297 that is supposed to run on all CPUs. */
298 static void __init early_cpu_detect(void)
300 struct cpuinfo_x86 *c = &boot_cpu_data;
302 c->x86_cache_alignment = 32;
309 get_cpu_vendor(c, 1);
311 switch (c->x86_vendor) {
315 case X86_VENDOR_INTEL:
321 static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
326 if (have_cpuid_p()) {
327 /* Get vendor name */
328 cpuid(0x00000000, &c->cpuid_level,
329 (int *)&c->x86_vendor_id[0],
330 (int *)&c->x86_vendor_id[8],
331 (int *)&c->x86_vendor_id[4]);
333 get_cpu_vendor(c, 0);
334 /* Initialize the standard set of capabilities */
335 /* Note that the vendor-specific code below might override */
337 /* Intel-defined flags: level 0x00000001 */
338 if ( c->cpuid_level >= 0x00000001 ) {
339 u32 capability, excap;
340 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
341 c->x86_capability[0] = capability;
342 c->x86_capability[4] = excap;
343 c->x86 = (tfms >> 8) & 15;
344 c->x86_model = (tfms >> 4) & 15;
346 c->x86 += (tfms >> 20) & 0xff;
348 c->x86_model += ((tfms >> 16) & 0xF) << 4;
349 c->x86_mask = tfms & 15;
351 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
353 c->apicid = (ebx >> 24) & 0xFF;
355 if (c->x86_capability[0] & (1<<19))
356 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
358 /* Have CPUID level 0 only - unheard of */
362 /* AMD-defined flags: level 0x80000001 */
363 xlvl = cpuid_eax(0x80000000);
364 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
365 if ( xlvl >= 0x80000001 ) {
366 c->x86_capability[1] = cpuid_edx(0x80000001);
367 c->x86_capability[6] = cpuid_ecx(0x80000001);
369 if ( xlvl >= 0x80000004 )
370 get_model_name(c); /* Default name */
373 init_scattered_cpuid_features(c);
377 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
381 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
383 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
384 /* Disable processor serial number */
386 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
388 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
389 printk(KERN_NOTICE "CPU serial number disabled.\n");
390 clear_bit(X86_FEATURE_PN, c->x86_capability);
392 /* Disabling the serial number may affect the cpuid level */
393 c->cpuid_level = cpuid_eax(0);
397 static int __init x86_serial_nr_setup(char *s)
399 disable_x86_serial_nr = 0;
402 __setup("serialnumber", x86_serial_nr_setup);
407 * This does the hard work of actually picking apart the CPU stuff...
409 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
413 c->loops_per_jiffy = loops_per_jiffy;
414 c->x86_cache_size = -1;
415 c->x86_vendor = X86_VENDOR_UNKNOWN;
416 c->cpuid_level = -1; /* CPUID not detected */
417 c->x86_model = c->x86_mask = 0; /* So far unknown... */
418 c->x86_vendor_id[0] = '\0'; /* Unset */
419 c->x86_model_id[0] = '\0'; /* Unset */
420 c->x86_max_cores = 1;
421 c->x86_clflush_size = 32;
422 memset(&c->x86_capability, 0, sizeof c->x86_capability);
424 if (!have_cpuid_p()) {
425 /* First of all, decide if this is a 486 or higher */
426 /* It's a 486 if we can modify the AC flag */
427 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
435 printk(KERN_DEBUG "CPU: After generic identify, caps:");
436 for (i = 0; i < NCAPINTS; i++)
437 printk(" %08x", c->x86_capability[i]);
440 if (this_cpu->c_identify) {
441 this_cpu->c_identify(c);
443 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
444 for (i = 0; i < NCAPINTS; i++)
445 printk(" %08x", c->x86_capability[i]);
450 * Vendor-specific initialization. In this section we
451 * canonicalize the feature flags, meaning if there are
452 * features a certain CPU supports which CPUID doesn't
453 * tell us, CPUID claiming incorrect flags, or other bugs,
454 * we handle them here.
456 * At the end of this section, c->x86_capability better
457 * indicate the features this CPU genuinely supports!
459 if (this_cpu->c_init)
462 /* Disable the PN if appropriate */
463 squash_the_stupid_serial_number(c);
466 * The vendor-specific functions might have changed features. Now
467 * we do "generic changes."
472 clear_bit(X86_FEATURE_TSC, c->x86_capability);
475 if (disable_x86_fxsr) {
476 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
477 clear_bit(X86_FEATURE_XMM, c->x86_capability);
482 clear_bit(X86_FEATURE_SEP, c->x86_capability);
485 clear_bit(X86_FEATURE_PSE, c->x86_capability);
487 /* If the model name is still unset, do table lookup. */
488 if ( !c->x86_model_id[0] ) {
490 p = table_lookup_model(c);
492 strcpy(c->x86_model_id, p);
495 sprintf(c->x86_model_id, "%02x/%02x",
496 c->x86, c->x86_model);
499 /* Now the feature flags better reflect actual CPU features! */
501 printk(KERN_DEBUG "CPU: After all inits, caps:");
502 for (i = 0; i < NCAPINTS; i++)
503 printk(" %08x", c->x86_capability[i]);
507 * On SMP, boot_cpu_data holds the common feature set between
508 * all CPUs; so make sure that we indicate which features are
509 * common between the CPUs. The first time this routine gets
510 * executed, c == &boot_cpu_data.
512 if ( c != &boot_cpu_data ) {
513 /* AND the already accumulated flags with these */
514 for ( i = 0 ; i < NCAPINTS ; i++ )
515 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
518 /* Init Machine Check Exception if available. */
522 void __init identify_boot_cpu(void)
524 identify_cpu(&boot_cpu_data);
530 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
532 BUG_ON(c == &boot_cpu_data);
539 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
541 u32 eax, ebx, ecx, edx;
542 int index_msb, core_bits;
544 cpuid(1, &eax, &ebx, &ecx, &edx);
546 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
549 smp_num_siblings = (ebx & 0xff0000) >> 16;
551 if (smp_num_siblings == 1) {
552 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
553 } else if (smp_num_siblings > 1 ) {
555 if (smp_num_siblings > NR_CPUS) {
556 printk(KERN_WARNING "CPU: Unsupported number of the "
557 "siblings %d", smp_num_siblings);
558 smp_num_siblings = 1;
562 index_msb = get_count_order(smp_num_siblings);
563 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
565 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
568 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
570 index_msb = get_count_order(smp_num_siblings) ;
572 core_bits = get_count_order(c->x86_max_cores);
574 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
575 ((1 << core_bits) - 1);
577 if (c->x86_max_cores > 1)
578 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
584 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
588 if (c->x86_vendor < X86_VENDOR_NUM)
589 vendor = this_cpu->c_vendor;
590 else if (c->cpuid_level >= 0)
591 vendor = c->x86_vendor_id;
593 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
594 printk("%s ", vendor);
596 if (!c->x86_model_id[0])
597 printk("%d86", c->x86);
599 printk("%s", c->x86_model_id);
601 if (c->x86_mask || c->cpuid_level >= 0)
602 printk(" stepping %02x\n", c->x86_mask);
607 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
610 * We're emulating future behavior.
611 * In the future, the cpu-specific init functions will be called implicitly
612 * via the magic of initcalls.
613 * They will insert themselves into the cpu_devs structure.
614 * Then, when cpu_init() is called, we can just iterate over that array.
617 extern int intel_cpu_init(void);
618 extern int cyrix_init_cpu(void);
619 extern int nsc_init_cpu(void);
620 extern int amd_init_cpu(void);
621 extern int centaur_init_cpu(void);
622 extern int transmeta_init_cpu(void);
623 extern int nexgen_init_cpu(void);
624 extern int umc_init_cpu(void);
626 void __init early_cpu_init(void)
633 transmeta_init_cpu();
638 #ifdef CONFIG_DEBUG_PAGEALLOC
639 /* pse is not compatible with on-the-fly unmapping,
640 * disable it even if the cpus claim to support it.
642 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
647 /* Make sure %fs is initialized properly in idle threads */
648 struct pt_regs * __devinit idle_regs(struct pt_regs *regs)
650 memset(regs, 0, sizeof(struct pt_regs));
651 regs->fs = __KERNEL_PERCPU;
655 /* Current gdt points %fs at the "master" per-cpu area: after this,
656 * it's on the real one. */
657 void switch_to_new_gdt(void)
659 struct desc_ptr gdt_descr;
661 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
662 gdt_descr.size = GDT_SIZE - 1;
663 load_gdt(&gdt_descr);
664 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
668 * cpu_init() initializes state that is per-CPU. Some data is already
669 * initialized (naturally) in the bootstrap process, such as the GDT
670 * and IDT. We reload them nevertheless, this function acts as a
671 * 'CPU state barrier', nothing should get across.
673 void __cpuinit cpu_init(void)
675 int cpu = smp_processor_id();
676 struct task_struct *curr = current;
677 struct tss_struct * t = &per_cpu(init_tss, cpu);
678 struct thread_struct *thread = &curr->thread;
680 if (cpu_test_and_set(cpu, cpu_initialized)) {
681 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
682 for (;;) local_irq_enable();
685 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
687 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
688 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
689 if (tsc_disable && cpu_has_tsc) {
690 printk(KERN_NOTICE "Disabling TSC...\n");
691 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
692 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
693 set_in_cr4(X86_CR4_TSD);
696 load_idt(&idt_descr);
700 * Set up and load the per-CPU TSS and LDT
702 atomic_inc(&init_mm.mm_count);
703 curr->active_mm = &init_mm;
706 enter_lazy_tlb(&init_mm, curr);
711 load_LDT(&init_mm.context);
713 #ifdef CONFIG_DOUBLEFAULT
714 /* Set up doublefault TSS pointer in the GDT */
715 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
719 asm volatile ("mov %0, %%gs" : : "r" (0));
721 /* Clear all 6 debug registers: */
730 * Force FPU initialization:
732 current_thread_info()->status = 0;
734 mxcsr_feature_mask_init();
737 #ifdef CONFIG_HOTPLUG_CPU
738 void __cpuinit cpu_uninit(void)
740 int cpu = raw_smp_processor_id();
741 cpu_clear(cpu, cpu_initialized);
744 per_cpu(cpu_tlbstate, cpu).state = 0;
745 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;