1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
25 #include <asm/cpumask.h>
28 #ifdef CONFIG_X86_LOCAL_APIC
29 #include <asm/uv/uv.h>
32 #include <asm/pgtable.h>
33 #include <asm/processor.h>
35 #include <asm/atomic.h>
36 #include <asm/proto.h>
37 #include <asm/sections.h>
38 #include <asm/setup.h>
39 #include <asm/hypervisor.h>
40 #include <asm/stackprotector.h>
46 /* all of these masks are initialized in setup_cpu_local_masks() */
47 cpumask_var_t cpu_callin_mask;
48 cpumask_var_t cpu_callout_mask;
49 cpumask_var_t cpu_initialized_mask;
51 /* representing cpus for which sibling maps can be computed */
52 cpumask_var_t cpu_sibling_setup_mask;
54 /* correctly size the local cpu masks */
55 void __init setup_cpu_local_masks(void)
57 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
58 alloc_bootmem_cpumask_var(&cpu_callin_mask);
59 alloc_bootmem_cpumask_var(&cpu_callout_mask);
60 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
63 #else /* CONFIG_X86_32 */
65 cpumask_t cpu_callin_map;
66 cpumask_t cpu_callout_map;
67 cpumask_t cpu_initialized;
68 cpumask_t cpu_sibling_setup_map;
70 #endif /* CONFIG_X86_32 */
73 static struct cpu_dev *this_cpu __cpuinitdata;
75 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
78 * We need valid kernel segments for data and code in long mode too
79 * IRET will check the segment types kkeil 2000/10/28
80 * Also sysret mandates a special GDT layout
82 * The TLS descriptors are currently at a different place compared to i386.
83 * Hopefully nobody expects them at a fixed place (Wine?)
85 [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
86 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
87 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
88 [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
89 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
90 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
92 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
93 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
94 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
95 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
97 * Segments used for calling PnP BIOS have byte granularity.
98 * They code segments and data segments have fixed 64k limits,
99 * the transfer segment sizes are set at run time.
102 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
104 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
106 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
108 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
110 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
112 * The APM segments have byte granularity and their bases
113 * are set at run time. All have 64k limits.
116 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
118 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
120 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
122 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
123 [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
124 GDT_STACK_CANARY_INIT
127 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
130 static int cachesize_override __cpuinitdata = -1;
131 static int disable_x86_serial_nr __cpuinitdata = 1;
133 static int __init cachesize_setup(char *str)
135 get_option(&str, &cachesize_override);
138 __setup("cachesize=", cachesize_setup);
140 static int __init x86_fxsr_setup(char *s)
142 setup_clear_cpu_cap(X86_FEATURE_FXSR);
143 setup_clear_cpu_cap(X86_FEATURE_XMM);
146 __setup("nofxsr", x86_fxsr_setup);
148 static int __init x86_sep_setup(char *s)
150 setup_clear_cpu_cap(X86_FEATURE_SEP);
153 __setup("nosep", x86_sep_setup);
155 /* Standard macro to see if a specific flag is changeable */
156 static inline int flag_is_changeable_p(u32 flag)
161 * Cyrix and IDT cpus allow disabling of CPUID
162 * so the code below may return different results
163 * when it is executed before and after enabling
164 * the CPUID. Add "volatile" to not allow gcc to
165 * optimize the subsequent calls to this function.
167 asm volatile ("pushfl\n\t"
177 : "=&r" (f1), "=&r" (f2)
180 return ((f1^f2) & flag) != 0;
183 /* Probe for the CPUID instruction */
184 static int __cpuinit have_cpuid_p(void)
186 return flag_is_changeable_p(X86_EFLAGS_ID);
189 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
191 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
192 /* Disable processor serial number */
193 unsigned long lo, hi;
194 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
196 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
197 printk(KERN_NOTICE "CPU serial number disabled.\n");
198 clear_cpu_cap(c, X86_FEATURE_PN);
200 /* Disabling the serial number may affect the cpuid level */
201 c->cpuid_level = cpuid_eax(0);
205 static int __init x86_serial_nr_setup(char *s)
207 disable_x86_serial_nr = 0;
210 __setup("serialnumber", x86_serial_nr_setup);
212 static inline int flag_is_changeable_p(u32 flag)
216 /* Probe for the CPUID instruction */
217 static inline int have_cpuid_p(void)
221 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
227 * Some CPU features depend on higher CPUID levels, which may not always
228 * be available due to CPUID level capping or broken virtualization
229 * software. Add those features to this table to auto-disable them.
231 struct cpuid_dependent_feature {
235 static const struct cpuid_dependent_feature __cpuinitconst
236 cpuid_dependent_features[] = {
237 { X86_FEATURE_MWAIT, 0x00000005 },
238 { X86_FEATURE_DCA, 0x00000009 },
239 { X86_FEATURE_XSAVE, 0x0000000d },
243 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
245 const struct cpuid_dependent_feature *df;
246 for (df = cpuid_dependent_features; df->feature; df++) {
248 * Note: cpuid_level is set to -1 if unavailable, but
249 * extended_extended_level is set to 0 if unavailable
250 * and the legitimate extended levels are all negative
251 * when signed; hence the weird messing around with
254 if (cpu_has(c, df->feature) &&
255 ((s32)df->level < 0 ?
256 (u32)df->level > (u32)c->extended_cpuid_level :
257 (s32)df->level > (s32)c->cpuid_level)) {
258 clear_cpu_cap(c, df->feature);
261 "CPU: CPU feature %s disabled "
262 "due to lack of CPUID level 0x%x\n",
263 x86_cap_flags[df->feature],
270 * Naming convention should be: <Name> [(<Codename>)]
271 * This table only is used unless init_<vendor>() below doesn't set it;
272 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
276 /* Look up CPU names by table lookup. */
277 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
279 struct cpu_model_info *info;
281 if (c->x86_model >= 16)
282 return NULL; /* Range check */
287 info = this_cpu->c_models;
289 while (info && info->family) {
290 if (info->family == c->x86)
291 return info->model_names[c->x86_model];
294 return NULL; /* Not found */
297 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
299 void load_percpu_segment(int cpu)
302 loadsegment(fs, __KERNEL_PERCPU);
305 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
307 load_stack_canary_segment();
310 /* Current gdt points %fs at the "master" per-cpu area: after this,
311 * it's on the real one. */
312 void switch_to_new_gdt(int cpu)
314 struct desc_ptr gdt_descr;
316 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
317 gdt_descr.size = GDT_SIZE - 1;
318 load_gdt(&gdt_descr);
319 /* Reload the per-cpu base */
321 load_percpu_segment(cpu);
324 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
326 static void __cpuinit default_init(struct cpuinfo_x86 *c)
329 display_cacheinfo(c);
331 /* Not much we can do here... */
332 /* Check if at least it has cpuid */
333 if (c->cpuid_level == -1) {
334 /* No cpuid. It must be an ancient CPU */
336 strcpy(c->x86_model_id, "486");
337 else if (c->x86 == 3)
338 strcpy(c->x86_model_id, "386");
343 static struct cpu_dev __cpuinitdata default_cpu = {
344 .c_init = default_init,
345 .c_vendor = "Unknown",
346 .c_x86_vendor = X86_VENDOR_UNKNOWN,
349 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
354 if (c->extended_cpuid_level < 0x80000004)
357 v = (unsigned int *) c->x86_model_id;
358 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
359 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
360 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
361 c->x86_model_id[48] = 0;
363 /* Intel chips right-justify this string for some dumb reason;
364 undo that brain damage */
365 p = q = &c->x86_model_id[0];
371 while (q <= &c->x86_model_id[48])
372 *q++ = '\0'; /* Zero-pad the rest */
376 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
378 unsigned int n, dummy, ebx, ecx, edx, l2size;
380 n = c->extended_cpuid_level;
382 if (n >= 0x80000005) {
383 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
384 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
385 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
386 c->x86_cache_size = (ecx>>24) + (edx>>24);
388 /* On K8 L1 TLB is inclusive, so don't count it */
393 if (n < 0x80000006) /* Some chips just has a large L1. */
396 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
400 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
402 /* do processor-specific cache resizing */
403 if (this_cpu->c_size_cache)
404 l2size = this_cpu->c_size_cache(c, l2size);
406 /* Allow user to override all this if necessary. */
407 if (cachesize_override != -1)
408 l2size = cachesize_override;
411 return; /* Again, no L2 cache is possible */
414 c->x86_cache_size = l2size;
416 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
420 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
423 u32 eax, ebx, ecx, edx;
424 int index_msb, core_bits;
426 if (!cpu_has(c, X86_FEATURE_HT))
429 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
432 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
435 cpuid(1, &eax, &ebx, &ecx, &edx);
437 smp_num_siblings = (ebx & 0xff0000) >> 16;
439 if (smp_num_siblings == 1) {
440 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
441 } else if (smp_num_siblings > 1) {
443 if (smp_num_siblings > nr_cpu_ids) {
444 printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
446 smp_num_siblings = 1;
450 index_msb = get_count_order(smp_num_siblings);
451 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
453 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
455 index_msb = get_count_order(smp_num_siblings);
457 core_bits = get_count_order(c->x86_max_cores);
459 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
460 ((1 << core_bits) - 1);
464 if ((c->x86_max_cores * smp_num_siblings) > 1) {
465 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
467 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
473 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
475 char *v = c->x86_vendor_id;
479 for (i = 0; i < X86_VENDOR_NUM; i++) {
483 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
484 (cpu_devs[i]->c_ident[1] &&
485 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
486 this_cpu = cpu_devs[i];
487 c->x86_vendor = this_cpu->c_x86_vendor;
494 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
495 printk(KERN_ERR "CPU: Your system may be unstable.\n");
498 c->x86_vendor = X86_VENDOR_UNKNOWN;
499 this_cpu = &default_cpu;
502 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
504 /* Get vendor name */
505 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
506 (unsigned int *)&c->x86_vendor_id[0],
507 (unsigned int *)&c->x86_vendor_id[8],
508 (unsigned int *)&c->x86_vendor_id[4]);
511 /* Intel-defined flags: level 0x00000001 */
512 if (c->cpuid_level >= 0x00000001) {
513 u32 junk, tfms, cap0, misc;
514 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
515 c->x86 = (tfms >> 8) & 0xf;
516 c->x86_model = (tfms >> 4) & 0xf;
517 c->x86_mask = tfms & 0xf;
519 c->x86 += (tfms >> 20) & 0xff;
521 c->x86_model += ((tfms >> 16) & 0xf) << 4;
522 if (cap0 & (1<<19)) {
523 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
524 c->x86_cache_alignment = c->x86_clflush_size;
529 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
534 /* Intel-defined flags: level 0x00000001 */
535 if (c->cpuid_level >= 0x00000001) {
536 u32 capability, excap;
537 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
538 c->x86_capability[0] = capability;
539 c->x86_capability[4] = excap;
542 /* AMD-defined flags: level 0x80000001 */
543 xlvl = cpuid_eax(0x80000000);
544 c->extended_cpuid_level = xlvl;
545 if ((xlvl & 0xffff0000) == 0x80000000) {
546 if (xlvl >= 0x80000001) {
547 c->x86_capability[1] = cpuid_edx(0x80000001);
548 c->x86_capability[6] = cpuid_ecx(0x80000001);
552 if (c->extended_cpuid_level >= 0x80000008) {
553 u32 eax = cpuid_eax(0x80000008);
555 c->x86_virt_bits = (eax >> 8) & 0xff;
556 c->x86_phys_bits = eax & 0xff;
559 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
560 c->x86_phys_bits = 36;
563 if (c->extended_cpuid_level >= 0x80000007)
564 c->x86_power = cpuid_edx(0x80000007);
568 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
574 * First of all, decide if this is a 486 or higher
575 * It's a 486 if we can modify the AC flag
577 if (flag_is_changeable_p(X86_EFLAGS_AC))
582 for (i = 0; i < X86_VENDOR_NUM; i++)
583 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
584 c->x86_vendor_id[0] = 0;
585 cpu_devs[i]->c_identify(c);
586 if (c->x86_vendor_id[0]) {
595 * Do minimum CPU detection early.
596 * Fields really needed: vendor, cpuid_level, family, model, mask,
598 * The others are not touched to avoid unwanted side effects.
600 * WARNING: this function is only called on the BP. Don't add code here
601 * that is supposed to run on all CPUs.
603 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
606 c->x86_clflush_size = 64;
607 c->x86_phys_bits = 36;
608 c->x86_virt_bits = 48;
610 c->x86_clflush_size = 32;
611 c->x86_phys_bits = 32;
612 c->x86_virt_bits = 32;
614 c->x86_cache_alignment = c->x86_clflush_size;
616 memset(&c->x86_capability, 0, sizeof c->x86_capability);
617 c->extended_cpuid_level = 0;
620 identify_cpu_without_cpuid(c);
622 /* cyrix could have cpuid enabled via c_identify()*/
632 if (this_cpu->c_early_init)
633 this_cpu->c_early_init(c);
636 c->cpu_index = boot_cpu_id;
638 filter_cpuid_features(c, false);
641 void __init early_cpu_init(void)
643 struct cpu_dev **cdev;
646 printk("KERNEL supported cpus:\n");
647 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
648 struct cpu_dev *cpudev = *cdev;
651 if (count >= X86_VENDOR_NUM)
653 cpu_devs[count] = cpudev;
656 for (j = 0; j < 2; j++) {
657 if (!cpudev->c_ident[j])
659 printk(" %s %s\n", cpudev->c_vendor,
664 early_identify_cpu(&boot_cpu_data);
668 * The NOPL instruction is supposed to exist on all CPUs with
669 * family >= 6; unfortunately, that's not true in practice because
670 * of early VIA chips and (more importantly) broken virtualizers that
671 * are not easy to detect. In the latter case it doesn't even *fail*
672 * reliably, so probing for it doesn't even work. Disable it completely
673 * unless we can find a reliable way to detect all the broken cases.
675 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
677 clear_cpu_cap(c, X86_FEATURE_NOPL);
680 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
682 c->extended_cpuid_level = 0;
685 identify_cpu_without_cpuid(c);
687 /* cyrix could have cpuid enabled via c_identify()*/
697 if (c->cpuid_level >= 0x00000001) {
698 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
700 # ifdef CONFIG_X86_HT
701 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
703 c->apicid = c->initial_apicid;
708 c->phys_proc_id = c->initial_apicid;
712 get_model_name(c); /* Default name */
714 init_scattered_cpuid_features(c);
719 * This does the hard work of actually picking apart the CPU stuff...
721 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
725 c->loops_per_jiffy = loops_per_jiffy;
726 c->x86_cache_size = -1;
727 c->x86_vendor = X86_VENDOR_UNKNOWN;
728 c->x86_model = c->x86_mask = 0; /* So far unknown... */
729 c->x86_vendor_id[0] = '\0'; /* Unset */
730 c->x86_model_id[0] = '\0'; /* Unset */
731 c->x86_max_cores = 1;
732 c->x86_coreid_bits = 0;
734 c->x86_clflush_size = 64;
735 c->x86_phys_bits = 36;
736 c->x86_virt_bits = 48;
738 c->cpuid_level = -1; /* CPUID not detected */
739 c->x86_clflush_size = 32;
740 c->x86_phys_bits = 32;
741 c->x86_virt_bits = 32;
743 c->x86_cache_alignment = c->x86_clflush_size;
744 memset(&c->x86_capability, 0, sizeof c->x86_capability);
748 if (this_cpu->c_identify)
749 this_cpu->c_identify(c);
752 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
756 * Vendor-specific initialization. In this section we
757 * canonicalize the feature flags, meaning if there are
758 * features a certain CPU supports which CPUID doesn't
759 * tell us, CPUID claiming incorrect flags, or other bugs,
760 * we handle them here.
762 * At the end of this section, c->x86_capability better
763 * indicate the features this CPU genuinely supports!
765 if (this_cpu->c_init)
768 /* Disable the PN if appropriate */
769 squash_the_stupid_serial_number(c);
772 * The vendor-specific functions might have changed features. Now
773 * we do "generic changes."
776 /* Filter out anything that depends on CPUID levels we don't have */
777 filter_cpuid_features(c, true);
779 /* If the model name is still unset, do table lookup. */
780 if (!c->x86_model_id[0]) {
782 p = table_lookup_model(c);
784 strcpy(c->x86_model_id, p);
787 sprintf(c->x86_model_id, "%02x/%02x",
788 c->x86, c->x86_model);
797 * On SMP, boot_cpu_data holds the common feature set between
798 * all CPUs; so make sure that we indicate which features are
799 * common between the CPUs. The first time this routine gets
800 * executed, c == &boot_cpu_data.
802 if (c != &boot_cpu_data) {
803 /* AND the already accumulated flags with these */
804 for (i = 0; i < NCAPINTS; i++)
805 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
808 /* Clear all flags overriden by options */
809 for (i = 0; i < NCAPINTS; i++)
810 c->x86_capability[i] &= ~cleared_cpu_caps[i];
812 #ifdef CONFIG_X86_MCE
813 /* Init Machine Check Exception if available. */
817 select_idle_routine(c);
819 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
820 numa_add_cpu(smp_processor_id());
825 static void vgetcpu_set_mode(void)
827 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
828 vgetcpu_mode = VGETCPU_RDTSCP;
830 vgetcpu_mode = VGETCPU_LSL;
834 void __init identify_boot_cpu(void)
836 identify_cpu(&boot_cpu_data);
845 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
847 BUG_ON(c == &boot_cpu_data);
860 static struct msr_range msr_range_array[] __cpuinitdata = {
861 { 0x00000000, 0x00000418},
862 { 0xc0000000, 0xc000040b},
863 { 0xc0010000, 0xc0010142},
864 { 0xc0011000, 0xc001103b},
867 static void __cpuinit print_cpu_msr(void)
872 unsigned index_min, index_max;
874 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
875 index_min = msr_range_array[i].min;
876 index_max = msr_range_array[i].max;
877 for (index = index_min; index < index_max; index++) {
878 if (rdmsrl_amd_safe(index, &val))
880 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
885 static int show_msr __cpuinitdata;
886 static __init int setup_show_msr(char *arg)
890 get_option(&arg, &num);
896 __setup("show_msr=", setup_show_msr);
898 static __init int setup_noclflush(char *arg)
900 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
903 __setup("noclflush", setup_noclflush);
905 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
909 if (c->x86_vendor < X86_VENDOR_NUM)
910 vendor = this_cpu->c_vendor;
911 else if (c->cpuid_level >= 0)
912 vendor = c->x86_vendor_id;
914 if (vendor && !strstr(c->x86_model_id, vendor))
915 printk(KERN_CONT "%s ", vendor);
917 if (c->x86_model_id[0])
918 printk(KERN_CONT "%s", c->x86_model_id);
920 printk(KERN_CONT "%d86", c->x86);
922 if (c->x86_mask || c->cpuid_level >= 0)
923 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
925 printk(KERN_CONT "\n");
928 if (c->cpu_index < show_msr)
936 static __init int setup_disablecpuid(char *arg)
939 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
940 setup_clear_cpu_cap(bit);
945 __setup("clearcpuid=", setup_disablecpuid);
948 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
950 DEFINE_PER_CPU_FIRST(union irq_stack_union,
951 irq_stack_union) __aligned(PAGE_SIZE);
952 DEFINE_PER_CPU(char *, irq_stack_ptr) =
953 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
955 DEFINE_PER_CPU(unsigned long, kernel_stack) =
956 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
957 EXPORT_PER_CPU_SYMBOL(kernel_stack);
959 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
961 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
962 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
963 __aligned(PAGE_SIZE);
965 extern asmlinkage void ignore_sysret(void);
967 /* May not be marked __init: used by software suspend */
968 void syscall_init(void)
971 * LSTAR and STAR live in a bit strange symbiosis.
972 * They both write to the same internal register. STAR allows to
973 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
975 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
976 wrmsrl(MSR_LSTAR, system_call);
977 wrmsrl(MSR_CSTAR, ignore_sysret);
979 #ifdef CONFIG_IA32_EMULATION
980 syscall32_cpu_init();
983 /* Flags to clear on syscall */
984 wrmsrl(MSR_SYSCALL_MASK,
985 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
988 unsigned long kernel_eflags;
991 * Copies of the original ist values from the tss are only accessed during
992 * debugging, no special alignment required.
994 DEFINE_PER_CPU(struct orig_ist, orig_ist);
998 #ifdef CONFIG_CC_STACKPROTECTOR
999 DEFINE_PER_CPU(unsigned long, stack_canary);
1002 /* Make sure %fs and %gs are initialized properly in idle threads */
1003 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1005 memset(regs, 0, sizeof(struct pt_regs));
1006 regs->fs = __KERNEL_PERCPU;
1007 regs->gs = __KERNEL_STACK_CANARY;
1013 * cpu_init() initializes state that is per-CPU. Some data is already
1014 * initialized (naturally) in the bootstrap process, such as the GDT
1015 * and IDT. We reload them nevertheless, this function acts as a
1016 * 'CPU state barrier', nothing should get across.
1017 * A lot of state is already set up in PDA init for 64 bit
1019 #ifdef CONFIG_X86_64
1020 void __cpuinit cpu_init(void)
1022 int cpu = stack_smp_processor_id();
1023 struct tss_struct *t = &per_cpu(init_tss, cpu);
1024 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
1026 struct task_struct *me;
1030 if (cpu != 0 && percpu_read(node_number) == 0 &&
1031 cpu_to_node(cpu) != NUMA_NO_NODE)
1032 percpu_write(node_number, cpu_to_node(cpu));
1037 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1038 panic("CPU#%d already initialized!\n", cpu);
1040 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1042 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1045 * Initialize the per-CPU GDT with the boot GDT,
1046 * and set up the GDT descriptor:
1049 switch_to_new_gdt(cpu);
1052 load_idt((const struct desc_ptr *)&idt_descr);
1054 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1057 wrmsrl(MSR_FS_BASE, 0);
1058 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1066 * set up and load the per-CPU TSS
1068 if (!orig_ist->ist[0]) {
1069 static const unsigned int sizes[N_EXCEPTION_STACKS] = {
1070 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1071 [DEBUG_STACK - 1] = DEBUG_STKSZ
1073 char *estacks = per_cpu(exception_stacks, cpu);
1074 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1075 estacks += sizes[v];
1076 orig_ist->ist[v] = t->x86_tss.ist[v] =
1077 (unsigned long)estacks;
1081 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1083 * <= is required because the CPU will access up to
1084 * 8 bits beyond the end of the IO permission bitmap.
1086 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1087 t->io_bitmap[i] = ~0UL;
1089 atomic_inc(&init_mm.mm_count);
1090 me->active_mm = &init_mm;
1093 enter_lazy_tlb(&init_mm, me);
1095 load_sp0(t, ¤t->thread);
1096 set_tss_desc(cpu, t);
1098 load_LDT(&init_mm.context);
1102 * If the kgdb is connected no debug regs should be altered. This
1103 * is only applicable when KGDB and a KGDB I/O module are built
1104 * into the kernel and you are using early debugging with
1105 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1107 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1108 arch_kgdb_ops.correct_hw_break();
1113 * Clear all 6 debug registers:
1115 set_debugreg(0UL, 0);
1116 set_debugreg(0UL, 1);
1117 set_debugreg(0UL, 2);
1118 set_debugreg(0UL, 3);
1119 set_debugreg(0UL, 6);
1120 set_debugreg(0UL, 7);
1125 raw_local_save_flags(kernel_eflags);
1133 void __cpuinit cpu_init(void)
1135 int cpu = smp_processor_id();
1136 struct task_struct *curr = current;
1137 struct tss_struct *t = &per_cpu(init_tss, cpu);
1138 struct thread_struct *thread = &curr->thread;
1140 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1141 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1142 for (;;) local_irq_enable();
1145 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1147 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1148 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1150 load_idt(&idt_descr);
1151 switch_to_new_gdt(cpu);
1154 * Set up and load the per-CPU TSS and LDT
1156 atomic_inc(&init_mm.mm_count);
1157 curr->active_mm = &init_mm;
1160 enter_lazy_tlb(&init_mm, curr);
1162 load_sp0(t, thread);
1163 set_tss_desc(cpu, t);
1165 load_LDT(&init_mm.context);
1167 #ifdef CONFIG_DOUBLEFAULT
1168 /* Set up doublefault TSS pointer in the GDT */
1169 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1172 /* Clear all 6 debug registers: */
1181 * Force FPU initialization:
1184 current_thread_info()->status = TS_XSAVE;
1186 current_thread_info()->status = 0;
1188 mxcsr_feature_mask_init();
1191 * Boot processor to setup the FP and extended state context info.
1193 if (smp_processor_id() == boot_cpu_id)
1194 init_thread_xstate();