2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 static int disable_apic_timer __cpuinitdata;
49 static int apic_calibrate_pmtmr __initdata;
54 /* x2apic enabled before OS handover */
55 int x2apic_preenabled;
57 /* Local APIC timer works in C2 */
58 int local_apic_timer_c2_ok;
59 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
62 * Debug level, exported for io_apic.c
66 /* Have we found an MP table */
69 static struct resource lapic_resource = {
71 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
74 static unsigned int calibration_result;
76 static int lapic_next_event(unsigned long delta,
77 struct clock_event_device *evt);
78 static void lapic_timer_setup(enum clock_event_mode mode,
79 struct clock_event_device *evt);
80 static void lapic_timer_broadcast(cpumask_t mask);
81 static void apic_pm_activate(void);
83 static struct clock_event_device lapic_clockevent = {
85 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
86 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
88 .set_mode = lapic_timer_setup,
89 .set_next_event = lapic_next_event,
90 .broadcast = lapic_timer_broadcast,
94 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
96 static unsigned long apic_phys;
98 unsigned long mp_lapic_addr;
100 unsigned int __cpuinitdata maxcpus = NR_CPUS;
102 * Get the LAPIC version
104 static inline int lapic_get_version(void)
106 return GET_APIC_VERSION(apic_read(APIC_LVR));
110 * Check, if the APIC is integrated or a seperate chip
112 static inline int lapic_is_integrated(void)
118 * Check, whether this is a modern or a first generation APIC
120 static int modern_apic(void)
122 /* AMD systems use old APIC versions, so check the CPU */
123 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
124 boot_cpu_data.x86 >= 0xf)
126 return lapic_get_version() >= 0x14;
129 void xapic_wait_icr_idle(void)
131 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
135 u32 safe_xapic_wait_icr_idle(void)
142 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
146 } while (timeout++ < 1000);
151 void xapic_icr_write(u32 low, u32 id)
153 apic_write(APIC_ICR2, id << 24);
154 apic_write(APIC_ICR, low);
157 u64 xapic_icr_read(void)
161 icr2 = apic_read(APIC_ICR2);
162 icr1 = apic_read(APIC_ICR);
164 return (icr1 | ((u64)icr2 << 32));
167 static struct apic_ops xapic_ops = {
168 .read = native_apic_mem_read,
169 .write = native_apic_mem_write,
170 .write_atomic = native_apic_mem_write_atomic,
171 .icr_read = xapic_icr_read,
172 .icr_write = xapic_icr_write,
173 .wait_icr_idle = xapic_wait_icr_idle,
174 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
177 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
179 EXPORT_SYMBOL_GPL(apic_ops);
181 static void x2apic_wait_icr_idle(void)
183 /* no need to wait for icr idle in x2apic */
187 static u32 safe_x2apic_wait_icr_idle(void)
189 /* no need to wait for icr idle in x2apic */
193 void x2apic_icr_write(u32 low, u32 id)
195 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
198 u64 x2apic_icr_read(void)
202 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
206 static struct apic_ops x2apic_ops = {
207 .read = native_apic_msr_read,
208 .write = native_apic_msr_write,
209 .write_atomic = native_apic_msr_write,
210 .icr_read = x2apic_icr_read,
211 .icr_write = x2apic_icr_write,
212 .wait_icr_idle = x2apic_wait_icr_idle,
213 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
217 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
219 void __cpuinit enable_NMI_through_LVT0(void)
223 /* unmask and set to NMI */
225 apic_write(APIC_LVT0, v);
229 * lapic_get_maxlvt - get the maximum number of local vector table entries
231 int lapic_get_maxlvt(void)
233 unsigned int v, maxlvt;
235 v = apic_read(APIC_LVR);
236 maxlvt = GET_APIC_MAXLVT(v);
241 * This function sets up the local APIC timer, with a timeout of
242 * 'clocks' APIC bus clock. During calibration we actually call
243 * this function twice on the boot CPU, once with a bogus timeout
244 * value, second time for real. The other (noncalibrating) CPUs
245 * call this function only once, with the real, calibrated value.
247 * We do reads before writes even if unnecessary, to get around the
248 * P5 APIC double write bug.
251 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
253 unsigned int lvtt_value, tmp_value;
255 lvtt_value = LOCAL_TIMER_VECTOR;
257 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
259 lvtt_value |= APIC_LVT_MASKED;
261 apic_write(APIC_LVTT, lvtt_value);
266 tmp_value = apic_read(APIC_TDCR);
267 apic_write(APIC_TDCR, (tmp_value
268 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
272 apic_write(APIC_TMICT, clocks);
276 * Setup extended LVT, AMD specific (K8, family 10h)
278 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
279 * MCE interrupts are supported. Thus MCE offset must be set to 0.
282 #define APIC_EILVT_LVTOFF_MCE 0
283 #define APIC_EILVT_LVTOFF_IBS 1
285 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
287 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
288 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
293 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
295 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
296 return APIC_EILVT_LVTOFF_MCE;
299 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
301 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
302 return APIC_EILVT_LVTOFF_IBS;
306 * Program the next event, relative to now
308 static int lapic_next_event(unsigned long delta,
309 struct clock_event_device *evt)
311 apic_write(APIC_TMICT, delta);
316 * Setup the lapic timer in periodic or oneshot mode
318 static void lapic_timer_setup(enum clock_event_mode mode,
319 struct clock_event_device *evt)
324 /* Lapic used as dummy for broadcast ? */
325 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
328 local_irq_save(flags);
331 case CLOCK_EVT_MODE_PERIODIC:
332 case CLOCK_EVT_MODE_ONESHOT:
333 __setup_APIC_LVTT(calibration_result,
334 mode != CLOCK_EVT_MODE_PERIODIC, 1);
336 case CLOCK_EVT_MODE_UNUSED:
337 case CLOCK_EVT_MODE_SHUTDOWN:
338 v = apic_read(APIC_LVTT);
339 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
340 apic_write(APIC_LVTT, v);
342 case CLOCK_EVT_MODE_RESUME:
343 /* Nothing to do here */
347 local_irq_restore(flags);
351 * Local APIC timer broadcast function
353 static void lapic_timer_broadcast(cpumask_t mask)
356 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
361 * Setup the local APIC timer for this CPU. Copy the initilized values
362 * of the boot CPU and register the clock event in the framework.
364 static void setup_APIC_timer(void)
366 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
368 memcpy(levt, &lapic_clockevent, sizeof(*levt));
369 levt->cpumask = cpumask_of_cpu(smp_processor_id());
371 clockevents_register_device(levt);
375 * In this function we calibrate APIC bus clocks to the external
376 * timer. Unfortunately we cannot use jiffies and the timer irq
377 * to calibrate, since some later bootup code depends on getting
378 * the first irq? Ugh.
380 * We want to do the calibration only once since we
381 * want to have local timer irqs syncron. CPUs connected
382 * by the same APIC bus have the very same bus frequency.
383 * And we want to have irqs off anyways, no accidental
387 #define TICK_COUNT 100000000
389 static void __init calibrate_APIC_clock(void)
391 unsigned apic, apic_start;
392 unsigned long tsc, tsc_start;
398 * Put whatever arbitrary (but long enough) timeout
399 * value into the APIC clock, we just want to get the
400 * counter running for calibration.
402 * No interrupt enable !
404 __setup_APIC_LVTT(250000000, 0, 0);
406 apic_start = apic_read(APIC_TMCCT);
407 #ifdef CONFIG_X86_PM_TIMER
408 if (apic_calibrate_pmtmr && pmtmr_ioport) {
409 pmtimer_wait(5000); /* 5ms wait */
410 apic = apic_read(APIC_TMCCT);
411 result = (apic_start - apic) * 1000L / 5;
418 apic = apic_read(APIC_TMCCT);
420 } while ((tsc - tsc_start) < TICK_COUNT &&
421 (apic_start - apic) < TICK_COUNT);
423 result = (apic_start - apic) * 1000L * tsc_khz /
429 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
431 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
432 result / 1000 / 1000, result / 1000 % 1000);
434 /* Calculate the scaled math multiplication factor */
435 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
436 lapic_clockevent.shift);
437 lapic_clockevent.max_delta_ns =
438 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
439 lapic_clockevent.min_delta_ns =
440 clockevent_delta2ns(0xF, &lapic_clockevent);
442 calibration_result = result / HZ;
446 * Setup the boot APIC
448 * Calibrate and verify the result.
450 void __init setup_boot_APIC_clock(void)
453 * The local apic timer can be disabled via the kernel commandline.
454 * Register the lapic timer as a dummy clock event source on SMP
455 * systems, so the broadcast mechanism is used. On UP systems simply
458 if (disable_apic_timer) {
459 printk(KERN_INFO "Disabling APIC timer\n");
460 /* No broadcast on UP ! */
461 if (num_possible_cpus() > 1) {
462 lapic_clockevent.mult = 1;
468 printk(KERN_INFO "Using local APIC timer interrupts.\n");
469 calibrate_APIC_clock();
472 * Do a sanity check on the APIC calibration result
474 if (calibration_result < (1000000 / HZ)) {
476 "APIC frequency too slow, disabling apic timer\n");
477 /* No broadcast on UP ! */
478 if (num_possible_cpus() > 1)
484 * If nmi_watchdog is set to IO_APIC, we need the
485 * PIT/HPET going. Otherwise register lapic as a dummy
488 if (nmi_watchdog != NMI_IO_APIC)
489 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
491 printk(KERN_WARNING "APIC timer registered as dummy,"
492 " due to nmi_watchdog=%d!\n", nmi_watchdog);
497 void __cpuinit setup_secondary_APIC_clock(void)
503 * The guts of the apic timer interrupt
505 static void local_apic_timer_interrupt(void)
507 int cpu = smp_processor_id();
508 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
511 * Normally we should not be here till LAPIC has been initialized but
512 * in some cases like kdump, its possible that there is a pending LAPIC
513 * timer interrupt from previous kernel's context and is delivered in
514 * new kernel the moment interrupts are enabled.
516 * Interrupts are enabled early and LAPIC is setup much later, hence
517 * its possible that when we get here evt->event_handler is NULL.
518 * Check for event_handler being NULL and discard the interrupt as
521 if (!evt->event_handler) {
523 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
525 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
530 * the NMI deadlock-detector uses this.
532 add_pda(apic_timer_irqs, 1);
534 evt->event_handler(evt);
538 * Local APIC timer interrupt. This is the most natural way for doing
539 * local interrupts, but local timer interrupts can be emulated by
540 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
542 * [ if a single-CPU system runs an SMP kernel then we call the local
543 * interrupt as well. Thus we cannot inline the local irq ... ]
545 void smp_apic_timer_interrupt(struct pt_regs *regs)
547 struct pt_regs *old_regs = set_irq_regs(regs);
550 * NOTE! We'd better ACK the irq immediately,
551 * because timer handling can be slow.
555 * update_process_times() expects us to have done irq_enter().
556 * Besides, if we don't timer interrupts ignore the global
557 * interrupt lock, which is the WrongThing (tm) to do.
561 local_apic_timer_interrupt();
563 set_irq_regs(old_regs);
566 int setup_profiling_timer(unsigned int multiplier)
573 * Local APIC start and shutdown
577 * clear_local_APIC - shutdown the local APIC
579 * This is called, when a CPU is disabled and before rebooting, so the state of
580 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
581 * leftovers during boot.
583 void clear_local_APIC(void)
588 /* APIC hasn't been mapped yet */
592 maxlvt = lapic_get_maxlvt();
594 * Masking an LVT entry can trigger a local APIC error
595 * if the vector is zero. Mask LVTERR first to prevent this.
598 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
599 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
602 * Careful: we have to set masks only first to deassert
603 * any level-triggered sources.
605 v = apic_read(APIC_LVTT);
606 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
607 v = apic_read(APIC_LVT0);
608 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
609 v = apic_read(APIC_LVT1);
610 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
612 v = apic_read(APIC_LVTPC);
613 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
617 * Clean APIC state for other OSs:
619 apic_write(APIC_LVTT, APIC_LVT_MASKED);
620 apic_write(APIC_LVT0, APIC_LVT_MASKED);
621 apic_write(APIC_LVT1, APIC_LVT_MASKED);
623 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
625 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
626 apic_write(APIC_ESR, 0);
631 * disable_local_APIC - clear and disable the local APIC
633 void disable_local_APIC(void)
640 * Disable APIC (implies clearing of registers
643 value = apic_read(APIC_SPIV);
644 value &= ~APIC_SPIV_APIC_ENABLED;
645 apic_write(APIC_SPIV, value);
648 void lapic_shutdown(void)
655 local_irq_save(flags);
657 disable_local_APIC();
659 local_irq_restore(flags);
663 * This is to verify that we're looking at a real local APIC.
664 * Check these against your board if the CPUs aren't getting
665 * started for no apparent reason.
667 int __init verify_local_APIC(void)
669 unsigned int reg0, reg1;
672 * The version register is read-only in a real APIC.
674 reg0 = apic_read(APIC_LVR);
675 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
676 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
677 reg1 = apic_read(APIC_LVR);
678 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
681 * The two version reads above should print the same
682 * numbers. If the second one is different, then we
683 * poke at a non-APIC.
689 * Check if the version looks reasonably.
691 reg1 = GET_APIC_VERSION(reg0);
692 if (reg1 == 0x00 || reg1 == 0xff)
694 reg1 = lapic_get_maxlvt();
695 if (reg1 < 0x02 || reg1 == 0xff)
699 * The ID register is read/write in a real APIC.
701 reg0 = apic_read(APIC_ID);
702 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
703 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
704 reg1 = apic_read(APIC_ID);
705 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
706 apic_write(APIC_ID, reg0);
707 if (reg1 != (reg0 ^ APIC_ID_MASK))
711 * The next two are just to see if we have sane values.
712 * They're only really relevant if we're in Virtual Wire
713 * compatibility mode, but most boxes are anymore.
715 reg0 = apic_read(APIC_LVT0);
716 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
717 reg1 = apic_read(APIC_LVT1);
718 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
724 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
726 void __init sync_Arb_IDs(void)
728 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
735 apic_wait_icr_idle();
737 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
738 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
743 * An initial setup of the virtual wire mode.
745 void __init init_bsp_APIC(void)
750 * Don't do the setup now if we have a SMP BIOS as the
751 * through-I/O-APIC virtual wire mode might be active.
753 if (smp_found_config || !cpu_has_apic)
756 value = apic_read(APIC_LVR);
759 * Do not trust the local APIC being empty at bootup.
766 value = apic_read(APIC_SPIV);
767 value &= ~APIC_VECTOR_MASK;
768 value |= APIC_SPIV_APIC_ENABLED;
769 value |= APIC_SPIV_FOCUS_DISABLED;
770 value |= SPURIOUS_APIC_VECTOR;
771 apic_write(APIC_SPIV, value);
774 * Set up the virtual wire mode.
776 apic_write(APIC_LVT0, APIC_DM_EXTINT);
778 apic_write(APIC_LVT1, value);
782 * setup_local_APIC - setup the local APIC
784 void __cpuinit setup_local_APIC(void)
790 value = apic_read(APIC_LVR);
792 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
795 * Double-check whether this APIC is really registered.
796 * This is meaningless in clustered apic mode, so we skip it.
798 if (!apic_id_registered())
802 * Intel recommends to set DFR, LDR and TPR before enabling
803 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
804 * document number 292116). So here it goes...
809 * Set Task Priority to 'accept all'. We never change this
812 value = apic_read(APIC_TASKPRI);
813 value &= ~APIC_TPRI_MASK;
814 apic_write(APIC_TASKPRI, value);
817 * After a crash, we no longer service the interrupts and a pending
818 * interrupt from previous kernel might still have ISR bit set.
820 * Most probably by now CPU has serviced that pending interrupt and
821 * it might not have done the ack_APIC_irq() because it thought,
822 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
823 * does not clear the ISR bit and cpu thinks it has already serivced
824 * the interrupt. Hence a vector might get locked. It was noticed
825 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
827 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
828 value = apic_read(APIC_ISR + i*0x10);
829 for (j = 31; j >= 0; j--) {
836 * Now that we are all set up, enable the APIC
838 value = apic_read(APIC_SPIV);
839 value &= ~APIC_VECTOR_MASK;
843 value |= APIC_SPIV_APIC_ENABLED;
845 /* We always use processor focus */
848 * Set spurious IRQ vector
850 value |= SPURIOUS_APIC_VECTOR;
851 apic_write(APIC_SPIV, value);
856 * set up through-local-APIC on the BP's LINT0. This is not
857 * strictly necessary in pure symmetric-IO mode, but sometimes
858 * we delegate interrupts to the 8259A.
861 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
863 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
864 if (!smp_processor_id() && !value) {
865 value = APIC_DM_EXTINT;
866 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
869 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
870 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
873 apic_write(APIC_LVT0, value);
876 * only the BP should see the LINT1 NMI signal, obviously.
878 if (!smp_processor_id())
881 value = APIC_DM_NMI | APIC_LVT_MASKED;
882 apic_write(APIC_LVT1, value);
886 static void __cpuinit lapic_setup_esr(void)
888 unsigned maxlvt = lapic_get_maxlvt();
890 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
892 * spec says clear errors after enabling vector.
895 apic_write(APIC_ESR, 0);
898 void __cpuinit end_local_APIC_setup(void)
901 setup_apic_nmi_watchdog(NULL);
905 void check_x2apic(void)
909 rdmsr(MSR_IA32_APICBASE, msr, msr2);
911 if (msr & X2APIC_ENABLE) {
912 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
913 x2apic_preenabled = x2apic = 1;
914 apic_ops = &x2apic_ops;
918 void enable_x2apic(void)
922 rdmsr(MSR_IA32_APICBASE, msr, msr2);
923 if (!(msr & X2APIC_ENABLE)) {
924 printk("Enabling x2apic\n");
925 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
929 void enable_IR_x2apic(void)
931 #ifdef CONFIG_INTR_REMAP
938 if (!x2apic_preenabled && disable_x2apic) {
940 "Skipped enabling x2apic and Interrupt-remapping "
941 "because of nox2apic\n");
945 if (x2apic_preenabled && disable_x2apic)
946 panic("Bios already enabled x2apic, can't enforce nox2apic");
948 if (!x2apic_preenabled && skip_ioapic_setup) {
950 "Skipped enabling x2apic and Interrupt-remapping "
951 "because of skipping io-apic setup\n");
955 ret = dmar_table_init();
958 "dmar_table_init() failed with %d:\n", ret);
960 if (x2apic_preenabled)
961 panic("x2apic enabled by bios. But IR enabling failed");
964 "Not enabling x2apic,Intr-remapping\n");
968 local_irq_save(flags);
970 save_mask_IO_APIC_setup();
972 ret = enable_intr_remapping(1);
974 if (ret && x2apic_preenabled) {
975 local_irq_restore(flags);
976 panic("x2apic enabled by bios. But IR enabling failed");
984 apic_ops = &x2apic_ops;
992 restore_IO_APIC_setup();
994 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
997 local_irq_restore(flags);
1000 if (!x2apic_preenabled)
1002 "Enabled x2apic and interrupt-remapping\n");
1005 "Enabled Interrupt-remapping\n");
1008 "Failed to enable Interrupt-remapping and x2apic\n");
1010 if (!cpu_has_x2apic)
1013 if (x2apic_preenabled)
1014 panic("x2apic enabled prior OS handover,"
1015 " enable CONFIG_INTR_REMAP");
1017 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1025 * Detect and enable local APICs on non-SMP boards.
1026 * Original code written by Keir Fraser.
1027 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1028 * not correctly set up (usually the APIC timer won't work etc.)
1030 static int __init detect_init_APIC(void)
1032 if (!cpu_has_apic) {
1033 printk(KERN_INFO "No local APIC present\n");
1037 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1038 boot_cpu_physical_apicid = 0;
1042 void __init early_init_lapic_mapping(void)
1044 unsigned long phys_addr;
1047 * If no local APIC can be found then go out
1048 * : it means there is no mpatable and MADT
1050 if (!smp_found_config)
1053 phys_addr = mp_lapic_addr;
1055 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1056 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1057 APIC_BASE, phys_addr);
1060 * Fetch the APIC ID of the BSP in case we have a
1061 * default configuration (or the MP table is broken).
1063 boot_cpu_physical_apicid = read_apic_id();
1067 * init_apic_mappings - initialize APIC mappings
1069 void __init init_apic_mappings(void)
1072 boot_cpu_physical_apicid = read_apic_id();
1077 * If no local APIC can be found then set up a fake all
1078 * zeroes page to simulate the local APIC and another
1079 * one for the IO-APIC.
1081 if (!smp_found_config && detect_init_APIC()) {
1082 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1083 apic_phys = __pa(apic_phys);
1085 apic_phys = mp_lapic_addr;
1087 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1088 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1089 APIC_BASE, apic_phys);
1092 * Fetch the APIC ID of the BSP in case we have a
1093 * default configuration (or the MP table is broken).
1095 boot_cpu_physical_apicid = read_apic_id();
1099 * This initializes the IO-APIC and APIC hardware if this is
1102 int __init APIC_init_uniprocessor(void)
1105 printk(KERN_INFO "Apic disabled\n");
1108 if (!cpu_has_apic) {
1110 printk(KERN_INFO "Apic disabled by BIOS\n");
1115 setup_apic_routing();
1117 verify_local_APIC();
1121 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1122 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1127 * Now enable IO-APICs, actually call clear_IO_APIC
1128 * We need clear_IO_APIC before enabling vector on BP
1130 if (!skip_ioapic_setup && nr_ioapics)
1133 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1134 localise_nmi_watchdog();
1135 end_local_APIC_setup();
1137 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1141 setup_boot_APIC_clock();
1142 check_nmi_watchdog();
1147 * Local APIC interrupts
1151 * This interrupt should _never_ happen with our APIC/SMP architecture
1153 asmlinkage void smp_spurious_interrupt(void)
1159 * Check if this really is a spurious interrupt and ACK it
1160 * if it is a vectored one. Just in case...
1161 * Spurious interrupts should not be ACKed.
1163 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1164 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1167 add_pda(irq_spurious_count, 1);
1172 * This interrupt should never happen with our APIC/SMP architecture
1174 asmlinkage void smp_error_interrupt(void)
1180 /* First tickle the hardware, only then report what went on. -- REW */
1181 v = apic_read(APIC_ESR);
1182 apic_write(APIC_ESR, 0);
1183 v1 = apic_read(APIC_ESR);
1185 atomic_inc(&irq_err_count);
1187 /* Here is what the APIC error bits mean:
1190 2: Send accept error
1191 3: Receive accept error
1193 5: Send illegal vector
1194 6: Received illegal vector
1195 7: Illegal register address
1197 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1198 smp_processor_id(), v , v1);
1203 * * connect_bsp_APIC - attach the APIC to the interrupt system
1205 void __init connect_bsp_APIC(void)
1210 void disconnect_bsp_APIC(int virt_wire_setup)
1212 /* Go back to Virtual Wire compatibility mode */
1213 unsigned long value;
1215 /* For the spurious interrupt use vector F, and enable it */
1216 value = apic_read(APIC_SPIV);
1217 value &= ~APIC_VECTOR_MASK;
1218 value |= APIC_SPIV_APIC_ENABLED;
1220 apic_write(APIC_SPIV, value);
1222 if (!virt_wire_setup) {
1224 * For LVT0 make it edge triggered, active high,
1225 * external and enabled
1227 value = apic_read(APIC_LVT0);
1228 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1229 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1230 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1231 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1232 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1233 apic_write(APIC_LVT0, value);
1236 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1239 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1240 value = apic_read(APIC_LVT1);
1241 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1242 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1243 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1244 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1245 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1246 apic_write(APIC_LVT1, value);
1249 void __cpuinit generic_processor_info(int apicid, int version)
1254 if (num_processors >= NR_CPUS) {
1255 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1256 " Processor ignored.\n", NR_CPUS);
1260 if (num_processors >= maxcpus) {
1261 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1262 " Processor ignored.\n", maxcpus);
1267 cpus_complement(tmp_map, cpu_present_map);
1268 cpu = first_cpu(tmp_map);
1270 physid_set(apicid, phys_cpu_present_map);
1271 if (apicid == boot_cpu_physical_apicid) {
1273 * x86_bios_cpu_apicid is required to have processors listed
1274 * in same order as logical cpu numbers. Hence the first
1275 * entry is BSP, and so on.
1279 if (apicid > max_physical_apicid)
1280 max_physical_apicid = apicid;
1282 /* are we being called early in kernel startup? */
1283 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1284 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1285 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1287 cpu_to_apicid[cpu] = apicid;
1288 bios_cpu_apicid[cpu] = apicid;
1290 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1291 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1294 cpu_set(cpu, cpu_possible_map);
1295 cpu_set(cpu, cpu_present_map);
1298 int hard_smp_processor_id(void)
1300 return read_apic_id();
1309 /* 'active' is true if the local APIC was enabled by us and
1310 not the BIOS; this signifies that we are also responsible
1311 for disabling it before entering apm/acpi suspend */
1313 /* r/w apic fields */
1314 unsigned int apic_id;
1315 unsigned int apic_taskpri;
1316 unsigned int apic_ldr;
1317 unsigned int apic_dfr;
1318 unsigned int apic_spiv;
1319 unsigned int apic_lvtt;
1320 unsigned int apic_lvtpc;
1321 unsigned int apic_lvt0;
1322 unsigned int apic_lvt1;
1323 unsigned int apic_lvterr;
1324 unsigned int apic_tmict;
1325 unsigned int apic_tdcr;
1326 unsigned int apic_thmr;
1329 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1331 unsigned long flags;
1334 if (!apic_pm_state.active)
1337 maxlvt = lapic_get_maxlvt();
1339 apic_pm_state.apic_id = apic_read(APIC_ID);
1340 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1341 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1342 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1343 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1344 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1346 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1347 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1348 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1349 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1350 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1351 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1352 #ifdef CONFIG_X86_MCE_INTEL
1354 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1356 local_irq_save(flags);
1357 disable_local_APIC();
1358 local_irq_restore(flags);
1362 static int lapic_resume(struct sys_device *dev)
1365 unsigned long flags;
1368 if (!apic_pm_state.active)
1371 maxlvt = lapic_get_maxlvt();
1373 local_irq_save(flags);
1375 rdmsr(MSR_IA32_APICBASE, l, h);
1376 l &= ~MSR_IA32_APICBASE_BASE;
1377 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1378 wrmsr(MSR_IA32_APICBASE, l, h);
1382 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1383 apic_write(APIC_ID, apic_pm_state.apic_id);
1384 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1385 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1386 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1387 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1388 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1389 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1390 #ifdef CONFIG_X86_MCE_INTEL
1392 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1395 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1396 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1397 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1398 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1399 apic_write(APIC_ESR, 0);
1400 apic_read(APIC_ESR);
1401 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1402 apic_write(APIC_ESR, 0);
1403 apic_read(APIC_ESR);
1404 local_irq_restore(flags);
1408 static struct sysdev_class lapic_sysclass = {
1410 .resume = lapic_resume,
1411 .suspend = lapic_suspend,
1414 static struct sys_device device_lapic = {
1416 .cls = &lapic_sysclass,
1419 static void __cpuinit apic_pm_activate(void)
1421 apic_pm_state.active = 1;
1424 static int __init init_lapic_sysfs(void)
1430 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1432 error = sysdev_class_register(&lapic_sysclass);
1434 error = sysdev_register(&device_lapic);
1437 device_initcall(init_lapic_sysfs);
1439 #else /* CONFIG_PM */
1441 static void apic_pm_activate(void) { }
1443 #endif /* CONFIG_PM */
1446 * apic_is_clustered_box() -- Check if we can expect good TSC
1448 * Thus far, the major user of this is IBM's Summit2 series:
1450 * Clustered boxes may have unsynced TSC problems if they are
1451 * multi-chassis. Use available data to take a good guess.
1452 * If in doubt, go HPET.
1454 __cpuinit int apic_is_clustered_box(void)
1456 int i, clusters, zeros;
1458 u16 *bios_cpu_apicid;
1459 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1462 * there is not this kind of box with AMD CPU yet.
1463 * Some AMD box with quadcore cpu and 8 sockets apicid
1464 * will be [4, 0x23] or [8, 0x27] could be thought to
1465 * vsmp box still need checking...
1467 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1470 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1471 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1473 for (i = 0; i < NR_CPUS; i++) {
1474 /* are we being called early in kernel startup? */
1475 if (bios_cpu_apicid) {
1476 id = bios_cpu_apicid[i];
1478 else if (i < nr_cpu_ids) {
1480 id = per_cpu(x86_bios_cpu_apicid, i);
1487 if (id != BAD_APICID)
1488 __set_bit(APIC_CLUSTERID(id), clustermap);
1491 /* Problem: Partially populated chassis may not have CPUs in some of
1492 * the APIC clusters they have been allocated. Only present CPUs have
1493 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1494 * Since clusters are allocated sequentially, count zeros only if
1495 * they are bounded by ones.
1499 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1500 if (test_bit(i, clustermap)) {
1501 clusters += 1 + zeros;
1507 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1508 * not guaranteed to be synced between boards
1510 if (is_vsmp_box() && clusters > 1)
1514 * If clusters > 2, then should be multi-chassis.
1515 * May have to revisit this when multi-core + hyperthreaded CPUs come
1516 * out, but AFAIK this will work even for them.
1518 return (clusters > 2);
1521 static __init int setup_nox2apic(char *str)
1524 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1527 early_param("nox2apic", setup_nox2apic);
1531 * APIC command line parameters
1533 static int __init apic_set_verbosity(char *str)
1536 skip_ioapic_setup = 0;
1540 if (strcmp("debug", str) == 0)
1541 apic_verbosity = APIC_DEBUG;
1542 else if (strcmp("verbose", str) == 0)
1543 apic_verbosity = APIC_VERBOSE;
1545 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1546 " use apic=verbose or apic=debug\n", str);
1552 early_param("apic", apic_set_verbosity);
1554 static __init int setup_disableapic(char *str)
1557 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1560 early_param("disableapic", setup_disableapic);
1562 /* same as disableapic, for compatibility */
1563 static __init int setup_nolapic(char *str)
1565 return setup_disableapic(str);
1567 early_param("nolapic", setup_nolapic);
1569 static int __init parse_lapic_timer_c2_ok(char *arg)
1571 local_apic_timer_c2_ok = 1;
1574 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1576 static __init int setup_noapictimer(char *str)
1578 if (str[0] != ' ' && str[0] != 0)
1580 disable_apic_timer = 1;
1583 __setup("noapictimer", setup_noapictimer);
1585 static __init int setup_apicpmtimer(char *s)
1587 apic_calibrate_pmtmr = 1;
1591 __setup("apicpmtimer", setup_apicpmtimer);
1593 static int __init lapic_insert_resource(void)
1598 /* Put local APIC into the resource map. */
1599 lapic_resource.start = apic_phys;
1600 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1601 insert_resource(&iomem_resource, &lapic_resource);
1607 * need call insert after e820_reserve_resources()
1608 * that is using request_resource
1610 late_initcall(lapic_insert_resource);