2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 static int disable_apic_timer __cpuinitdata;
49 static int apic_calibrate_pmtmr __initdata;
54 /* x2apic enabled before OS handover */
55 int x2apic_preenabled;
57 /* Local APIC timer works in C2 */
58 int local_apic_timer_c2_ok;
59 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
62 * Debug level, exported for io_apic.c
64 unsigned int apic_verbosity;
66 /* Have we found an MP table */
69 static struct resource lapic_resource = {
71 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
74 static unsigned int calibration_result;
76 static int lapic_next_event(unsigned long delta,
77 struct clock_event_device *evt);
78 static void lapic_timer_setup(enum clock_event_mode mode,
79 struct clock_event_device *evt);
80 static void lapic_timer_broadcast(cpumask_t mask);
81 static void apic_pm_activate(void);
83 static struct clock_event_device lapic_clockevent = {
85 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
86 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
88 .set_mode = lapic_timer_setup,
89 .set_next_event = lapic_next_event,
90 .broadcast = lapic_timer_broadcast,
94 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
96 static unsigned long apic_phys;
98 unsigned long mp_lapic_addr;
100 unsigned int __cpuinitdata maxcpus = NR_CPUS;
102 * Get the LAPIC version
104 static inline int lapic_get_version(void)
106 return GET_APIC_VERSION(apic_read(APIC_LVR));
110 * Check, if the APIC is integrated or a seperate chip
112 static inline int lapic_is_integrated(void)
118 * Check, whether this is a modern or a first generation APIC
120 static int modern_apic(void)
122 /* AMD systems use old APIC versions, so check the CPU */
123 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
124 boot_cpu_data.x86 >= 0xf)
126 return lapic_get_version() >= 0x14;
129 void xapic_wait_icr_idle(void)
131 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
135 u32 safe_xapic_wait_icr_idle(void)
142 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
146 } while (timeout++ < 1000);
151 void xapic_icr_write(u32 low, u32 id)
153 apic_write(APIC_ICR2, id << 24);
154 apic_write(APIC_ICR, low);
157 u64 xapic_icr_read(void)
161 icr2 = apic_read(APIC_ICR2);
162 icr1 = apic_read(APIC_ICR);
164 return (icr1 | ((u64)icr2 << 32));
167 static struct apic_ops xapic_ops = {
168 .read = native_apic_mem_read,
169 .write = native_apic_mem_write,
170 .write_atomic = native_apic_mem_write_atomic,
171 .icr_read = xapic_icr_read,
172 .icr_write = xapic_icr_write,
173 .wait_icr_idle = xapic_wait_icr_idle,
174 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
177 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
179 EXPORT_SYMBOL_GPL(apic_ops);
181 static void x2apic_wait_icr_idle(void)
183 /* no need to wait for icr idle in x2apic */
187 static u32 safe_x2apic_wait_icr_idle(void)
189 /* no need to wait for icr idle in x2apic */
193 void x2apic_icr_write(u32 low, u32 id)
195 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
198 u64 x2apic_icr_read(void)
202 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
206 static struct apic_ops x2apic_ops = {
207 .read = native_apic_msr_read,
208 .write = native_apic_msr_write,
209 .write_atomic = native_apic_msr_write,
210 .icr_read = x2apic_icr_read,
211 .icr_write = x2apic_icr_write,
212 .wait_icr_idle = x2apic_wait_icr_idle,
213 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
217 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
219 void __cpuinit enable_NMI_through_LVT0(void)
223 /* unmask and set to NMI */
225 apic_write(APIC_LVT0, v);
229 * lapic_get_maxlvt - get the maximum number of local vector table entries
231 int lapic_get_maxlvt(void)
233 unsigned int v, maxlvt;
235 v = apic_read(APIC_LVR);
236 maxlvt = GET_APIC_MAXLVT(v);
241 * This function sets up the local APIC timer, with a timeout of
242 * 'clocks' APIC bus clock. During calibration we actually call
243 * this function twice on the boot CPU, once with a bogus timeout
244 * value, second time for real. The other (noncalibrating) CPUs
245 * call this function only once, with the real, calibrated value.
247 * We do reads before writes even if unnecessary, to get around the
248 * P5 APIC double write bug.
251 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
253 unsigned int lvtt_value, tmp_value;
255 lvtt_value = LOCAL_TIMER_VECTOR;
257 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
259 lvtt_value |= APIC_LVT_MASKED;
261 apic_write(APIC_LVTT, lvtt_value);
266 tmp_value = apic_read(APIC_TDCR);
267 apic_write(APIC_TDCR, (tmp_value
268 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
272 apic_write(APIC_TMICT, clocks);
276 * Setup extended LVT, AMD specific (K8, family 10h)
278 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
279 * MCE interrupts are supported. Thus MCE offset must be set to 0.
282 #define APIC_EILVT_LVTOFF_MCE 0
283 #define APIC_EILVT_LVTOFF_IBS 1
285 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
287 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
288 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
293 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
295 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
296 return APIC_EILVT_LVTOFF_MCE;
299 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
301 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
302 return APIC_EILVT_LVTOFF_IBS;
306 * Program the next event, relative to now
308 static int lapic_next_event(unsigned long delta,
309 struct clock_event_device *evt)
311 apic_write(APIC_TMICT, delta);
316 * Setup the lapic timer in periodic or oneshot mode
318 static void lapic_timer_setup(enum clock_event_mode mode,
319 struct clock_event_device *evt)
324 /* Lapic used as dummy for broadcast ? */
325 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
328 local_irq_save(flags);
331 case CLOCK_EVT_MODE_PERIODIC:
332 case CLOCK_EVT_MODE_ONESHOT:
333 __setup_APIC_LVTT(calibration_result,
334 mode != CLOCK_EVT_MODE_PERIODIC, 1);
336 case CLOCK_EVT_MODE_UNUSED:
337 case CLOCK_EVT_MODE_SHUTDOWN:
338 v = apic_read(APIC_LVTT);
339 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
340 apic_write(APIC_LVTT, v);
342 case CLOCK_EVT_MODE_RESUME:
343 /* Nothing to do here */
347 local_irq_restore(flags);
351 * Local APIC timer broadcast function
353 static void lapic_timer_broadcast(cpumask_t mask)
356 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
361 * Setup the local APIC timer for this CPU. Copy the initilized values
362 * of the boot CPU and register the clock event in the framework.
364 static void setup_APIC_timer(void)
366 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
368 memcpy(levt, &lapic_clockevent, sizeof(*levt));
369 levt->cpumask = cpumask_of_cpu(smp_processor_id());
371 clockevents_register_device(levt);
375 * In this function we calibrate APIC bus clocks to the external
376 * timer. Unfortunately we cannot use jiffies and the timer irq
377 * to calibrate, since some later bootup code depends on getting
378 * the first irq? Ugh.
380 * We want to do the calibration only once since we
381 * want to have local timer irqs syncron. CPUs connected
382 * by the same APIC bus have the very same bus frequency.
383 * And we want to have irqs off anyways, no accidental
387 #define TICK_COUNT 100000000
389 static int __init calibrate_APIC_clock(void)
391 unsigned apic, apic_start;
392 unsigned long tsc, tsc_start;
398 * Put whatever arbitrary (but long enough) timeout
399 * value into the APIC clock, we just want to get the
400 * counter running for calibration.
402 * No interrupt enable !
404 __setup_APIC_LVTT(250000000, 0, 0);
406 apic_start = apic_read(APIC_TMCCT);
407 #ifdef CONFIG_X86_PM_TIMER
408 if (apic_calibrate_pmtmr && pmtmr_ioport) {
409 pmtimer_wait(5000); /* 5ms wait */
410 apic = apic_read(APIC_TMCCT);
411 result = (apic_start - apic) * 1000L / 5;
418 apic = apic_read(APIC_TMCCT);
420 } while ((tsc - tsc_start) < TICK_COUNT &&
421 (apic_start - apic) < TICK_COUNT);
423 result = (apic_start - apic) * 1000L * tsc_khz /
429 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
431 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
432 result / 1000 / 1000, result / 1000 % 1000);
434 /* Calculate the scaled math multiplication factor */
435 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
436 lapic_clockevent.shift);
437 lapic_clockevent.max_delta_ns =
438 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
439 lapic_clockevent.min_delta_ns =
440 clockevent_delta2ns(0xF, &lapic_clockevent);
442 calibration_result = result / HZ;
445 * Do a sanity check on the APIC calibration result
447 if (calibration_result < (1000000 / HZ)) {
449 "APIC frequency too slow, disabling apic timer\n");
457 * Setup the boot APIC
459 * Calibrate and verify the result.
461 void __init setup_boot_APIC_clock(void)
464 * The local apic timer can be disabled via the kernel commandline.
465 * Register the lapic timer as a dummy clock event source on SMP
466 * systems, so the broadcast mechanism is used. On UP systems simply
469 if (disable_apic_timer) {
470 printk(KERN_INFO "Disabling APIC timer\n");
471 /* No broadcast on UP ! */
472 if (num_possible_cpus() > 1) {
473 lapic_clockevent.mult = 1;
479 printk(KERN_INFO "Using local APIC timer interrupts.\n");
480 if (calibrate_APIC_clock()) {
481 /* No broadcast on UP ! */
482 if (num_possible_cpus() > 1)
488 * If nmi_watchdog is set to IO_APIC, we need the
489 * PIT/HPET going. Otherwise register lapic as a dummy
492 if (nmi_watchdog != NMI_IO_APIC)
493 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
495 printk(KERN_WARNING "APIC timer registered as dummy,"
496 " due to nmi_watchdog=%d!\n", nmi_watchdog);
501 void __cpuinit setup_secondary_APIC_clock(void)
507 * The guts of the apic timer interrupt
509 static void local_apic_timer_interrupt(void)
511 int cpu = smp_processor_id();
512 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
515 * Normally we should not be here till LAPIC has been initialized but
516 * in some cases like kdump, its possible that there is a pending LAPIC
517 * timer interrupt from previous kernel's context and is delivered in
518 * new kernel the moment interrupts are enabled.
520 * Interrupts are enabled early and LAPIC is setup much later, hence
521 * its possible that when we get here evt->event_handler is NULL.
522 * Check for event_handler being NULL and discard the interrupt as
525 if (!evt->event_handler) {
527 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
529 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
534 * the NMI deadlock-detector uses this.
536 add_pda(apic_timer_irqs, 1);
538 evt->event_handler(evt);
542 * Local APIC timer interrupt. This is the most natural way for doing
543 * local interrupts, but local timer interrupts can be emulated by
544 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
546 * [ if a single-CPU system runs an SMP kernel then we call the local
547 * interrupt as well. Thus we cannot inline the local irq ... ]
549 void smp_apic_timer_interrupt(struct pt_regs *regs)
551 struct pt_regs *old_regs = set_irq_regs(regs);
554 * NOTE! We'd better ACK the irq immediately,
555 * because timer handling can be slow.
559 * update_process_times() expects us to have done irq_enter().
560 * Besides, if we don't timer interrupts ignore the global
561 * interrupt lock, which is the WrongThing (tm) to do.
565 local_apic_timer_interrupt();
567 set_irq_regs(old_regs);
570 int setup_profiling_timer(unsigned int multiplier)
577 * Local APIC start and shutdown
581 * clear_local_APIC - shutdown the local APIC
583 * This is called, when a CPU is disabled and before rebooting, so the state of
584 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
585 * leftovers during boot.
587 void clear_local_APIC(void)
592 /* APIC hasn't been mapped yet */
596 maxlvt = lapic_get_maxlvt();
598 * Masking an LVT entry can trigger a local APIC error
599 * if the vector is zero. Mask LVTERR first to prevent this.
602 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
603 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
606 * Careful: we have to set masks only first to deassert
607 * any level-triggered sources.
609 v = apic_read(APIC_LVTT);
610 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
611 v = apic_read(APIC_LVT0);
612 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
613 v = apic_read(APIC_LVT1);
614 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
616 v = apic_read(APIC_LVTPC);
617 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
621 * Clean APIC state for other OSs:
623 apic_write(APIC_LVTT, APIC_LVT_MASKED);
624 apic_write(APIC_LVT0, APIC_LVT_MASKED);
625 apic_write(APIC_LVT1, APIC_LVT_MASKED);
627 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
629 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
630 apic_write(APIC_ESR, 0);
635 * disable_local_APIC - clear and disable the local APIC
637 void disable_local_APIC(void)
644 * Disable APIC (implies clearing of registers
647 value = apic_read(APIC_SPIV);
648 value &= ~APIC_SPIV_APIC_ENABLED;
649 apic_write(APIC_SPIV, value);
652 void lapic_shutdown(void)
659 local_irq_save(flags);
661 disable_local_APIC();
663 local_irq_restore(flags);
667 * This is to verify that we're looking at a real local APIC.
668 * Check these against your board if the CPUs aren't getting
669 * started for no apparent reason.
671 int __init verify_local_APIC(void)
673 unsigned int reg0, reg1;
676 * The version register is read-only in a real APIC.
678 reg0 = apic_read(APIC_LVR);
679 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
680 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
681 reg1 = apic_read(APIC_LVR);
682 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
685 * The two version reads above should print the same
686 * numbers. If the second one is different, then we
687 * poke at a non-APIC.
693 * Check if the version looks reasonably.
695 reg1 = GET_APIC_VERSION(reg0);
696 if (reg1 == 0x00 || reg1 == 0xff)
698 reg1 = lapic_get_maxlvt();
699 if (reg1 < 0x02 || reg1 == 0xff)
703 * The ID register is read/write in a real APIC.
705 reg0 = apic_read(APIC_ID);
706 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
707 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
708 reg1 = apic_read(APIC_ID);
709 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
710 apic_write(APIC_ID, reg0);
711 if (reg1 != (reg0 ^ APIC_ID_MASK))
715 * The next two are just to see if we have sane values.
716 * They're only really relevant if we're in Virtual Wire
717 * compatibility mode, but most boxes are anymore.
719 reg0 = apic_read(APIC_LVT0);
720 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
721 reg1 = apic_read(APIC_LVT1);
722 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
728 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
730 void __init sync_Arb_IDs(void)
732 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
739 apic_wait_icr_idle();
741 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
742 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
747 * An initial setup of the virtual wire mode.
749 void __init init_bsp_APIC(void)
754 * Don't do the setup now if we have a SMP BIOS as the
755 * through-I/O-APIC virtual wire mode might be active.
757 if (smp_found_config || !cpu_has_apic)
760 value = apic_read(APIC_LVR);
763 * Do not trust the local APIC being empty at bootup.
770 value = apic_read(APIC_SPIV);
771 value &= ~APIC_VECTOR_MASK;
772 value |= APIC_SPIV_APIC_ENABLED;
773 value |= APIC_SPIV_FOCUS_DISABLED;
774 value |= SPURIOUS_APIC_VECTOR;
775 apic_write(APIC_SPIV, value);
778 * Set up the virtual wire mode.
780 apic_write(APIC_LVT0, APIC_DM_EXTINT);
782 apic_write(APIC_LVT1, value);
786 * setup_local_APIC - setup the local APIC
788 void __cpuinit setup_local_APIC(void)
794 value = apic_read(APIC_LVR);
796 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
799 * Double-check whether this APIC is really registered.
800 * This is meaningless in clustered apic mode, so we skip it.
802 if (!apic_id_registered())
806 * Intel recommends to set DFR, LDR and TPR before enabling
807 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
808 * document number 292116). So here it goes...
813 * Set Task Priority to 'accept all'. We never change this
816 value = apic_read(APIC_TASKPRI);
817 value &= ~APIC_TPRI_MASK;
818 apic_write(APIC_TASKPRI, value);
821 * After a crash, we no longer service the interrupts and a pending
822 * interrupt from previous kernel might still have ISR bit set.
824 * Most probably by now CPU has serviced that pending interrupt and
825 * it might not have done the ack_APIC_irq() because it thought,
826 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
827 * does not clear the ISR bit and cpu thinks it has already serivced
828 * the interrupt. Hence a vector might get locked. It was noticed
829 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
831 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
832 value = apic_read(APIC_ISR + i*0x10);
833 for (j = 31; j >= 0; j--) {
840 * Now that we are all set up, enable the APIC
842 value = apic_read(APIC_SPIV);
843 value &= ~APIC_VECTOR_MASK;
847 value |= APIC_SPIV_APIC_ENABLED;
849 /* We always use processor focus */
852 * Set spurious IRQ vector
854 value |= SPURIOUS_APIC_VECTOR;
855 apic_write(APIC_SPIV, value);
860 * set up through-local-APIC on the BP's LINT0. This is not
861 * strictly necessary in pure symmetric-IO mode, but sometimes
862 * we delegate interrupts to the 8259A.
865 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
867 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
868 if (!smp_processor_id() && !value) {
869 value = APIC_DM_EXTINT;
870 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
873 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
874 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
877 apic_write(APIC_LVT0, value);
880 * only the BP should see the LINT1 NMI signal, obviously.
882 if (!smp_processor_id())
885 value = APIC_DM_NMI | APIC_LVT_MASKED;
886 apic_write(APIC_LVT1, value);
890 static void __cpuinit lapic_setup_esr(void)
892 unsigned maxlvt = lapic_get_maxlvt();
894 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
896 * spec says clear errors after enabling vector.
899 apic_write(APIC_ESR, 0);
902 void __cpuinit end_local_APIC_setup(void)
905 setup_apic_nmi_watchdog(NULL);
909 void check_x2apic(void)
913 rdmsr(MSR_IA32_APICBASE, msr, msr2);
915 if (msr & X2APIC_ENABLE) {
916 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
917 x2apic_preenabled = x2apic = 1;
918 apic_ops = &x2apic_ops;
922 void enable_x2apic(void)
926 rdmsr(MSR_IA32_APICBASE, msr, msr2);
927 if (!(msr & X2APIC_ENABLE)) {
928 printk("Enabling x2apic\n");
929 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
933 void enable_IR_x2apic(void)
935 #ifdef CONFIG_INTR_REMAP
942 if (!x2apic_preenabled && disable_x2apic) {
944 "Skipped enabling x2apic and Interrupt-remapping "
945 "because of nox2apic\n");
949 if (x2apic_preenabled && disable_x2apic)
950 panic("Bios already enabled x2apic, can't enforce nox2apic");
952 if (!x2apic_preenabled && skip_ioapic_setup) {
954 "Skipped enabling x2apic and Interrupt-remapping "
955 "because of skipping io-apic setup\n");
959 ret = dmar_table_init();
962 "dmar_table_init() failed with %d:\n", ret);
964 if (x2apic_preenabled)
965 panic("x2apic enabled by bios. But IR enabling failed");
968 "Not enabling x2apic,Intr-remapping\n");
972 local_irq_save(flags);
974 save_mask_IO_APIC_setup();
976 ret = enable_intr_remapping(1);
978 if (ret && x2apic_preenabled) {
979 local_irq_restore(flags);
980 panic("x2apic enabled by bios. But IR enabling failed");
988 apic_ops = &x2apic_ops;
996 restore_IO_APIC_setup();
998 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1001 local_irq_restore(flags);
1004 if (!x2apic_preenabled)
1006 "Enabled x2apic and interrupt-remapping\n");
1009 "Enabled Interrupt-remapping\n");
1012 "Failed to enable Interrupt-remapping and x2apic\n");
1014 if (!cpu_has_x2apic)
1017 if (x2apic_preenabled)
1018 panic("x2apic enabled prior OS handover,"
1019 " enable CONFIG_INTR_REMAP");
1021 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1029 * Detect and enable local APICs on non-SMP boards.
1030 * Original code written by Keir Fraser.
1031 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1032 * not correctly set up (usually the APIC timer won't work etc.)
1034 static int __init detect_init_APIC(void)
1036 if (!cpu_has_apic) {
1037 printk(KERN_INFO "No local APIC present\n");
1041 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1042 boot_cpu_physical_apicid = 0;
1046 void __init early_init_lapic_mapping(void)
1048 unsigned long phys_addr;
1051 * If no local APIC can be found then go out
1052 * : it means there is no mpatable and MADT
1054 if (!smp_found_config)
1057 phys_addr = mp_lapic_addr;
1059 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1060 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1061 APIC_BASE, phys_addr);
1064 * Fetch the APIC ID of the BSP in case we have a
1065 * default configuration (or the MP table is broken).
1067 boot_cpu_physical_apicid = read_apic_id();
1071 * init_apic_mappings - initialize APIC mappings
1073 void __init init_apic_mappings(void)
1076 boot_cpu_physical_apicid = read_apic_id();
1081 * If no local APIC can be found then set up a fake all
1082 * zeroes page to simulate the local APIC and another
1083 * one for the IO-APIC.
1085 if (!smp_found_config && detect_init_APIC()) {
1086 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1087 apic_phys = __pa(apic_phys);
1089 apic_phys = mp_lapic_addr;
1091 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1092 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1093 APIC_BASE, apic_phys);
1096 * Fetch the APIC ID of the BSP in case we have a
1097 * default configuration (or the MP table is broken).
1099 boot_cpu_physical_apicid = read_apic_id();
1103 * This initializes the IO-APIC and APIC hardware if this is
1106 int __init APIC_init_uniprocessor(void)
1109 printk(KERN_INFO "Apic disabled\n");
1112 if (!cpu_has_apic) {
1114 printk(KERN_INFO "Apic disabled by BIOS\n");
1119 setup_apic_routing();
1121 verify_local_APIC();
1125 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1126 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1131 * Now enable IO-APICs, actually call clear_IO_APIC
1132 * We need clear_IO_APIC before enabling vector on BP
1134 if (!skip_ioapic_setup && nr_ioapics)
1137 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1138 localise_nmi_watchdog();
1139 end_local_APIC_setup();
1141 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1145 setup_boot_APIC_clock();
1146 check_nmi_watchdog();
1151 * Local APIC interrupts
1155 * This interrupt should _never_ happen with our APIC/SMP architecture
1157 asmlinkage void smp_spurious_interrupt(void)
1163 * Check if this really is a spurious interrupt and ACK it
1164 * if it is a vectored one. Just in case...
1165 * Spurious interrupts should not be ACKed.
1167 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1168 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1171 add_pda(irq_spurious_count, 1);
1176 * This interrupt should never happen with our APIC/SMP architecture
1178 asmlinkage void smp_error_interrupt(void)
1184 /* First tickle the hardware, only then report what went on. -- REW */
1185 v = apic_read(APIC_ESR);
1186 apic_write(APIC_ESR, 0);
1187 v1 = apic_read(APIC_ESR);
1189 atomic_inc(&irq_err_count);
1191 /* Here is what the APIC error bits mean:
1194 2: Send accept error
1195 3: Receive accept error
1197 5: Send illegal vector
1198 6: Received illegal vector
1199 7: Illegal register address
1201 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1202 smp_processor_id(), v , v1);
1207 * * connect_bsp_APIC - attach the APIC to the interrupt system
1209 void __init connect_bsp_APIC(void)
1214 void disconnect_bsp_APIC(int virt_wire_setup)
1216 /* Go back to Virtual Wire compatibility mode */
1217 unsigned long value;
1219 /* For the spurious interrupt use vector F, and enable it */
1220 value = apic_read(APIC_SPIV);
1221 value &= ~APIC_VECTOR_MASK;
1222 value |= APIC_SPIV_APIC_ENABLED;
1224 apic_write(APIC_SPIV, value);
1226 if (!virt_wire_setup) {
1228 * For LVT0 make it edge triggered, active high,
1229 * external and enabled
1231 value = apic_read(APIC_LVT0);
1232 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1233 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1234 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1235 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1236 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1237 apic_write(APIC_LVT0, value);
1240 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1243 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1244 value = apic_read(APIC_LVT1);
1245 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1246 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1247 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1248 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1249 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1250 apic_write(APIC_LVT1, value);
1253 void __cpuinit generic_processor_info(int apicid, int version)
1258 if (num_processors >= NR_CPUS) {
1259 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1260 " Processor ignored.\n", NR_CPUS);
1264 if (num_processors >= maxcpus) {
1265 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1266 " Processor ignored.\n", maxcpus);
1271 cpus_complement(tmp_map, cpu_present_map);
1272 cpu = first_cpu(tmp_map);
1274 physid_set(apicid, phys_cpu_present_map);
1275 if (apicid == boot_cpu_physical_apicid) {
1277 * x86_bios_cpu_apicid is required to have processors listed
1278 * in same order as logical cpu numbers. Hence the first
1279 * entry is BSP, and so on.
1283 if (apicid > max_physical_apicid)
1284 max_physical_apicid = apicid;
1286 /* are we being called early in kernel startup? */
1287 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1288 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1289 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1291 cpu_to_apicid[cpu] = apicid;
1292 bios_cpu_apicid[cpu] = apicid;
1294 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1295 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1298 cpu_set(cpu, cpu_possible_map);
1299 cpu_set(cpu, cpu_present_map);
1302 int hard_smp_processor_id(void)
1304 return read_apic_id();
1313 /* 'active' is true if the local APIC was enabled by us and
1314 not the BIOS; this signifies that we are also responsible
1315 for disabling it before entering apm/acpi suspend */
1317 /* r/w apic fields */
1318 unsigned int apic_id;
1319 unsigned int apic_taskpri;
1320 unsigned int apic_ldr;
1321 unsigned int apic_dfr;
1322 unsigned int apic_spiv;
1323 unsigned int apic_lvtt;
1324 unsigned int apic_lvtpc;
1325 unsigned int apic_lvt0;
1326 unsigned int apic_lvt1;
1327 unsigned int apic_lvterr;
1328 unsigned int apic_tmict;
1329 unsigned int apic_tdcr;
1330 unsigned int apic_thmr;
1333 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1335 unsigned long flags;
1338 if (!apic_pm_state.active)
1341 maxlvt = lapic_get_maxlvt();
1343 apic_pm_state.apic_id = apic_read(APIC_ID);
1344 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1345 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1346 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1347 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1348 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1350 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1351 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1352 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1353 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1354 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1355 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1356 #ifdef CONFIG_X86_MCE_INTEL
1358 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1360 local_irq_save(flags);
1361 disable_local_APIC();
1362 local_irq_restore(flags);
1366 static int lapic_resume(struct sys_device *dev)
1369 unsigned long flags;
1372 if (!apic_pm_state.active)
1375 maxlvt = lapic_get_maxlvt();
1377 local_irq_save(flags);
1379 rdmsr(MSR_IA32_APICBASE, l, h);
1380 l &= ~MSR_IA32_APICBASE_BASE;
1381 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1382 wrmsr(MSR_IA32_APICBASE, l, h);
1386 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1387 apic_write(APIC_ID, apic_pm_state.apic_id);
1388 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1389 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1390 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1391 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1392 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1393 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1394 #ifdef CONFIG_X86_MCE_INTEL
1396 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1399 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1400 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1401 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1402 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1403 apic_write(APIC_ESR, 0);
1404 apic_read(APIC_ESR);
1405 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1406 apic_write(APIC_ESR, 0);
1407 apic_read(APIC_ESR);
1408 local_irq_restore(flags);
1412 static struct sysdev_class lapic_sysclass = {
1414 .resume = lapic_resume,
1415 .suspend = lapic_suspend,
1418 static struct sys_device device_lapic = {
1420 .cls = &lapic_sysclass,
1423 static void __cpuinit apic_pm_activate(void)
1425 apic_pm_state.active = 1;
1428 static int __init init_lapic_sysfs(void)
1434 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1436 error = sysdev_class_register(&lapic_sysclass);
1438 error = sysdev_register(&device_lapic);
1441 device_initcall(init_lapic_sysfs);
1443 #else /* CONFIG_PM */
1445 static void apic_pm_activate(void) { }
1447 #endif /* CONFIG_PM */
1450 * apic_is_clustered_box() -- Check if we can expect good TSC
1452 * Thus far, the major user of this is IBM's Summit2 series:
1454 * Clustered boxes may have unsynced TSC problems if they are
1455 * multi-chassis. Use available data to take a good guess.
1456 * If in doubt, go HPET.
1458 __cpuinit int apic_is_clustered_box(void)
1460 int i, clusters, zeros;
1462 u16 *bios_cpu_apicid;
1463 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1466 * there is not this kind of box with AMD CPU yet.
1467 * Some AMD box with quadcore cpu and 8 sockets apicid
1468 * will be [4, 0x23] or [8, 0x27] could be thought to
1469 * vsmp box still need checking...
1471 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1474 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1475 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1477 for (i = 0; i < NR_CPUS; i++) {
1478 /* are we being called early in kernel startup? */
1479 if (bios_cpu_apicid) {
1480 id = bios_cpu_apicid[i];
1482 else if (i < nr_cpu_ids) {
1484 id = per_cpu(x86_bios_cpu_apicid, i);
1491 if (id != BAD_APICID)
1492 __set_bit(APIC_CLUSTERID(id), clustermap);
1495 /* Problem: Partially populated chassis may not have CPUs in some of
1496 * the APIC clusters they have been allocated. Only present CPUs have
1497 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1498 * Since clusters are allocated sequentially, count zeros only if
1499 * they are bounded by ones.
1503 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1504 if (test_bit(i, clustermap)) {
1505 clusters += 1 + zeros;
1511 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1512 * not guaranteed to be synced between boards
1514 if (is_vsmp_box() && clusters > 1)
1518 * If clusters > 2, then should be multi-chassis.
1519 * May have to revisit this when multi-core + hyperthreaded CPUs come
1520 * out, but AFAIK this will work even for them.
1522 return (clusters > 2);
1525 static __init int setup_nox2apic(char *str)
1528 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1531 early_param("nox2apic", setup_nox2apic);
1535 * APIC command line parameters
1537 static int __init apic_set_verbosity(char *str)
1540 skip_ioapic_setup = 0;
1544 if (strcmp("debug", str) == 0)
1545 apic_verbosity = APIC_DEBUG;
1546 else if (strcmp("verbose", str) == 0)
1547 apic_verbosity = APIC_VERBOSE;
1549 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1550 " use apic=verbose or apic=debug\n", str);
1556 early_param("apic", apic_set_verbosity);
1558 static __init int setup_disableapic(char *str)
1561 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1564 early_param("disableapic", setup_disableapic);
1566 /* same as disableapic, for compatibility */
1567 static __init int setup_nolapic(char *str)
1569 return setup_disableapic(str);
1571 early_param("nolapic", setup_nolapic);
1573 static int __init parse_lapic_timer_c2_ok(char *arg)
1575 local_apic_timer_c2_ok = 1;
1578 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1580 static __init int setup_noapictimer(char *str)
1582 if (str[0] != ' ' && str[0] != 0)
1584 disable_apic_timer = 1;
1587 __setup("noapictimer", setup_noapictimer);
1589 static __init int setup_apicpmtimer(char *s)
1591 apic_calibrate_pmtmr = 1;
1595 __setup("apicpmtimer", setup_apicpmtimer);
1597 static int __init lapic_insert_resource(void)
1602 /* Put local APIC into the resource map. */
1603 lapic_resource.start = apic_phys;
1604 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1605 insert_resource(&iomem_resource, &lapic_resource);
1611 * need call insert after e820_reserve_resources()
1612 * that is using request_resource
1614 late_initcall(lapic_insert_resource);