2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
49 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
50 static int disable_apic_timer __cpuinitdata;
51 static int apic_calibrate_pmtmr __initdata;
56 /* x2apic enabled before OS handover */
57 int x2apic_preenabled;
59 /* Local APIC timer works in C2 */
60 int local_apic_timer_c2_ok;
61 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
63 int first_system_vector = 0xfe;
65 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
68 * Debug level, exported for io_apic.c
70 unsigned int apic_verbosity;
72 /* Have we found an MP table */
75 static struct resource lapic_resource = {
77 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
80 static unsigned int calibration_result;
82 static int lapic_next_event(unsigned long delta,
83 struct clock_event_device *evt);
84 static void lapic_timer_setup(enum clock_event_mode mode,
85 struct clock_event_device *evt);
86 static void lapic_timer_broadcast(cpumask_t mask);
87 static void apic_pm_activate(void);
90 * The local apic timer can be used for any function which is CPU local.
92 static struct clock_event_device lapic_clockevent = {
94 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
95 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
97 .set_mode = lapic_timer_setup,
98 .set_next_event = lapic_next_event,
99 .broadcast = lapic_timer_broadcast,
103 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
105 static unsigned long apic_phys;
107 unsigned long mp_lapic_addr;
110 * Get the LAPIC version
112 static inline int lapic_get_version(void)
114 return GET_APIC_VERSION(apic_read(APIC_LVR));
118 * Check, if the APIC is integrated or a separate chip
120 static inline int lapic_is_integrated(void)
125 return APIC_INTEGRATED(lapic_get_version());
130 * Check, whether this is a modern or a first generation APIC
132 static int modern_apic(void)
134 /* AMD systems use old APIC versions, so check the CPU */
135 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
136 boot_cpu_data.x86 >= 0xf)
138 return lapic_get_version() >= 0x14;
142 * Paravirt kernels also might be using these below ops. So we still
143 * use generic apic_read()/apic_write(), which might be pointing to different
144 * ops in PARAVIRT case.
146 void xapic_wait_icr_idle(void)
148 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
152 u32 safe_xapic_wait_icr_idle(void)
159 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
163 } while (timeout++ < 1000);
168 void xapic_icr_write(u32 low, u32 id)
170 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
171 apic_write(APIC_ICR, low);
174 u64 xapic_icr_read(void)
178 icr2 = apic_read(APIC_ICR2);
179 icr1 = apic_read(APIC_ICR);
181 return icr1 | ((u64)icr2 << 32);
184 static struct apic_ops xapic_ops = {
185 .read = native_apic_mem_read,
186 .write = native_apic_mem_write,
187 .icr_read = xapic_icr_read,
188 .icr_write = xapic_icr_write,
189 .wait_icr_idle = xapic_wait_icr_idle,
190 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
193 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
194 EXPORT_SYMBOL_GPL(apic_ops);
196 static void x2apic_wait_icr_idle(void)
198 /* no need to wait for icr idle in x2apic */
202 static u32 safe_x2apic_wait_icr_idle(void)
204 /* no need to wait for icr idle in x2apic */
208 void x2apic_icr_write(u32 low, u32 id)
210 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
213 u64 x2apic_icr_read(void)
217 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
221 static struct apic_ops x2apic_ops = {
222 .read = native_apic_msr_read,
223 .write = native_apic_msr_write,
224 .icr_read = x2apic_icr_read,
225 .icr_write = x2apic_icr_write,
226 .wait_icr_idle = x2apic_wait_icr_idle,
227 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
231 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
233 void __cpuinit enable_NMI_through_LVT0(void)
237 /* unmask and set to NMI */
240 /* Level triggered for 82489DX (32bit mode) */
241 if (!lapic_is_integrated())
242 v |= APIC_LVT_LEVEL_TRIGGER;
244 apic_write(APIC_LVT0, v);
249 * get_physical_broadcast - Get number of physical broadcast IDs
251 int get_physical_broadcast(void)
253 return modern_apic() ? 0xff : 0xf;
258 * lapic_get_maxlvt - get the maximum number of local vector table entries
260 int lapic_get_maxlvt(void)
264 v = apic_read(APIC_LVR);
266 * - we always have APIC integrated on 64bit mode
267 * - 82489DXs do not report # of LVT entries
269 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
278 #define APIC_DIVISOR 1
280 #define APIC_DIVISOR 16
284 * This function sets up the local APIC timer, with a timeout of
285 * 'clocks' APIC bus clock. During calibration we actually call
286 * this function twice on the boot CPU, once with a bogus timeout
287 * value, second time for real. The other (noncalibrating) CPUs
288 * call this function only once, with the real, calibrated value.
290 * We do reads before writes even if unnecessary, to get around the
291 * P5 APIC double write bug.
293 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
295 unsigned int lvtt_value, tmp_value;
297 lvtt_value = LOCAL_TIMER_VECTOR;
299 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
300 if (!lapic_is_integrated())
301 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
304 lvtt_value |= APIC_LVT_MASKED;
306 apic_write(APIC_LVTT, lvtt_value);
311 tmp_value = apic_read(APIC_TDCR);
312 apic_write(APIC_TDCR,
313 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
317 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
321 * Setup extended LVT, AMD specific (K8, family 10h)
323 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
324 * MCE interrupts are supported. Thus MCE offset must be set to 0.
326 * If mask=1, the LVT entry does not generate interrupts while mask=0
327 * enables the vector. See also the BKDGs.
330 #define APIC_EILVT_LVTOFF_MCE 0
331 #define APIC_EILVT_LVTOFF_IBS 1
333 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
335 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
336 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
341 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
343 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
344 return APIC_EILVT_LVTOFF_MCE;
347 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
349 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
350 return APIC_EILVT_LVTOFF_IBS;
352 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
355 * Program the next event, relative to now
357 static int lapic_next_event(unsigned long delta,
358 struct clock_event_device *evt)
360 apic_write(APIC_TMICT, delta);
365 * Setup the lapic timer in periodic or oneshot mode
367 static void lapic_timer_setup(enum clock_event_mode mode,
368 struct clock_event_device *evt)
373 /* Lapic used as dummy for broadcast ? */
374 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
377 local_irq_save(flags);
380 case CLOCK_EVT_MODE_PERIODIC:
381 case CLOCK_EVT_MODE_ONESHOT:
382 __setup_APIC_LVTT(calibration_result,
383 mode != CLOCK_EVT_MODE_PERIODIC, 1);
385 case CLOCK_EVT_MODE_UNUSED:
386 case CLOCK_EVT_MODE_SHUTDOWN:
387 v = apic_read(APIC_LVTT);
388 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
389 apic_write(APIC_LVTT, v);
391 case CLOCK_EVT_MODE_RESUME:
392 /* Nothing to do here */
396 local_irq_restore(flags);
400 * Local APIC timer broadcast function
402 static void lapic_timer_broadcast(cpumask_t mask)
405 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
410 * Setup the local APIC timer for this CPU. Copy the initilized values
411 * of the boot CPU and register the clock event in the framework.
413 static void __cpuinit setup_APIC_timer(void)
415 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
417 memcpy(levt, &lapic_clockevent, sizeof(*levt));
418 levt->cpumask = cpumask_of_cpu(smp_processor_id());
420 clockevents_register_device(levt);
424 * In this function we calibrate APIC bus clocks to the external
425 * timer. Unfortunately we cannot use jiffies and the timer irq
426 * to calibrate, since some later bootup code depends on getting
427 * the first irq? Ugh.
429 * We want to do the calibration only once since we
430 * want to have local timer irqs syncron. CPUs connected
431 * by the same APIC bus have the very same bus frequency.
432 * And we want to have irqs off anyways, no accidental
436 #define TICK_COUNT 100000000
438 static int __init calibrate_APIC_clock(void)
440 unsigned apic, apic_start;
441 unsigned long tsc, tsc_start;
447 * Put whatever arbitrary (but long enough) timeout
448 * value into the APIC clock, we just want to get the
449 * counter running for calibration.
451 * No interrupt enable !
453 __setup_APIC_LVTT(250000000, 0, 0);
455 apic_start = apic_read(APIC_TMCCT);
456 #ifdef CONFIG_X86_PM_TIMER
457 if (apic_calibrate_pmtmr && pmtmr_ioport) {
458 pmtimer_wait(5000); /* 5ms wait */
459 apic = apic_read(APIC_TMCCT);
460 result = (apic_start - apic) * 1000L / 5;
467 apic = apic_read(APIC_TMCCT);
469 } while ((tsc - tsc_start) < TICK_COUNT &&
470 (apic_start - apic) < TICK_COUNT);
472 result = (apic_start - apic) * 1000L * tsc_khz /
478 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
480 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
481 result / 1000 / 1000, result / 1000 % 1000);
483 /* Calculate the scaled math multiplication factor */
484 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
485 lapic_clockevent.shift);
486 lapic_clockevent.max_delta_ns =
487 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
488 lapic_clockevent.min_delta_ns =
489 clockevent_delta2ns(0xF, &lapic_clockevent);
491 calibration_result = (result * APIC_DIVISOR) / HZ;
494 * Do a sanity check on the APIC calibration result
496 if (calibration_result < (1000000 / HZ)) {
498 "APIC frequency too slow, disabling apic timer\n");
506 * Setup the boot APIC
508 * Calibrate and verify the result.
510 void __init setup_boot_APIC_clock(void)
513 * The local apic timer can be disabled via the kernel
514 * commandline or from the CPU detection code. Register the lapic
515 * timer as a dummy clock event source on SMP systems, so the
516 * broadcast mechanism is used. On UP systems simply ignore it.
518 if (disable_apic_timer) {
519 printk(KERN_INFO "Disabling APIC timer\n");
520 /* No broadcast on UP ! */
521 if (num_possible_cpus() > 1) {
522 lapic_clockevent.mult = 1;
528 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
529 "calibrating APIC timer ...\n");
531 if (calibrate_APIC_clock()) {
532 /* No broadcast on UP ! */
533 if (num_possible_cpus() > 1)
539 * If nmi_watchdog is set to IO_APIC, we need the
540 * PIT/HPET going. Otherwise register lapic as a dummy
543 if (nmi_watchdog != NMI_IO_APIC)
544 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
546 printk(KERN_WARNING "APIC timer registered as dummy,"
547 " due to nmi_watchdog=%d!\n", nmi_watchdog);
549 /* Setup the lapic or request the broadcast */
553 void __cpuinit setup_secondary_APIC_clock(void)
559 * The guts of the apic timer interrupt
561 static void local_apic_timer_interrupt(void)
563 int cpu = smp_processor_id();
564 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
567 * Normally we should not be here till LAPIC has been initialized but
568 * in some cases like kdump, its possible that there is a pending LAPIC
569 * timer interrupt from previous kernel's context and is delivered in
570 * new kernel the moment interrupts are enabled.
572 * Interrupts are enabled early and LAPIC is setup much later, hence
573 * its possible that when we get here evt->event_handler is NULL.
574 * Check for event_handler being NULL and discard the interrupt as
577 if (!evt->event_handler) {
579 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
581 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
586 * the NMI deadlock-detector uses this.
589 add_pda(apic_timer_irqs, 1);
591 per_cpu(irq_stat, cpu).apic_timer_irqs++;
594 evt->event_handler(evt);
598 * Local APIC timer interrupt. This is the most natural way for doing
599 * local interrupts, but local timer interrupts can be emulated by
600 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
602 * [ if a single-CPU system runs an SMP kernel then we call the local
603 * interrupt as well. Thus we cannot inline the local irq ... ]
605 void smp_apic_timer_interrupt(struct pt_regs *regs)
607 struct pt_regs *old_regs = set_irq_regs(regs);
610 * NOTE! We'd better ACK the irq immediately,
611 * because timer handling can be slow.
615 * update_process_times() expects us to have done irq_enter().
616 * Besides, if we don't timer interrupts ignore the global
617 * interrupt lock, which is the WrongThing (tm) to do.
621 local_apic_timer_interrupt();
624 set_irq_regs(old_regs);
627 int setup_profiling_timer(unsigned int multiplier)
634 * Local APIC start and shutdown
638 * clear_local_APIC - shutdown the local APIC
640 * This is called, when a CPU is disabled and before rebooting, so the state of
641 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
642 * leftovers during boot.
644 void clear_local_APIC(void)
649 /* APIC hasn't been mapped yet */
653 maxlvt = lapic_get_maxlvt();
655 * Masking an LVT entry can trigger a local APIC error
656 * if the vector is zero. Mask LVTERR first to prevent this.
659 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
660 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
663 * Careful: we have to set masks only first to deassert
664 * any level-triggered sources.
666 v = apic_read(APIC_LVTT);
667 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
668 v = apic_read(APIC_LVT0);
669 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
670 v = apic_read(APIC_LVT1);
671 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
673 v = apic_read(APIC_LVTPC);
674 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
677 /* lets not touch this if we didn't frob it */
678 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
680 v = apic_read(APIC_LVTTHMR);
681 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
685 * Clean APIC state for other OSs:
687 apic_write(APIC_LVTT, APIC_LVT_MASKED);
688 apic_write(APIC_LVT0, APIC_LVT_MASKED);
689 apic_write(APIC_LVT1, APIC_LVT_MASKED);
691 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
693 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
695 /* Integrated APIC (!82489DX) ? */
696 if (lapic_is_integrated()) {
698 /* Clear ESR due to Pentium errata 3AP and 11AP */
699 apic_write(APIC_ESR, 0);
705 * disable_local_APIC - clear and disable the local APIC
707 void disable_local_APIC(void)
714 * Disable APIC (implies clearing of registers
717 value = apic_read(APIC_SPIV);
718 value &= ~APIC_SPIV_APIC_ENABLED;
719 apic_write(APIC_SPIV, value);
723 * When LAPIC was disabled by the BIOS and enabled by the kernel,
724 * restore the disabled state.
726 if (enabled_via_apicbase) {
729 rdmsr(MSR_IA32_APICBASE, l, h);
730 l &= ~MSR_IA32_APICBASE_ENABLE;
731 wrmsr(MSR_IA32_APICBASE, l, h);
737 * If Linux enabled the LAPIC against the BIOS default disable it down before
738 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
739 * not power-off. Additionally clear all LVT entries before disable_local_APIC
740 * for the case where Linux didn't enable the LAPIC.
742 void lapic_shutdown(void)
749 local_irq_save(flags);
752 if (!enabled_via_apicbase)
756 disable_local_APIC();
759 local_irq_restore(flags);
763 * This is to verify that we're looking at a real local APIC.
764 * Check these against your board if the CPUs aren't getting
765 * started for no apparent reason.
767 int __init verify_local_APIC(void)
769 unsigned int reg0, reg1;
772 * The version register is read-only in a real APIC.
774 reg0 = apic_read(APIC_LVR);
775 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
776 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
777 reg1 = apic_read(APIC_LVR);
778 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
781 * The two version reads above should print the same
782 * numbers. If the second one is different, then we
783 * poke at a non-APIC.
789 * Check if the version looks reasonably.
791 reg1 = GET_APIC_VERSION(reg0);
792 if (reg1 == 0x00 || reg1 == 0xff)
794 reg1 = lapic_get_maxlvt();
795 if (reg1 < 0x02 || reg1 == 0xff)
799 * The ID register is read/write in a real APIC.
801 reg0 = apic_read(APIC_ID);
802 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
803 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
804 reg1 = apic_read(APIC_ID);
805 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
806 apic_write(APIC_ID, reg0);
807 if (reg1 != (reg0 ^ APIC_ID_MASK))
811 * The next two are just to see if we have sane values.
812 * They're only really relevant if we're in Virtual Wire
813 * compatibility mode, but most boxes are anymore.
815 reg0 = apic_read(APIC_LVT0);
816 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
817 reg1 = apic_read(APIC_LVT1);
818 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
824 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
826 void __init sync_Arb_IDs(void)
829 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
832 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
838 apic_wait_icr_idle();
840 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
841 apic_write(APIC_ICR, APIC_DEST_ALLINC |
842 APIC_INT_LEVELTRIG | APIC_DM_INIT);
846 * An initial setup of the virtual wire mode.
848 void __init init_bsp_APIC(void)
853 * Don't do the setup now if we have a SMP BIOS as the
854 * through-I/O-APIC virtual wire mode might be active.
856 if (smp_found_config || !cpu_has_apic)
860 * Do not trust the local APIC being empty at bootup.
867 value = apic_read(APIC_SPIV);
868 value &= ~APIC_VECTOR_MASK;
869 value |= APIC_SPIV_APIC_ENABLED;
872 /* This bit is reserved on P4/Xeon and should be cleared */
873 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
874 (boot_cpu_data.x86 == 15))
875 value &= ~APIC_SPIV_FOCUS_DISABLED;
878 value |= APIC_SPIV_FOCUS_DISABLED;
879 value |= SPURIOUS_APIC_VECTOR;
880 apic_write(APIC_SPIV, value);
883 * Set up the virtual wire mode.
885 apic_write(APIC_LVT0, APIC_DM_EXTINT);
887 if (!lapic_is_integrated()) /* 82489DX */
888 value |= APIC_LVT_LEVEL_TRIGGER;
889 apic_write(APIC_LVT1, value);
892 static void __cpuinit lapic_setup_esr(void)
894 unsigned long oldvalue, value, maxlvt;
895 if (lapic_is_integrated() && !esr_disable) {
898 * Something untraceable is creating bad interrupts on
899 * secondary quads ... for the moment, just leave the
900 * ESR disabled - we can't do anything useful with the
901 * errors anyway - mbligh
903 printk(KERN_INFO "Leaving ESR disabled.\n");
907 maxlvt = lapic_get_maxlvt();
908 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
909 apic_write(APIC_ESR, 0);
910 oldvalue = apic_read(APIC_ESR);
912 /* enables sending errors */
913 value = ERROR_APIC_VECTOR;
914 apic_write(APIC_LVTERR, value);
916 * spec says clear errors after enabling vector.
919 apic_write(APIC_ESR, 0);
920 value = apic_read(APIC_ESR);
921 if (value != oldvalue)
922 apic_printk(APIC_VERBOSE, "ESR value before enabling "
923 "vector: 0x%08lx after: 0x%08lx\n",
926 printk(KERN_INFO "No ESR for 82489DX.\n");
932 * setup_local_APIC - setup the local APIC
934 void __cpuinit setup_local_APIC(void)
940 value = apic_read(APIC_LVR);
942 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
945 * Double-check whether this APIC is really registered.
946 * This is meaningless in clustered apic mode, so we skip it.
948 if (!apic_id_registered())
952 * Intel recommends to set DFR, LDR and TPR before enabling
953 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
954 * document number 292116). So here it goes...
959 * Set Task Priority to 'accept all'. We never change this
962 value = apic_read(APIC_TASKPRI);
963 value &= ~APIC_TPRI_MASK;
964 apic_write(APIC_TASKPRI, value);
967 * After a crash, we no longer service the interrupts and a pending
968 * interrupt from previous kernel might still have ISR bit set.
970 * Most probably by now CPU has serviced that pending interrupt and
971 * it might not have done the ack_APIC_irq() because it thought,
972 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
973 * does not clear the ISR bit and cpu thinks it has already serivced
974 * the interrupt. Hence a vector might get locked. It was noticed
975 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
977 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
978 value = apic_read(APIC_ISR + i*0x10);
979 for (j = 31; j >= 0; j--) {
986 * Now that we are all set up, enable the APIC
988 value = apic_read(APIC_SPIV);
989 value &= ~APIC_VECTOR_MASK;
993 value |= APIC_SPIV_APIC_ENABLED;
995 /* We always use processor focus */
998 * Set spurious IRQ vector
1000 value |= SPURIOUS_APIC_VECTOR;
1001 apic_write(APIC_SPIV, value);
1004 * Set up LVT0, LVT1:
1006 * set up through-local-APIC on the BP's LINT0. This is not
1007 * strictly necessary in pure symmetric-IO mode, but sometimes
1008 * we delegate interrupts to the 8259A.
1011 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1013 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1014 if (!smp_processor_id() && !value) {
1015 value = APIC_DM_EXTINT;
1016 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1017 smp_processor_id());
1019 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1020 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1021 smp_processor_id());
1023 apic_write(APIC_LVT0, value);
1026 * only the BP should see the LINT1 NMI signal, obviously.
1028 if (!smp_processor_id())
1029 value = APIC_DM_NMI;
1031 value = APIC_DM_NMI | APIC_LVT_MASKED;
1032 apic_write(APIC_LVT1, value);
1036 void __cpuinit end_local_APIC_setup(void)
1040 #ifdef CONFIG_X86_32
1043 /* Disable the local apic timer */
1044 value = apic_read(APIC_LVTT);
1045 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1046 apic_write(APIC_LVTT, value);
1050 setup_apic_nmi_watchdog(NULL);
1054 void check_x2apic(void)
1058 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1060 if (msr & X2APIC_ENABLE) {
1061 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1062 x2apic_preenabled = x2apic = 1;
1063 apic_ops = &x2apic_ops;
1067 void enable_x2apic(void)
1071 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1072 if (!(msr & X2APIC_ENABLE)) {
1073 printk("Enabling x2apic\n");
1074 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1078 void enable_IR_x2apic(void)
1080 #ifdef CONFIG_INTR_REMAP
1082 unsigned long flags;
1084 if (!cpu_has_x2apic)
1087 if (!x2apic_preenabled && disable_x2apic) {
1089 "Skipped enabling x2apic and Interrupt-remapping "
1090 "because of nox2apic\n");
1094 if (x2apic_preenabled && disable_x2apic)
1095 panic("Bios already enabled x2apic, can't enforce nox2apic");
1097 if (!x2apic_preenabled && skip_ioapic_setup) {
1099 "Skipped enabling x2apic and Interrupt-remapping "
1100 "because of skipping io-apic setup\n");
1104 ret = dmar_table_init();
1107 "dmar_table_init() failed with %d:\n", ret);
1109 if (x2apic_preenabled)
1110 panic("x2apic enabled by bios. But IR enabling failed");
1113 "Not enabling x2apic,Intr-remapping\n");
1117 local_irq_save(flags);
1119 save_mask_IO_APIC_setup();
1121 ret = enable_intr_remapping(1);
1123 if (ret && x2apic_preenabled) {
1124 local_irq_restore(flags);
1125 panic("x2apic enabled by bios. But IR enabling failed");
1133 apic_ops = &x2apic_ops;
1139 * IR enabling failed
1141 restore_IO_APIC_setup();
1143 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1146 local_irq_restore(flags);
1149 if (!x2apic_preenabled)
1151 "Enabled x2apic and interrupt-remapping\n");
1154 "Enabled Interrupt-remapping\n");
1157 "Failed to enable Interrupt-remapping and x2apic\n");
1159 if (!cpu_has_x2apic)
1162 if (x2apic_preenabled)
1163 panic("x2apic enabled prior OS handover,"
1164 " enable CONFIG_INTR_REMAP");
1166 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1174 * Detect and enable local APICs on non-SMP boards.
1175 * Original code written by Keir Fraser.
1176 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1177 * not correctly set up (usually the APIC timer won't work etc.)
1179 static int __init detect_init_APIC(void)
1181 if (!cpu_has_apic) {
1182 printk(KERN_INFO "No local APIC present\n");
1186 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1187 boot_cpu_physical_apicid = 0;
1191 void __init early_init_lapic_mapping(void)
1193 unsigned long phys_addr;
1196 * If no local APIC can be found then go out
1197 * : it means there is no mpatable and MADT
1199 if (!smp_found_config)
1202 phys_addr = mp_lapic_addr;
1204 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1205 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1206 APIC_BASE, phys_addr);
1209 * Fetch the APIC ID of the BSP in case we have a
1210 * default configuration (or the MP table is broken).
1212 boot_cpu_physical_apicid = read_apic_id();
1216 * init_apic_mappings - initialize APIC mappings
1218 void __init init_apic_mappings(void)
1221 boot_cpu_physical_apicid = read_apic_id();
1226 * If no local APIC can be found then set up a fake all
1227 * zeroes page to simulate the local APIC and another
1228 * one for the IO-APIC.
1230 if (!smp_found_config && detect_init_APIC()) {
1231 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1232 apic_phys = __pa(apic_phys);
1234 apic_phys = mp_lapic_addr;
1236 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1237 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1238 APIC_BASE, apic_phys);
1241 * Fetch the APIC ID of the BSP in case we have a
1242 * default configuration (or the MP table is broken).
1244 boot_cpu_physical_apicid = read_apic_id();
1248 * This initializes the IO-APIC and APIC hardware if this is
1251 int apic_version[MAX_APICS];
1253 int __init APIC_init_uniprocessor(void)
1256 printk(KERN_INFO "Apic disabled\n");
1259 if (!cpu_has_apic) {
1261 printk(KERN_INFO "Apic disabled by BIOS\n");
1266 setup_apic_routing();
1268 verify_local_APIC();
1272 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1273 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1278 * Now enable IO-APICs, actually call clear_IO_APIC
1279 * We need clear_IO_APIC before enabling vector on BP
1281 if (!skip_ioapic_setup && nr_ioapics)
1284 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1285 localise_nmi_watchdog();
1286 end_local_APIC_setup();
1288 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1292 setup_boot_APIC_clock();
1293 check_nmi_watchdog();
1298 * Local APIC interrupts
1302 * This interrupt should _never_ happen with our APIC/SMP architecture
1304 asmlinkage void smp_spurious_interrupt(void)
1310 * Check if this really is a spurious interrupt and ACK it
1311 * if it is a vectored one. Just in case...
1312 * Spurious interrupts should not be ACKed.
1314 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1315 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1318 add_pda(irq_spurious_count, 1);
1323 * This interrupt should never happen with our APIC/SMP architecture
1325 asmlinkage void smp_error_interrupt(void)
1331 /* First tickle the hardware, only then report what went on. -- REW */
1332 v = apic_read(APIC_ESR);
1333 apic_write(APIC_ESR, 0);
1334 v1 = apic_read(APIC_ESR);
1336 atomic_inc(&irq_err_count);
1338 /* Here is what the APIC error bits mean:
1341 2: Send accept error
1342 3: Receive accept error
1344 5: Send illegal vector
1345 6: Received illegal vector
1346 7: Illegal register address
1348 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1349 smp_processor_id(), v , v1);
1354 * connect_bsp_APIC - attach the APIC to the interrupt system
1356 void __init connect_bsp_APIC(void)
1358 #ifdef CONFIG_X86_32
1361 * Do not trust the local APIC being empty at bootup.
1365 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1366 * local APIC to INT and NMI lines.
1368 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1369 "enabling APIC mode.\n");
1378 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1379 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1381 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1384 void disconnect_bsp_APIC(int virt_wire_setup)
1388 #ifdef CONFIG_X86_32
1391 * Put the board back into PIC mode (has an effect only on
1392 * certain older boards). Note that APIC interrupts, including
1393 * IPIs, won't work beyond this point! The only exception are
1396 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1397 "entering PIC mode.\n");
1404 /* Go back to Virtual Wire compatibility mode */
1406 /* For the spurious interrupt use vector F, and enable it */
1407 value = apic_read(APIC_SPIV);
1408 value &= ~APIC_VECTOR_MASK;
1409 value |= APIC_SPIV_APIC_ENABLED;
1411 apic_write(APIC_SPIV, value);
1413 if (!virt_wire_setup) {
1415 * For LVT0 make it edge triggered, active high,
1416 * external and enabled
1418 value = apic_read(APIC_LVT0);
1419 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1420 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1421 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1422 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1423 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1424 apic_write(APIC_LVT0, value);
1427 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1431 * For LVT1 make it edge triggered, active high,
1434 value = apic_read(APIC_LVT1);
1435 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1436 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1437 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1438 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1439 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1440 apic_write(APIC_LVT1, value);
1443 void __cpuinit generic_processor_info(int apicid, int version)
1451 if (version == 0x0) {
1452 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1453 "fixing up to 0x10. (tell your hw vendor)\n",
1457 apic_version[apicid] = version;
1459 if (num_processors >= NR_CPUS) {
1460 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1461 " Processor ignored.\n", NR_CPUS);
1466 cpus_complement(tmp_map, cpu_present_map);
1467 cpu = first_cpu(tmp_map);
1469 physid_set(apicid, phys_cpu_present_map);
1470 if (apicid == boot_cpu_physical_apicid) {
1472 * x86_bios_cpu_apicid is required to have processors listed
1473 * in same order as logical cpu numbers. Hence the first
1474 * entry is BSP, and so on.
1478 if (apicid > max_physical_apicid)
1479 max_physical_apicid = apicid;
1481 #ifdef CONFIG_X86_32
1483 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1484 * but we need to work other dependencies like SMP_SUSPEND etc
1485 * before this can be done without some confusion.
1486 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1487 * - Ashok Raj <ashok.raj@intel.com>
1489 if (max_physical_apicid >= 8) {
1490 switch (boot_cpu_data.x86_vendor) {
1491 case X86_VENDOR_INTEL:
1492 if (!APIC_XAPIC(version)) {
1496 /* If P4 and above fall through */
1497 case X86_VENDOR_AMD:
1503 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1504 /* are we being called early in kernel startup? */
1505 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1506 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1507 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1509 cpu_to_apicid[cpu] = apicid;
1510 bios_cpu_apicid[cpu] = apicid;
1512 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1513 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1517 cpu_set(cpu, cpu_possible_map);
1518 cpu_set(cpu, cpu_present_map);
1521 int hard_smp_processor_id(void)
1523 return read_apic_id();
1533 * 'active' is true if the local APIC was enabled by us and
1534 * not the BIOS; this signifies that we are also responsible
1535 * for disabling it before entering apm/acpi suspend
1538 /* r/w apic fields */
1539 unsigned int apic_id;
1540 unsigned int apic_taskpri;
1541 unsigned int apic_ldr;
1542 unsigned int apic_dfr;
1543 unsigned int apic_spiv;
1544 unsigned int apic_lvtt;
1545 unsigned int apic_lvtpc;
1546 unsigned int apic_lvt0;
1547 unsigned int apic_lvt1;
1548 unsigned int apic_lvterr;
1549 unsigned int apic_tmict;
1550 unsigned int apic_tdcr;
1551 unsigned int apic_thmr;
1554 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1556 unsigned long flags;
1559 if (!apic_pm_state.active)
1562 maxlvt = lapic_get_maxlvt();
1564 apic_pm_state.apic_id = apic_read(APIC_ID);
1565 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1566 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1567 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1568 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1569 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1571 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1572 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1573 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1574 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1575 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1576 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1577 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1579 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1582 local_irq_save(flags);
1583 disable_local_APIC();
1584 local_irq_restore(flags);
1588 static int lapic_resume(struct sys_device *dev)
1591 unsigned long flags;
1594 if (!apic_pm_state.active)
1597 maxlvt = lapic_get_maxlvt();
1599 local_irq_save(flags);
1601 #ifdef CONFIG_X86_64
1608 * Make sure the APICBASE points to the right address
1610 * FIXME! This will be wrong if we ever support suspend on
1611 * SMP! We'll need to do this as part of the CPU restore!
1613 rdmsr(MSR_IA32_APICBASE, l, h);
1614 l &= ~MSR_IA32_APICBASE_BASE;
1615 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1616 wrmsr(MSR_IA32_APICBASE, l, h);
1619 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1620 apic_write(APIC_ID, apic_pm_state.apic_id);
1621 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1622 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1623 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1624 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1625 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1626 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1627 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1629 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1632 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1633 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1634 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1635 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1636 apic_write(APIC_ESR, 0);
1637 apic_read(APIC_ESR);
1638 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1639 apic_write(APIC_ESR, 0);
1640 apic_read(APIC_ESR);
1642 local_irq_restore(flags);
1648 * This device has no shutdown method - fully functioning local APICs
1649 * are needed on every CPU up until machine_halt/restart/poweroff.
1652 static struct sysdev_class lapic_sysclass = {
1654 .resume = lapic_resume,
1655 .suspend = lapic_suspend,
1658 static struct sys_device device_lapic = {
1660 .cls = &lapic_sysclass,
1663 static void __cpuinit apic_pm_activate(void)
1665 apic_pm_state.active = 1;
1668 static int __init init_lapic_sysfs(void)
1674 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1676 error = sysdev_class_register(&lapic_sysclass);
1678 error = sysdev_register(&device_lapic);
1681 device_initcall(init_lapic_sysfs);
1683 #else /* CONFIG_PM */
1685 static void apic_pm_activate(void) { }
1687 #endif /* CONFIG_PM */
1690 * apic_is_clustered_box() -- Check if we can expect good TSC
1692 * Thus far, the major user of this is IBM's Summit2 series:
1694 * Clustered boxes may have unsynced TSC problems if they are
1695 * multi-chassis. Use available data to take a good guess.
1696 * If in doubt, go HPET.
1698 __cpuinit int apic_is_clustered_box(void)
1700 int i, clusters, zeros;
1702 u16 *bios_cpu_apicid;
1703 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1706 * there is not this kind of box with AMD CPU yet.
1707 * Some AMD box with quadcore cpu and 8 sockets apicid
1708 * will be [4, 0x23] or [8, 0x27] could be thought to
1709 * vsmp box still need checking...
1711 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1714 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1715 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1717 for (i = 0; i < NR_CPUS; i++) {
1718 /* are we being called early in kernel startup? */
1719 if (bios_cpu_apicid) {
1720 id = bios_cpu_apicid[i];
1722 else if (i < nr_cpu_ids) {
1724 id = per_cpu(x86_bios_cpu_apicid, i);
1731 if (id != BAD_APICID)
1732 __set_bit(APIC_CLUSTERID(id), clustermap);
1735 /* Problem: Partially populated chassis may not have CPUs in some of
1736 * the APIC clusters they have been allocated. Only present CPUs have
1737 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1738 * Since clusters are allocated sequentially, count zeros only if
1739 * they are bounded by ones.
1743 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1744 if (test_bit(i, clustermap)) {
1745 clusters += 1 + zeros;
1751 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1752 * not guaranteed to be synced between boards
1754 if (is_vsmp_box() && clusters > 1)
1758 * If clusters > 2, then should be multi-chassis.
1759 * May have to revisit this when multi-core + hyperthreaded CPUs come
1760 * out, but AFAIK this will work even for them.
1762 return (clusters > 2);
1765 static __init int setup_nox2apic(char *str)
1768 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1771 early_param("nox2apic", setup_nox2apic);
1775 * APIC command line parameters
1777 static int __init setup_disableapic(char *arg)
1780 setup_clear_cpu_cap(X86_FEATURE_APIC);
1783 early_param("disableapic", setup_disableapic);
1785 /* same as disableapic, for compatibility */
1786 static int __init setup_nolapic(char *arg)
1788 return setup_disableapic(arg);
1790 early_param("nolapic", setup_nolapic);
1792 static int __init parse_lapic_timer_c2_ok(char *arg)
1794 local_apic_timer_c2_ok = 1;
1797 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1799 static int __init parse_disable_apic_timer(char *arg)
1801 disable_apic_timer = 1;
1804 early_param("noapictimer", parse_disable_apic_timer);
1806 static int __init parse_nolapic_timer(char *arg)
1808 disable_apic_timer = 1;
1811 early_param("nolapic_timer", parse_nolapic_timer);
1813 #ifdef CONFIG_X86_64
1814 static __init int setup_apicpmtimer(char *s)
1816 apic_calibrate_pmtmr = 1;
1820 __setup("apicpmtimer", setup_apicpmtimer);
1823 static int __init apic_set_verbosity(char *arg)
1826 #ifdef CONFIG_X86_64
1827 skip_ioapic_setup = 0;
1833 if (strcmp("debug", arg) == 0)
1834 apic_verbosity = APIC_DEBUG;
1835 else if (strcmp("verbose", arg) == 0)
1836 apic_verbosity = APIC_VERBOSE;
1838 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1839 " use apic=verbose or apic=debug\n", arg);
1845 early_param("apic", apic_set_verbosity);
1847 static int __init lapic_insert_resource(void)
1852 /* Put local APIC into the resource map. */
1853 lapic_resource.start = apic_phys;
1854 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1855 insert_resource(&iomem_resource, &lapic_resource);
1861 * need call insert after e820_reserve_resources()
1862 * that is using request_resource
1864 late_initcall(lapic_insert_resource);