2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
52 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
53 # error SPURIOUS_APIC_VECTOR definition error
58 * Knob to control our willingness to enable the local APIC.
62 static int force_enable_local_apic;
64 * APIC command line parameters
66 static int __init parse_lapic(char *arg)
68 force_enable_local_apic = 1;
71 early_param("lapic", parse_lapic);
75 static int apic_calibrate_pmtmr __initdata;
76 static __init int setup_apicpmtimer(char *s)
78 apic_calibrate_pmtmr = 1;
82 __setup("apicpmtimer", setup_apicpmtimer);
87 /* x2apic enabled before OS handover */
88 int x2apic_preenabled;
90 unsigned long mp_lapic_addr;
92 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
93 static int disable_apic_timer __cpuinitdata;
94 /* Local APIC timer works in C2 */
95 int local_apic_timer_c2_ok;
96 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
98 int first_system_vector = 0xfe;
100 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
103 * Debug level, exported for io_apic.c
105 unsigned int apic_verbosity;
109 /* Have we found an MP table */
110 int smp_found_config;
112 static struct resource lapic_resource = {
113 .name = "Local APIC",
114 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
117 static unsigned int calibration_result;
119 static int lapic_next_event(unsigned long delta,
120 struct clock_event_device *evt);
121 static void lapic_timer_setup(enum clock_event_mode mode,
122 struct clock_event_device *evt);
123 static void lapic_timer_broadcast(cpumask_t mask);
124 static void apic_pm_activate(void);
127 * The local apic timer can be used for any function which is CPU local.
129 static struct clock_event_device lapic_clockevent = {
131 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
132 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
134 .set_mode = lapic_timer_setup,
135 .set_next_event = lapic_next_event,
136 .broadcast = lapic_timer_broadcast,
140 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
142 static unsigned long apic_phys;
145 * Get the LAPIC version
147 static inline int lapic_get_version(void)
149 return GET_APIC_VERSION(apic_read(APIC_LVR));
153 * Check, if the APIC is integrated or a separate chip
155 static inline int lapic_is_integrated(void)
160 return APIC_INTEGRATED(lapic_get_version());
165 * Check, whether this is a modern or a first generation APIC
167 static int modern_apic(void)
169 /* AMD systems use old APIC versions, so check the CPU */
170 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
171 boot_cpu_data.x86 >= 0xf)
173 return lapic_get_version() >= 0x14;
177 * Paravirt kernels also might be using these below ops. So we still
178 * use generic apic_read()/apic_write(), which might be pointing to different
179 * ops in PARAVIRT case.
181 void xapic_wait_icr_idle(void)
183 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
187 u32 safe_xapic_wait_icr_idle(void)
194 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
198 } while (timeout++ < 1000);
203 void xapic_icr_write(u32 low, u32 id)
205 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
206 apic_write(APIC_ICR, low);
209 u64 xapic_icr_read(void)
213 icr2 = apic_read(APIC_ICR2);
214 icr1 = apic_read(APIC_ICR);
216 return icr1 | ((u64)icr2 << 32);
219 static struct apic_ops xapic_ops = {
220 .read = native_apic_mem_read,
221 .write = native_apic_mem_write,
222 .icr_read = xapic_icr_read,
223 .icr_write = xapic_icr_write,
224 .wait_icr_idle = xapic_wait_icr_idle,
225 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
228 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
229 EXPORT_SYMBOL_GPL(apic_ops);
231 static void x2apic_wait_icr_idle(void)
233 /* no need to wait for icr idle in x2apic */
237 static u32 safe_x2apic_wait_icr_idle(void)
239 /* no need to wait for icr idle in x2apic */
243 void x2apic_icr_write(u32 low, u32 id)
245 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
248 u64 x2apic_icr_read(void)
252 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
256 static struct apic_ops x2apic_ops = {
257 .read = native_apic_msr_read,
258 .write = native_apic_msr_write,
259 .icr_read = x2apic_icr_read,
260 .icr_write = x2apic_icr_write,
261 .wait_icr_idle = x2apic_wait_icr_idle,
262 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
266 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
268 void __cpuinit enable_NMI_through_LVT0(void)
272 /* unmask and set to NMI */
275 /* Level triggered for 82489DX (32bit mode) */
276 if (!lapic_is_integrated())
277 v |= APIC_LVT_LEVEL_TRIGGER;
279 apic_write(APIC_LVT0, v);
284 * get_physical_broadcast - Get number of physical broadcast IDs
286 int get_physical_broadcast(void)
288 return modern_apic() ? 0xff : 0xf;
293 * lapic_get_maxlvt - get the maximum number of local vector table entries
295 int lapic_get_maxlvt(void)
299 v = apic_read(APIC_LVR);
301 * - we always have APIC integrated on 64bit mode
302 * - 82489DXs do not report # of LVT entries
304 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
313 #define APIC_DIVISOR 1
315 #define APIC_DIVISOR 16
319 * This function sets up the local APIC timer, with a timeout of
320 * 'clocks' APIC bus clock. During calibration we actually call
321 * this function twice on the boot CPU, once with a bogus timeout
322 * value, second time for real. The other (noncalibrating) CPUs
323 * call this function only once, with the real, calibrated value.
325 * We do reads before writes even if unnecessary, to get around the
326 * P5 APIC double write bug.
328 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
330 unsigned int lvtt_value, tmp_value;
332 lvtt_value = LOCAL_TIMER_VECTOR;
334 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
335 if (!lapic_is_integrated())
336 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
339 lvtt_value |= APIC_LVT_MASKED;
341 apic_write(APIC_LVTT, lvtt_value);
346 tmp_value = apic_read(APIC_TDCR);
347 apic_write(APIC_TDCR,
348 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
352 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
356 * Setup extended LVT, AMD specific (K8, family 10h)
358 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
359 * MCE interrupts are supported. Thus MCE offset must be set to 0.
361 * If mask=1, the LVT entry does not generate interrupts while mask=0
362 * enables the vector. See also the BKDGs.
365 #define APIC_EILVT_LVTOFF_MCE 0
366 #define APIC_EILVT_LVTOFF_IBS 1
368 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
370 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
371 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
376 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
378 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
379 return APIC_EILVT_LVTOFF_MCE;
382 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
384 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
385 return APIC_EILVT_LVTOFF_IBS;
387 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
390 * Program the next event, relative to now
392 static int lapic_next_event(unsigned long delta,
393 struct clock_event_device *evt)
395 apic_write(APIC_TMICT, delta);
400 * Setup the lapic timer in periodic or oneshot mode
402 static void lapic_timer_setup(enum clock_event_mode mode,
403 struct clock_event_device *evt)
408 /* Lapic used as dummy for broadcast ? */
409 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
412 local_irq_save(flags);
415 case CLOCK_EVT_MODE_PERIODIC:
416 case CLOCK_EVT_MODE_ONESHOT:
417 __setup_APIC_LVTT(calibration_result,
418 mode != CLOCK_EVT_MODE_PERIODIC, 1);
420 case CLOCK_EVT_MODE_UNUSED:
421 case CLOCK_EVT_MODE_SHUTDOWN:
422 v = apic_read(APIC_LVTT);
423 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
424 apic_write(APIC_LVTT, v);
426 case CLOCK_EVT_MODE_RESUME:
427 /* Nothing to do here */
431 local_irq_restore(flags);
435 * Local APIC timer broadcast function
437 static void lapic_timer_broadcast(cpumask_t mask)
440 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
445 * Setup the local APIC timer for this CPU. Copy the initilized values
446 * of the boot CPU and register the clock event in the framework.
448 static void __cpuinit setup_APIC_timer(void)
450 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
452 memcpy(levt, &lapic_clockevent, sizeof(*levt));
453 levt->cpumask = cpumask_of_cpu(smp_processor_id());
455 clockevents_register_device(levt);
459 * In this function we calibrate APIC bus clocks to the external
460 * timer. Unfortunately we cannot use jiffies and the timer irq
461 * to calibrate, since some later bootup code depends on getting
462 * the first irq? Ugh.
464 * We want to do the calibration only once since we
465 * want to have local timer irqs syncron. CPUs connected
466 * by the same APIC bus have the very same bus frequency.
467 * And we want to have irqs off anyways, no accidental
471 #define TICK_COUNT 100000000
473 static int __init calibrate_APIC_clock(void)
475 unsigned apic, apic_start;
476 unsigned long tsc, tsc_start;
482 * Put whatever arbitrary (but long enough) timeout
483 * value into the APIC clock, we just want to get the
484 * counter running for calibration.
486 * No interrupt enable !
488 __setup_APIC_LVTT(250000000, 0, 0);
490 apic_start = apic_read(APIC_TMCCT);
491 #ifdef CONFIG_X86_PM_TIMER
492 if (apic_calibrate_pmtmr && pmtmr_ioport) {
493 pmtimer_wait(5000); /* 5ms wait */
494 apic = apic_read(APIC_TMCCT);
495 result = (apic_start - apic) * 1000L / 5;
502 apic = apic_read(APIC_TMCCT);
504 } while ((tsc - tsc_start) < TICK_COUNT &&
505 (apic_start - apic) < TICK_COUNT);
507 result = (apic_start - apic) * 1000L * tsc_khz /
513 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
515 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
516 result / 1000 / 1000, result / 1000 % 1000);
518 /* Calculate the scaled math multiplication factor */
519 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
520 lapic_clockevent.shift);
521 lapic_clockevent.max_delta_ns =
522 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
523 lapic_clockevent.min_delta_ns =
524 clockevent_delta2ns(0xF, &lapic_clockevent);
526 calibration_result = (result * APIC_DIVISOR) / HZ;
529 * Do a sanity check on the APIC calibration result
531 if (calibration_result < (1000000 / HZ)) {
533 "APIC frequency too slow, disabling apic timer\n");
541 * Setup the boot APIC
543 * Calibrate and verify the result.
545 void __init setup_boot_APIC_clock(void)
548 * The local apic timer can be disabled via the kernel
549 * commandline or from the CPU detection code. Register the lapic
550 * timer as a dummy clock event source on SMP systems, so the
551 * broadcast mechanism is used. On UP systems simply ignore it.
553 if (disable_apic_timer) {
554 printk(KERN_INFO "Disabling APIC timer\n");
555 /* No broadcast on UP ! */
556 if (num_possible_cpus() > 1) {
557 lapic_clockevent.mult = 1;
563 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
564 "calibrating APIC timer ...\n");
566 if (calibrate_APIC_clock()) {
567 /* No broadcast on UP ! */
568 if (num_possible_cpus() > 1)
574 * If nmi_watchdog is set to IO_APIC, we need the
575 * PIT/HPET going. Otherwise register lapic as a dummy
578 if (nmi_watchdog != NMI_IO_APIC)
579 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
581 printk(KERN_WARNING "APIC timer registered as dummy,"
582 " due to nmi_watchdog=%d!\n", nmi_watchdog);
584 /* Setup the lapic or request the broadcast */
588 void __cpuinit setup_secondary_APIC_clock(void)
594 * The guts of the apic timer interrupt
596 static void local_apic_timer_interrupt(void)
598 int cpu = smp_processor_id();
599 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
602 * Normally we should not be here till LAPIC has been initialized but
603 * in some cases like kdump, its possible that there is a pending LAPIC
604 * timer interrupt from previous kernel's context and is delivered in
605 * new kernel the moment interrupts are enabled.
607 * Interrupts are enabled early and LAPIC is setup much later, hence
608 * its possible that when we get here evt->event_handler is NULL.
609 * Check for event_handler being NULL and discard the interrupt as
612 if (!evt->event_handler) {
614 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
616 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
621 * the NMI deadlock-detector uses this.
624 add_pda(apic_timer_irqs, 1);
626 per_cpu(irq_stat, cpu).apic_timer_irqs++;
629 evt->event_handler(evt);
633 * Local APIC timer interrupt. This is the most natural way for doing
634 * local interrupts, but local timer interrupts can be emulated by
635 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
637 * [ if a single-CPU system runs an SMP kernel then we call the local
638 * interrupt as well. Thus we cannot inline the local irq ... ]
640 void smp_apic_timer_interrupt(struct pt_regs *regs)
642 struct pt_regs *old_regs = set_irq_regs(regs);
645 * NOTE! We'd better ACK the irq immediately,
646 * because timer handling can be slow.
650 * update_process_times() expects us to have done irq_enter().
651 * Besides, if we don't timer interrupts ignore the global
652 * interrupt lock, which is the WrongThing (tm) to do.
658 local_apic_timer_interrupt();
661 set_irq_regs(old_regs);
664 int setup_profiling_timer(unsigned int multiplier)
671 * Local APIC start and shutdown
675 * clear_local_APIC - shutdown the local APIC
677 * This is called, when a CPU is disabled and before rebooting, so the state of
678 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
679 * leftovers during boot.
681 void clear_local_APIC(void)
686 /* APIC hasn't been mapped yet */
690 maxlvt = lapic_get_maxlvt();
692 * Masking an LVT entry can trigger a local APIC error
693 * if the vector is zero. Mask LVTERR first to prevent this.
696 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
697 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
700 * Careful: we have to set masks only first to deassert
701 * any level-triggered sources.
703 v = apic_read(APIC_LVTT);
704 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
705 v = apic_read(APIC_LVT0);
706 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
707 v = apic_read(APIC_LVT1);
708 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
710 v = apic_read(APIC_LVTPC);
711 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
714 /* lets not touch this if we didn't frob it */
715 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
717 v = apic_read(APIC_LVTTHMR);
718 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
722 * Clean APIC state for other OSs:
724 apic_write(APIC_LVTT, APIC_LVT_MASKED);
725 apic_write(APIC_LVT0, APIC_LVT_MASKED);
726 apic_write(APIC_LVT1, APIC_LVT_MASKED);
728 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
730 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
732 /* Integrated APIC (!82489DX) ? */
733 if (lapic_is_integrated()) {
735 /* Clear ESR due to Pentium errata 3AP and 11AP */
736 apic_write(APIC_ESR, 0);
742 * disable_local_APIC - clear and disable the local APIC
744 void disable_local_APIC(void)
751 * Disable APIC (implies clearing of registers
754 value = apic_read(APIC_SPIV);
755 value &= ~APIC_SPIV_APIC_ENABLED;
756 apic_write(APIC_SPIV, value);
760 * When LAPIC was disabled by the BIOS and enabled by the kernel,
761 * restore the disabled state.
763 if (enabled_via_apicbase) {
766 rdmsr(MSR_IA32_APICBASE, l, h);
767 l &= ~MSR_IA32_APICBASE_ENABLE;
768 wrmsr(MSR_IA32_APICBASE, l, h);
774 * If Linux enabled the LAPIC against the BIOS default disable it down before
775 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
776 * not power-off. Additionally clear all LVT entries before disable_local_APIC
777 * for the case where Linux didn't enable the LAPIC.
779 void lapic_shutdown(void)
786 local_irq_save(flags);
789 if (!enabled_via_apicbase)
793 disable_local_APIC();
796 local_irq_restore(flags);
800 * This is to verify that we're looking at a real local APIC.
801 * Check these against your board if the CPUs aren't getting
802 * started for no apparent reason.
804 int __init verify_local_APIC(void)
806 unsigned int reg0, reg1;
809 * The version register is read-only in a real APIC.
811 reg0 = apic_read(APIC_LVR);
812 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
813 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
814 reg1 = apic_read(APIC_LVR);
815 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
818 * The two version reads above should print the same
819 * numbers. If the second one is different, then we
820 * poke at a non-APIC.
826 * Check if the version looks reasonably.
828 reg1 = GET_APIC_VERSION(reg0);
829 if (reg1 == 0x00 || reg1 == 0xff)
831 reg1 = lapic_get_maxlvt();
832 if (reg1 < 0x02 || reg1 == 0xff)
836 * The ID register is read/write in a real APIC.
838 reg0 = apic_read(APIC_ID);
839 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
840 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
841 reg1 = apic_read(APIC_ID);
842 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
843 apic_write(APIC_ID, reg0);
844 if (reg1 != (reg0 ^ APIC_ID_MASK))
848 * The next two are just to see if we have sane values.
849 * They're only really relevant if we're in Virtual Wire
850 * compatibility mode, but most boxes are anymore.
852 reg0 = apic_read(APIC_LVT0);
853 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
854 reg1 = apic_read(APIC_LVT1);
855 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
861 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
863 void __init sync_Arb_IDs(void)
866 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
869 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
875 apic_wait_icr_idle();
877 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
878 apic_write(APIC_ICR, APIC_DEST_ALLINC |
879 APIC_INT_LEVELTRIG | APIC_DM_INIT);
883 * An initial setup of the virtual wire mode.
885 void __init init_bsp_APIC(void)
890 * Don't do the setup now if we have a SMP BIOS as the
891 * through-I/O-APIC virtual wire mode might be active.
893 if (smp_found_config || !cpu_has_apic)
897 * Do not trust the local APIC being empty at bootup.
904 value = apic_read(APIC_SPIV);
905 value &= ~APIC_VECTOR_MASK;
906 value |= APIC_SPIV_APIC_ENABLED;
909 /* This bit is reserved on P4/Xeon and should be cleared */
910 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
911 (boot_cpu_data.x86 == 15))
912 value &= ~APIC_SPIV_FOCUS_DISABLED;
915 value |= APIC_SPIV_FOCUS_DISABLED;
916 value |= SPURIOUS_APIC_VECTOR;
917 apic_write(APIC_SPIV, value);
920 * Set up the virtual wire mode.
922 apic_write(APIC_LVT0, APIC_DM_EXTINT);
924 if (!lapic_is_integrated()) /* 82489DX */
925 value |= APIC_LVT_LEVEL_TRIGGER;
926 apic_write(APIC_LVT1, value);
929 static void __cpuinit lapic_setup_esr(void)
931 unsigned long oldvalue, value, maxlvt;
932 if (lapic_is_integrated() && !esr_disable) {
935 * Something untraceable is creating bad interrupts on
936 * secondary quads ... for the moment, just leave the
937 * ESR disabled - we can't do anything useful with the
938 * errors anyway - mbligh
940 printk(KERN_INFO "Leaving ESR disabled.\n");
944 maxlvt = lapic_get_maxlvt();
945 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
946 apic_write(APIC_ESR, 0);
947 oldvalue = apic_read(APIC_ESR);
949 /* enables sending errors */
950 value = ERROR_APIC_VECTOR;
951 apic_write(APIC_LVTERR, value);
953 * spec says clear errors after enabling vector.
956 apic_write(APIC_ESR, 0);
957 value = apic_read(APIC_ESR);
958 if (value != oldvalue)
959 apic_printk(APIC_VERBOSE, "ESR value before enabling "
960 "vector: 0x%08lx after: 0x%08lx\n",
963 printk(KERN_INFO "No ESR for 82489DX.\n");
969 * setup_local_APIC - setup the local APIC
971 void __cpuinit setup_local_APIC(void)
977 /* Pound the ESR really hard over the head with a big hammer - mbligh */
979 apic_write(APIC_ESR, 0);
980 apic_write(APIC_ESR, 0);
981 apic_write(APIC_ESR, 0);
982 apic_write(APIC_ESR, 0);
989 * Double-check whether this APIC is really registered.
990 * This is meaningless in clustered apic mode, so we skip it.
992 if (!apic_id_registered())
996 * Intel recommends to set DFR, LDR and TPR before enabling
997 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
998 * document number 292116). So here it goes...
1003 * Set Task Priority to 'accept all'. We never change this
1006 value = apic_read(APIC_TASKPRI);
1007 value &= ~APIC_TPRI_MASK;
1008 apic_write(APIC_TASKPRI, value);
1011 * After a crash, we no longer service the interrupts and a pending
1012 * interrupt from previous kernel might still have ISR bit set.
1014 * Most probably by now CPU has serviced that pending interrupt and
1015 * it might not have done the ack_APIC_irq() because it thought,
1016 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1017 * does not clear the ISR bit and cpu thinks it has already serivced
1018 * the interrupt. Hence a vector might get locked. It was noticed
1019 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1021 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1022 value = apic_read(APIC_ISR + i*0x10);
1023 for (j = 31; j >= 0; j--) {
1030 * Now that we are all set up, enable the APIC
1032 value = apic_read(APIC_SPIV);
1033 value &= ~APIC_VECTOR_MASK;
1037 value |= APIC_SPIV_APIC_ENABLED;
1039 #ifdef CONFIG_X86_32
1041 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1042 * certain networking cards. If high frequency interrupts are
1043 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1044 * entry is masked/unmasked at a high rate as well then sooner or
1045 * later IOAPIC line gets 'stuck', no more interrupts are received
1046 * from the device. If focus CPU is disabled then the hang goes
1049 * [ This bug can be reproduced easily with a level-triggered
1050 * PCI Ne2000 networking cards and PII/PIII processors, dual
1054 * Actually disabling the focus CPU check just makes the hang less
1055 * frequent as it makes the interrupt distributon model be more
1056 * like LRU than MRU (the short-term load is more even across CPUs).
1057 * See also the comment in end_level_ioapic_irq(). --macro
1061 * - enable focus processor (bit==0)
1062 * - 64bit mode always use processor focus
1063 * so no need to set it
1065 value &= ~APIC_SPIV_FOCUS_DISABLED;
1069 * Set spurious IRQ vector
1071 value |= SPURIOUS_APIC_VECTOR;
1072 apic_write(APIC_SPIV, value);
1075 * Set up LVT0, LVT1:
1077 * set up through-local-APIC on the BP's LINT0. This is not
1078 * strictly necessary in pure symmetric-IO mode, but sometimes
1079 * we delegate interrupts to the 8259A.
1082 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1084 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1085 if (!smp_processor_id() && (pic_mode || !value)) {
1086 value = APIC_DM_EXTINT;
1087 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1088 smp_processor_id());
1090 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1091 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1092 smp_processor_id());
1094 apic_write(APIC_LVT0, value);
1097 * only the BP should see the LINT1 NMI signal, obviously.
1099 if (!smp_processor_id())
1100 value = APIC_DM_NMI;
1102 value = APIC_DM_NMI | APIC_LVT_MASKED;
1103 if (!lapic_is_integrated()) /* 82489DX */
1104 value |= APIC_LVT_LEVEL_TRIGGER;
1105 apic_write(APIC_LVT1, value);
1110 void __cpuinit end_local_APIC_setup(void)
1114 #ifdef CONFIG_X86_32
1117 /* Disable the local apic timer */
1118 value = apic_read(APIC_LVTT);
1119 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1120 apic_write(APIC_LVTT, value);
1124 setup_apic_nmi_watchdog(NULL);
1128 void check_x2apic(void)
1132 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1134 if (msr & X2APIC_ENABLE) {
1135 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1136 x2apic_preenabled = x2apic = 1;
1137 apic_ops = &x2apic_ops;
1141 void enable_x2apic(void)
1145 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1146 if (!(msr & X2APIC_ENABLE)) {
1147 printk("Enabling x2apic\n");
1148 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1152 void enable_IR_x2apic(void)
1154 #ifdef CONFIG_INTR_REMAP
1156 unsigned long flags;
1158 if (!cpu_has_x2apic)
1161 if (!x2apic_preenabled && disable_x2apic) {
1163 "Skipped enabling x2apic and Interrupt-remapping "
1164 "because of nox2apic\n");
1168 if (x2apic_preenabled && disable_x2apic)
1169 panic("Bios already enabled x2apic, can't enforce nox2apic");
1171 if (!x2apic_preenabled && skip_ioapic_setup) {
1173 "Skipped enabling x2apic and Interrupt-remapping "
1174 "because of skipping io-apic setup\n");
1178 ret = dmar_table_init();
1181 "dmar_table_init() failed with %d:\n", ret);
1183 if (x2apic_preenabled)
1184 panic("x2apic enabled by bios. But IR enabling failed");
1187 "Not enabling x2apic,Intr-remapping\n");
1191 local_irq_save(flags);
1193 save_mask_IO_APIC_setup();
1195 ret = enable_intr_remapping(1);
1197 if (ret && x2apic_preenabled) {
1198 local_irq_restore(flags);
1199 panic("x2apic enabled by bios. But IR enabling failed");
1207 apic_ops = &x2apic_ops;
1213 * IR enabling failed
1215 restore_IO_APIC_setup();
1217 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1220 local_irq_restore(flags);
1223 if (!x2apic_preenabled)
1225 "Enabled x2apic and interrupt-remapping\n");
1228 "Enabled Interrupt-remapping\n");
1231 "Failed to enable Interrupt-remapping and x2apic\n");
1233 if (!cpu_has_x2apic)
1236 if (x2apic_preenabled)
1237 panic("x2apic enabled prior OS handover,"
1238 " enable CONFIG_INTR_REMAP");
1240 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1248 * Detect and enable local APICs on non-SMP boards.
1249 * Original code written by Keir Fraser.
1250 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1251 * not correctly set up (usually the APIC timer won't work etc.)
1253 static int __init detect_init_APIC(void)
1255 if (!cpu_has_apic) {
1256 printk(KERN_INFO "No local APIC present\n");
1260 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1261 boot_cpu_physical_apicid = 0;
1265 void __init early_init_lapic_mapping(void)
1267 unsigned long phys_addr;
1270 * If no local APIC can be found then go out
1271 * : it means there is no mpatable and MADT
1273 if (!smp_found_config)
1276 phys_addr = mp_lapic_addr;
1278 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1279 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1280 APIC_BASE, phys_addr);
1283 * Fetch the APIC ID of the BSP in case we have a
1284 * default configuration (or the MP table is broken).
1286 boot_cpu_physical_apicid = read_apic_id();
1290 * init_apic_mappings - initialize APIC mappings
1292 void __init init_apic_mappings(void)
1295 boot_cpu_physical_apicid = read_apic_id();
1300 * If no local APIC can be found then set up a fake all
1301 * zeroes page to simulate the local APIC and another
1302 * one for the IO-APIC.
1304 if (!smp_found_config && detect_init_APIC()) {
1305 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1306 apic_phys = __pa(apic_phys);
1308 apic_phys = mp_lapic_addr;
1310 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1311 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1312 APIC_BASE, apic_phys);
1315 * Fetch the APIC ID of the BSP in case we have a
1316 * default configuration (or the MP table is broken).
1318 boot_cpu_physical_apicid = read_apic_id();
1322 * This initializes the IO-APIC and APIC hardware if this is
1325 int apic_version[MAX_APICS];
1327 int __init APIC_init_uniprocessor(void)
1330 printk(KERN_INFO "Apic disabled\n");
1333 if (!cpu_has_apic) {
1335 printk(KERN_INFO "Apic disabled by BIOS\n");
1340 setup_apic_routing();
1342 verify_local_APIC();
1346 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1347 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1352 * Now enable IO-APICs, actually call clear_IO_APIC
1353 * We need clear_IO_APIC before enabling vector on BP
1355 if (!skip_ioapic_setup && nr_ioapics)
1358 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1359 localise_nmi_watchdog();
1360 end_local_APIC_setup();
1362 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1366 setup_boot_APIC_clock();
1367 check_nmi_watchdog();
1372 * Local APIC interrupts
1376 * This interrupt should _never_ happen with our APIC/SMP architecture
1378 asmlinkage void smp_spurious_interrupt(void)
1384 * Check if this really is a spurious interrupt and ACK it
1385 * if it is a vectored one. Just in case...
1386 * Spurious interrupts should not be ACKed.
1388 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1389 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1392 add_pda(irq_spurious_count, 1);
1397 * This interrupt should never happen with our APIC/SMP architecture
1399 asmlinkage void smp_error_interrupt(void)
1405 /* First tickle the hardware, only then report what went on. -- REW */
1406 v = apic_read(APIC_ESR);
1407 apic_write(APIC_ESR, 0);
1408 v1 = apic_read(APIC_ESR);
1410 atomic_inc(&irq_err_count);
1412 /* Here is what the APIC error bits mean:
1415 2: Send accept error
1416 3: Receive accept error
1418 5: Send illegal vector
1419 6: Received illegal vector
1420 7: Illegal register address
1422 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1423 smp_processor_id(), v , v1);
1428 * connect_bsp_APIC - attach the APIC to the interrupt system
1430 void __init connect_bsp_APIC(void)
1432 #ifdef CONFIG_X86_32
1435 * Do not trust the local APIC being empty at bootup.
1439 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1440 * local APIC to INT and NMI lines.
1442 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1443 "enabling APIC mode.\n");
1452 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1453 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1455 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1458 void disconnect_bsp_APIC(int virt_wire_setup)
1462 #ifdef CONFIG_X86_32
1465 * Put the board back into PIC mode (has an effect only on
1466 * certain older boards). Note that APIC interrupts, including
1467 * IPIs, won't work beyond this point! The only exception are
1470 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1471 "entering PIC mode.\n");
1478 /* Go back to Virtual Wire compatibility mode */
1480 /* For the spurious interrupt use vector F, and enable it */
1481 value = apic_read(APIC_SPIV);
1482 value &= ~APIC_VECTOR_MASK;
1483 value |= APIC_SPIV_APIC_ENABLED;
1485 apic_write(APIC_SPIV, value);
1487 if (!virt_wire_setup) {
1489 * For LVT0 make it edge triggered, active high,
1490 * external and enabled
1492 value = apic_read(APIC_LVT0);
1493 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1494 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1495 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1496 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1497 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1498 apic_write(APIC_LVT0, value);
1501 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1505 * For LVT1 make it edge triggered, active high,
1508 value = apic_read(APIC_LVT1);
1509 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1510 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1511 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1512 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1513 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1514 apic_write(APIC_LVT1, value);
1517 void __cpuinit generic_processor_info(int apicid, int version)
1525 if (version == 0x0) {
1526 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1527 "fixing up to 0x10. (tell your hw vendor)\n",
1531 apic_version[apicid] = version;
1533 if (num_processors >= NR_CPUS) {
1534 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1535 " Processor ignored.\n", NR_CPUS);
1540 cpus_complement(tmp_map, cpu_present_map);
1541 cpu = first_cpu(tmp_map);
1543 physid_set(apicid, phys_cpu_present_map);
1544 if (apicid == boot_cpu_physical_apicid) {
1546 * x86_bios_cpu_apicid is required to have processors listed
1547 * in same order as logical cpu numbers. Hence the first
1548 * entry is BSP, and so on.
1552 if (apicid > max_physical_apicid)
1553 max_physical_apicid = apicid;
1555 #ifdef CONFIG_X86_32
1557 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1558 * but we need to work other dependencies like SMP_SUSPEND etc
1559 * before this can be done without some confusion.
1560 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1561 * - Ashok Raj <ashok.raj@intel.com>
1563 if (max_physical_apicid >= 8) {
1564 switch (boot_cpu_data.x86_vendor) {
1565 case X86_VENDOR_INTEL:
1566 if (!APIC_XAPIC(version)) {
1570 /* If P4 and above fall through */
1571 case X86_VENDOR_AMD:
1577 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1578 /* are we being called early in kernel startup? */
1579 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1580 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1581 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1583 cpu_to_apicid[cpu] = apicid;
1584 bios_cpu_apicid[cpu] = apicid;
1586 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1587 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1591 cpu_set(cpu, cpu_possible_map);
1592 cpu_set(cpu, cpu_present_map);
1595 int hard_smp_processor_id(void)
1597 return read_apic_id();
1607 * 'active' is true if the local APIC was enabled by us and
1608 * not the BIOS; this signifies that we are also responsible
1609 * for disabling it before entering apm/acpi suspend
1612 /* r/w apic fields */
1613 unsigned int apic_id;
1614 unsigned int apic_taskpri;
1615 unsigned int apic_ldr;
1616 unsigned int apic_dfr;
1617 unsigned int apic_spiv;
1618 unsigned int apic_lvtt;
1619 unsigned int apic_lvtpc;
1620 unsigned int apic_lvt0;
1621 unsigned int apic_lvt1;
1622 unsigned int apic_lvterr;
1623 unsigned int apic_tmict;
1624 unsigned int apic_tdcr;
1625 unsigned int apic_thmr;
1628 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1630 unsigned long flags;
1633 if (!apic_pm_state.active)
1636 maxlvt = lapic_get_maxlvt();
1638 apic_pm_state.apic_id = apic_read(APIC_ID);
1639 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1640 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1641 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1642 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1643 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1645 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1646 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1647 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1648 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1649 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1650 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1651 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1653 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1656 local_irq_save(flags);
1657 disable_local_APIC();
1658 local_irq_restore(flags);
1662 static int lapic_resume(struct sys_device *dev)
1665 unsigned long flags;
1668 if (!apic_pm_state.active)
1671 maxlvt = lapic_get_maxlvt();
1673 local_irq_save(flags);
1675 #ifdef CONFIG_X86_64
1682 * Make sure the APICBASE points to the right address
1684 * FIXME! This will be wrong if we ever support suspend on
1685 * SMP! We'll need to do this as part of the CPU restore!
1687 rdmsr(MSR_IA32_APICBASE, l, h);
1688 l &= ~MSR_IA32_APICBASE_BASE;
1689 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1690 wrmsr(MSR_IA32_APICBASE, l, h);
1693 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1694 apic_write(APIC_ID, apic_pm_state.apic_id);
1695 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1696 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1697 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1698 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1699 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1700 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1701 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1703 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1706 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1707 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1708 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1709 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1710 apic_write(APIC_ESR, 0);
1711 apic_read(APIC_ESR);
1712 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1713 apic_write(APIC_ESR, 0);
1714 apic_read(APIC_ESR);
1716 local_irq_restore(flags);
1722 * This device has no shutdown method - fully functioning local APICs
1723 * are needed on every CPU up until machine_halt/restart/poweroff.
1726 static struct sysdev_class lapic_sysclass = {
1728 .resume = lapic_resume,
1729 .suspend = lapic_suspend,
1732 static struct sys_device device_lapic = {
1734 .cls = &lapic_sysclass,
1737 static void __cpuinit apic_pm_activate(void)
1739 apic_pm_state.active = 1;
1742 static int __init init_lapic_sysfs(void)
1748 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1750 error = sysdev_class_register(&lapic_sysclass);
1752 error = sysdev_register(&device_lapic);
1755 device_initcall(init_lapic_sysfs);
1757 #else /* CONFIG_PM */
1759 static void apic_pm_activate(void) { }
1761 #endif /* CONFIG_PM */
1764 * apic_is_clustered_box() -- Check if we can expect good TSC
1766 * Thus far, the major user of this is IBM's Summit2 series:
1768 * Clustered boxes may have unsynced TSC problems if they are
1769 * multi-chassis. Use available data to take a good guess.
1770 * If in doubt, go HPET.
1772 __cpuinit int apic_is_clustered_box(void)
1774 int i, clusters, zeros;
1776 u16 *bios_cpu_apicid;
1777 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1780 * there is not this kind of box with AMD CPU yet.
1781 * Some AMD box with quadcore cpu and 8 sockets apicid
1782 * will be [4, 0x23] or [8, 0x27] could be thought to
1783 * vsmp box still need checking...
1785 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1788 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1789 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1791 for (i = 0; i < NR_CPUS; i++) {
1792 /* are we being called early in kernel startup? */
1793 if (bios_cpu_apicid) {
1794 id = bios_cpu_apicid[i];
1796 else if (i < nr_cpu_ids) {
1798 id = per_cpu(x86_bios_cpu_apicid, i);
1805 if (id != BAD_APICID)
1806 __set_bit(APIC_CLUSTERID(id), clustermap);
1809 /* Problem: Partially populated chassis may not have CPUs in some of
1810 * the APIC clusters they have been allocated. Only present CPUs have
1811 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1812 * Since clusters are allocated sequentially, count zeros only if
1813 * they are bounded by ones.
1817 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1818 if (test_bit(i, clustermap)) {
1819 clusters += 1 + zeros;
1825 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1826 * not guaranteed to be synced between boards
1828 if (is_vsmp_box() && clusters > 1)
1832 * If clusters > 2, then should be multi-chassis.
1833 * May have to revisit this when multi-core + hyperthreaded CPUs come
1834 * out, but AFAIK this will work even for them.
1836 return (clusters > 2);
1839 static __init int setup_nox2apic(char *str)
1842 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1845 early_param("nox2apic", setup_nox2apic);
1849 * APIC command line parameters
1851 static int __init setup_disableapic(char *arg)
1854 setup_clear_cpu_cap(X86_FEATURE_APIC);
1857 early_param("disableapic", setup_disableapic);
1859 /* same as disableapic, for compatibility */
1860 static int __init setup_nolapic(char *arg)
1862 return setup_disableapic(arg);
1864 early_param("nolapic", setup_nolapic);
1866 static int __init parse_lapic_timer_c2_ok(char *arg)
1868 local_apic_timer_c2_ok = 1;
1871 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1873 static int __init parse_disable_apic_timer(char *arg)
1875 disable_apic_timer = 1;
1878 early_param("noapictimer", parse_disable_apic_timer);
1880 static int __init parse_nolapic_timer(char *arg)
1882 disable_apic_timer = 1;
1885 early_param("nolapic_timer", parse_nolapic_timer);
1887 static int __init apic_set_verbosity(char *arg)
1890 #ifdef CONFIG_X86_64
1891 skip_ioapic_setup = 0;
1897 if (strcmp("debug", arg) == 0)
1898 apic_verbosity = APIC_DEBUG;
1899 else if (strcmp("verbose", arg) == 0)
1900 apic_verbosity = APIC_VERBOSE;
1902 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1903 " use apic=verbose or apic=debug\n", arg);
1909 early_param("apic", apic_set_verbosity);
1911 static int __init lapic_insert_resource(void)
1916 /* Put local APIC into the resource map. */
1917 lapic_resource.start = apic_phys;
1918 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1919 insert_resource(&iomem_resource, &lapic_resource);
1925 * need call insert after e820_reserve_resources()
1926 * that is using request_resource
1928 late_initcall(lapic_insert_resource);