2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
49 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
50 static int disable_apic_timer __cpuinitdata;
51 static int apic_calibrate_pmtmr __initdata;
56 /* x2apic enabled before OS handover */
57 int x2apic_preenabled;
59 /* Local APIC timer works in C2 */
60 int local_apic_timer_c2_ok;
61 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
63 int first_system_vector = 0xfe;
65 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
68 * Debug level, exported for io_apic.c
70 unsigned int apic_verbosity;
72 /* Have we found an MP table */
75 static struct resource lapic_resource = {
77 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
80 static unsigned int calibration_result;
82 static int lapic_next_event(unsigned long delta,
83 struct clock_event_device *evt);
84 static void lapic_timer_setup(enum clock_event_mode mode,
85 struct clock_event_device *evt);
86 static void lapic_timer_broadcast(cpumask_t mask);
87 static void apic_pm_activate(void);
90 * The local apic timer can be used for any function which is CPU local.
92 static struct clock_event_device lapic_clockevent = {
94 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
95 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
97 .set_mode = lapic_timer_setup,
98 .set_next_event = lapic_next_event,
99 .broadcast = lapic_timer_broadcast,
103 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
105 static unsigned long apic_phys;
107 unsigned long mp_lapic_addr;
110 * Get the LAPIC version
112 static inline int lapic_get_version(void)
114 return GET_APIC_VERSION(apic_read(APIC_LVR));
118 * Check, if the APIC is integrated or a separate chip
120 static inline int lapic_is_integrated(void)
125 return APIC_INTEGRATED(lapic_get_version());
130 * Check, whether this is a modern or a first generation APIC
132 static int modern_apic(void)
134 /* AMD systems use old APIC versions, so check the CPU */
135 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
136 boot_cpu_data.x86 >= 0xf)
138 return lapic_get_version() >= 0x14;
142 * Paravirt kernels also might be using these below ops. So we still
143 * use generic apic_read()/apic_write(), which might be pointing to different
144 * ops in PARAVIRT case.
146 void xapic_wait_icr_idle(void)
148 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
152 u32 safe_xapic_wait_icr_idle(void)
159 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
163 } while (timeout++ < 1000);
168 void xapic_icr_write(u32 low, u32 id)
170 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
171 apic_write(APIC_ICR, low);
174 u64 xapic_icr_read(void)
178 icr2 = apic_read(APIC_ICR2);
179 icr1 = apic_read(APIC_ICR);
181 return icr1 | ((u64)icr2 << 32);
184 static struct apic_ops xapic_ops = {
185 .read = native_apic_mem_read,
186 .write = native_apic_mem_write,
187 .icr_read = xapic_icr_read,
188 .icr_write = xapic_icr_write,
189 .wait_icr_idle = xapic_wait_icr_idle,
190 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
193 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
194 EXPORT_SYMBOL_GPL(apic_ops);
196 static void x2apic_wait_icr_idle(void)
198 /* no need to wait for icr idle in x2apic */
202 static u32 safe_x2apic_wait_icr_idle(void)
204 /* no need to wait for icr idle in x2apic */
208 void x2apic_icr_write(u32 low, u32 id)
210 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
213 u64 x2apic_icr_read(void)
217 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
221 static struct apic_ops x2apic_ops = {
222 .read = native_apic_msr_read,
223 .write = native_apic_msr_write,
224 .icr_read = x2apic_icr_read,
225 .icr_write = x2apic_icr_write,
226 .wait_icr_idle = x2apic_wait_icr_idle,
227 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
231 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
233 void __cpuinit enable_NMI_through_LVT0(void)
237 /* unmask and set to NMI */
240 /* Level triggered for 82489DX (32bit mode) */
241 if (!lapic_is_integrated())
242 v |= APIC_LVT_LEVEL_TRIGGER;
244 apic_write(APIC_LVT0, v);
248 * lapic_get_maxlvt - get the maximum number of local vector table entries
250 int lapic_get_maxlvt(void)
254 v = apic_read(APIC_LVR);
256 * - we always have APIC integrated on 64bit mode
257 * - 82489DXs do not report # of LVT entries
259 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
268 #define APIC_DIVISOR 1
270 #define APIC_DIVISOR 16
274 * This function sets up the local APIC timer, with a timeout of
275 * 'clocks' APIC bus clock. During calibration we actually call
276 * this function twice on the boot CPU, once with a bogus timeout
277 * value, second time for real. The other (noncalibrating) CPUs
278 * call this function only once, with the real, calibrated value.
280 * We do reads before writes even if unnecessary, to get around the
281 * P5 APIC double write bug.
283 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
285 unsigned int lvtt_value, tmp_value;
287 lvtt_value = LOCAL_TIMER_VECTOR;
289 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
290 if (!lapic_is_integrated())
291 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
294 lvtt_value |= APIC_LVT_MASKED;
296 apic_write(APIC_LVTT, lvtt_value);
301 tmp_value = apic_read(APIC_TDCR);
302 apic_write(APIC_TDCR,
303 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
307 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
311 * Setup extended LVT, AMD specific (K8, family 10h)
313 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
314 * MCE interrupts are supported. Thus MCE offset must be set to 0.
316 * If mask=1, the LVT entry does not generate interrupts while mask=0
317 * enables the vector. See also the BKDGs.
320 #define APIC_EILVT_LVTOFF_MCE 0
321 #define APIC_EILVT_LVTOFF_IBS 1
323 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
325 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
326 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
331 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
333 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
334 return APIC_EILVT_LVTOFF_MCE;
337 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
339 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
340 return APIC_EILVT_LVTOFF_IBS;
342 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
345 * Program the next event, relative to now
347 static int lapic_next_event(unsigned long delta,
348 struct clock_event_device *evt)
350 apic_write(APIC_TMICT, delta);
355 * Setup the lapic timer in periodic or oneshot mode
357 static void lapic_timer_setup(enum clock_event_mode mode,
358 struct clock_event_device *evt)
363 /* Lapic used as dummy for broadcast ? */
364 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
367 local_irq_save(flags);
370 case CLOCK_EVT_MODE_PERIODIC:
371 case CLOCK_EVT_MODE_ONESHOT:
372 __setup_APIC_LVTT(calibration_result,
373 mode != CLOCK_EVT_MODE_PERIODIC, 1);
375 case CLOCK_EVT_MODE_UNUSED:
376 case CLOCK_EVT_MODE_SHUTDOWN:
377 v = apic_read(APIC_LVTT);
378 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
379 apic_write(APIC_LVTT, v);
381 case CLOCK_EVT_MODE_RESUME:
382 /* Nothing to do here */
386 local_irq_restore(flags);
390 * Local APIC timer broadcast function
392 static void lapic_timer_broadcast(cpumask_t mask)
395 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
400 * Setup the local APIC timer for this CPU. Copy the initilized values
401 * of the boot CPU and register the clock event in the framework.
403 static void setup_APIC_timer(void)
405 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
407 memcpy(levt, &lapic_clockevent, sizeof(*levt));
408 levt->cpumask = cpumask_of_cpu(smp_processor_id());
410 clockevents_register_device(levt);
414 * In this function we calibrate APIC bus clocks to the external
415 * timer. Unfortunately we cannot use jiffies and the timer irq
416 * to calibrate, since some later bootup code depends on getting
417 * the first irq? Ugh.
419 * We want to do the calibration only once since we
420 * want to have local timer irqs syncron. CPUs connected
421 * by the same APIC bus have the very same bus frequency.
422 * And we want to have irqs off anyways, no accidental
426 #define TICK_COUNT 100000000
428 static int __init calibrate_APIC_clock(void)
430 unsigned apic, apic_start;
431 unsigned long tsc, tsc_start;
437 * Put whatever arbitrary (but long enough) timeout
438 * value into the APIC clock, we just want to get the
439 * counter running for calibration.
441 * No interrupt enable !
443 __setup_APIC_LVTT(250000000, 0, 0);
445 apic_start = apic_read(APIC_TMCCT);
446 #ifdef CONFIG_X86_PM_TIMER
447 if (apic_calibrate_pmtmr && pmtmr_ioport) {
448 pmtimer_wait(5000); /* 5ms wait */
449 apic = apic_read(APIC_TMCCT);
450 result = (apic_start - apic) * 1000L / 5;
457 apic = apic_read(APIC_TMCCT);
459 } while ((tsc - tsc_start) < TICK_COUNT &&
460 (apic_start - apic) < TICK_COUNT);
462 result = (apic_start - apic) * 1000L * tsc_khz /
468 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
470 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
471 result / 1000 / 1000, result / 1000 % 1000);
473 /* Calculate the scaled math multiplication factor */
474 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
475 lapic_clockevent.shift);
476 lapic_clockevent.max_delta_ns =
477 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
478 lapic_clockevent.min_delta_ns =
479 clockevent_delta2ns(0xF, &lapic_clockevent);
481 calibration_result = (result * APIC_DIVISOR) / HZ;
484 * Do a sanity check on the APIC calibration result
486 if (calibration_result < (1000000 / HZ)) {
488 "APIC frequency too slow, disabling apic timer\n");
496 * Setup the boot APIC
498 * Calibrate and verify the result.
500 void __init setup_boot_APIC_clock(void)
503 * The local apic timer can be disabled via the kernel
504 * commandline or from the CPU detection code. Register the lapic
505 * timer as a dummy clock event source on SMP systems, so the
506 * broadcast mechanism is used. On UP systems simply ignore it.
508 if (disable_apic_timer) {
509 printk(KERN_INFO "Disabling APIC timer\n");
510 /* No broadcast on UP ! */
511 if (num_possible_cpus() > 1) {
512 lapic_clockevent.mult = 1;
518 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
519 "calibrating APIC timer ...\n");
521 if (calibrate_APIC_clock()) {
522 /* No broadcast on UP ! */
523 if (num_possible_cpus() > 1)
529 * If nmi_watchdog is set to IO_APIC, we need the
530 * PIT/HPET going. Otherwise register lapic as a dummy
533 if (nmi_watchdog != NMI_IO_APIC)
534 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
536 printk(KERN_WARNING "APIC timer registered as dummy,"
537 " due to nmi_watchdog=%d!\n", nmi_watchdog);
539 /* Setup the lapic or request the broadcast */
543 void __cpuinit setup_secondary_APIC_clock(void)
549 * The guts of the apic timer interrupt
551 static void local_apic_timer_interrupt(void)
553 int cpu = smp_processor_id();
554 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
557 * Normally we should not be here till LAPIC has been initialized but
558 * in some cases like kdump, its possible that there is a pending LAPIC
559 * timer interrupt from previous kernel's context and is delivered in
560 * new kernel the moment interrupts are enabled.
562 * Interrupts are enabled early and LAPIC is setup much later, hence
563 * its possible that when we get here evt->event_handler is NULL.
564 * Check for event_handler being NULL and discard the interrupt as
567 if (!evt->event_handler) {
569 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
571 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
576 * the NMI deadlock-detector uses this.
579 add_pda(apic_timer_irqs, 1);
581 per_cpu(irq_stat, cpu).apic_timer_irqs++;
584 evt->event_handler(evt);
588 * Local APIC timer interrupt. This is the most natural way for doing
589 * local interrupts, but local timer interrupts can be emulated by
590 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
592 * [ if a single-CPU system runs an SMP kernel then we call the local
593 * interrupt as well. Thus we cannot inline the local irq ... ]
595 void smp_apic_timer_interrupt(struct pt_regs *regs)
597 struct pt_regs *old_regs = set_irq_regs(regs);
600 * NOTE! We'd better ACK the irq immediately,
601 * because timer handling can be slow.
605 * update_process_times() expects us to have done irq_enter().
606 * Besides, if we don't timer interrupts ignore the global
607 * interrupt lock, which is the WrongThing (tm) to do.
611 local_apic_timer_interrupt();
614 set_irq_regs(old_regs);
617 int setup_profiling_timer(unsigned int multiplier)
624 * Local APIC start and shutdown
628 * clear_local_APIC - shutdown the local APIC
630 * This is called, when a CPU is disabled and before rebooting, so the state of
631 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
632 * leftovers during boot.
634 void clear_local_APIC(void)
639 /* APIC hasn't been mapped yet */
643 maxlvt = lapic_get_maxlvt();
645 * Masking an LVT entry can trigger a local APIC error
646 * if the vector is zero. Mask LVTERR first to prevent this.
649 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
650 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
653 * Careful: we have to set masks only first to deassert
654 * any level-triggered sources.
656 v = apic_read(APIC_LVTT);
657 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
658 v = apic_read(APIC_LVT0);
659 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
660 v = apic_read(APIC_LVT1);
661 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
663 v = apic_read(APIC_LVTPC);
664 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
667 /* lets not touch this if we didn't frob it */
668 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
670 v = apic_read(APIC_LVTTHMR);
671 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
675 * Clean APIC state for other OSs:
677 apic_write(APIC_LVTT, APIC_LVT_MASKED);
678 apic_write(APIC_LVT0, APIC_LVT_MASKED);
679 apic_write(APIC_LVT1, APIC_LVT_MASKED);
681 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
683 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
685 /* Integrated APIC (!82489DX) ? */
686 if (lapic_is_integrated()) {
688 /* Clear ESR due to Pentium errata 3AP and 11AP */
689 apic_write(APIC_ESR, 0);
695 * disable_local_APIC - clear and disable the local APIC
697 void disable_local_APIC(void)
704 * Disable APIC (implies clearing of registers
707 value = apic_read(APIC_SPIV);
708 value &= ~APIC_SPIV_APIC_ENABLED;
709 apic_write(APIC_SPIV, value);
713 * When LAPIC was disabled by the BIOS and enabled by the kernel,
714 * restore the disabled state.
716 if (enabled_via_apicbase) {
719 rdmsr(MSR_IA32_APICBASE, l, h);
720 l &= ~MSR_IA32_APICBASE_ENABLE;
721 wrmsr(MSR_IA32_APICBASE, l, h);
727 * If Linux enabled the LAPIC against the BIOS default disable it down before
728 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
729 * not power-off. Additionally clear all LVT entries before disable_local_APIC
730 * for the case where Linux didn't enable the LAPIC.
732 void lapic_shutdown(void)
739 local_irq_save(flags);
742 if (!enabled_via_apicbase)
746 disable_local_APIC();
749 local_irq_restore(flags);
753 * This is to verify that we're looking at a real local APIC.
754 * Check these against your board if the CPUs aren't getting
755 * started for no apparent reason.
757 int __init verify_local_APIC(void)
759 unsigned int reg0, reg1;
762 * The version register is read-only in a real APIC.
764 reg0 = apic_read(APIC_LVR);
765 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
766 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
767 reg1 = apic_read(APIC_LVR);
768 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
771 * The two version reads above should print the same
772 * numbers. If the second one is different, then we
773 * poke at a non-APIC.
779 * Check if the version looks reasonably.
781 reg1 = GET_APIC_VERSION(reg0);
782 if (reg1 == 0x00 || reg1 == 0xff)
784 reg1 = lapic_get_maxlvt();
785 if (reg1 < 0x02 || reg1 == 0xff)
789 * The ID register is read/write in a real APIC.
791 reg0 = apic_read(APIC_ID);
792 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
793 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
794 reg1 = apic_read(APIC_ID);
795 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
796 apic_write(APIC_ID, reg0);
797 if (reg1 != (reg0 ^ APIC_ID_MASK))
801 * The next two are just to see if we have sane values.
802 * They're only really relevant if we're in Virtual Wire
803 * compatibility mode, but most boxes are anymore.
805 reg0 = apic_read(APIC_LVT0);
806 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
807 reg1 = apic_read(APIC_LVT1);
808 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
814 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
816 void __init sync_Arb_IDs(void)
819 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
822 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
828 apic_wait_icr_idle();
830 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
831 apic_write(APIC_ICR, APIC_DEST_ALLINC |
832 APIC_INT_LEVELTRIG | APIC_DM_INIT);
836 * An initial setup of the virtual wire mode.
838 void __init init_bsp_APIC(void)
843 * Don't do the setup now if we have a SMP BIOS as the
844 * through-I/O-APIC virtual wire mode might be active.
846 if (smp_found_config || !cpu_has_apic)
850 * Do not trust the local APIC being empty at bootup.
857 value = apic_read(APIC_SPIV);
858 value &= ~APIC_VECTOR_MASK;
859 value |= APIC_SPIV_APIC_ENABLED;
862 /* This bit is reserved on P4/Xeon and should be cleared */
863 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
864 (boot_cpu_data.x86 == 15))
865 value &= ~APIC_SPIV_FOCUS_DISABLED;
868 value |= APIC_SPIV_FOCUS_DISABLED;
869 value |= SPURIOUS_APIC_VECTOR;
870 apic_write(APIC_SPIV, value);
873 * Set up the virtual wire mode.
875 apic_write(APIC_LVT0, APIC_DM_EXTINT);
877 if (!lapic_is_integrated()) /* 82489DX */
878 value |= APIC_LVT_LEVEL_TRIGGER;
879 apic_write(APIC_LVT1, value);
882 static void __cpuinit lapic_setup_esr(void)
884 unsigned long oldvalue, value, maxlvt;
885 if (lapic_is_integrated() && !esr_disable) {
888 * Something untraceable is creating bad interrupts on
889 * secondary quads ... for the moment, just leave the
890 * ESR disabled - we can't do anything useful with the
891 * errors anyway - mbligh
893 printk(KERN_INFO "Leaving ESR disabled.\n");
897 maxlvt = lapic_get_maxlvt();
898 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
899 apic_write(APIC_ESR, 0);
900 oldvalue = apic_read(APIC_ESR);
902 /* enables sending errors */
903 value = ERROR_APIC_VECTOR;
904 apic_write(APIC_LVTERR, value);
906 * spec says clear errors after enabling vector.
909 apic_write(APIC_ESR, 0);
910 value = apic_read(APIC_ESR);
911 if (value != oldvalue)
912 apic_printk(APIC_VERBOSE, "ESR value before enabling "
913 "vector: 0x%08lx after: 0x%08lx\n",
916 printk(KERN_INFO "No ESR for 82489DX.\n");
922 * setup_local_APIC - setup the local APIC
924 void __cpuinit setup_local_APIC(void)
930 value = apic_read(APIC_LVR);
932 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
935 * Double-check whether this APIC is really registered.
936 * This is meaningless in clustered apic mode, so we skip it.
938 if (!apic_id_registered())
942 * Intel recommends to set DFR, LDR and TPR before enabling
943 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
944 * document number 292116). So here it goes...
949 * Set Task Priority to 'accept all'. We never change this
952 value = apic_read(APIC_TASKPRI);
953 value &= ~APIC_TPRI_MASK;
954 apic_write(APIC_TASKPRI, value);
957 * After a crash, we no longer service the interrupts and a pending
958 * interrupt from previous kernel might still have ISR bit set.
960 * Most probably by now CPU has serviced that pending interrupt and
961 * it might not have done the ack_APIC_irq() because it thought,
962 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
963 * does not clear the ISR bit and cpu thinks it has already serivced
964 * the interrupt. Hence a vector might get locked. It was noticed
965 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
967 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
968 value = apic_read(APIC_ISR + i*0x10);
969 for (j = 31; j >= 0; j--) {
976 * Now that we are all set up, enable the APIC
978 value = apic_read(APIC_SPIV);
979 value &= ~APIC_VECTOR_MASK;
983 value |= APIC_SPIV_APIC_ENABLED;
985 /* We always use processor focus */
988 * Set spurious IRQ vector
990 value |= SPURIOUS_APIC_VECTOR;
991 apic_write(APIC_SPIV, value);
996 * set up through-local-APIC on the BP's LINT0. This is not
997 * strictly necessary in pure symmetric-IO mode, but sometimes
998 * we delegate interrupts to the 8259A.
1001 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1003 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1004 if (!smp_processor_id() && !value) {
1005 value = APIC_DM_EXTINT;
1006 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1007 smp_processor_id());
1009 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1010 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1011 smp_processor_id());
1013 apic_write(APIC_LVT0, value);
1016 * only the BP should see the LINT1 NMI signal, obviously.
1018 if (!smp_processor_id())
1019 value = APIC_DM_NMI;
1021 value = APIC_DM_NMI | APIC_LVT_MASKED;
1022 apic_write(APIC_LVT1, value);
1026 void __cpuinit end_local_APIC_setup(void)
1030 #ifdef CONFIG_X86_32
1033 /* Disable the local apic timer */
1034 value = apic_read(APIC_LVTT);
1035 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1036 apic_write(APIC_LVTT, value);
1040 setup_apic_nmi_watchdog(NULL);
1044 void check_x2apic(void)
1048 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1050 if (msr & X2APIC_ENABLE) {
1051 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1052 x2apic_preenabled = x2apic = 1;
1053 apic_ops = &x2apic_ops;
1057 void enable_x2apic(void)
1061 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1062 if (!(msr & X2APIC_ENABLE)) {
1063 printk("Enabling x2apic\n");
1064 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1068 void enable_IR_x2apic(void)
1070 #ifdef CONFIG_INTR_REMAP
1072 unsigned long flags;
1074 if (!cpu_has_x2apic)
1077 if (!x2apic_preenabled && disable_x2apic) {
1079 "Skipped enabling x2apic and Interrupt-remapping "
1080 "because of nox2apic\n");
1084 if (x2apic_preenabled && disable_x2apic)
1085 panic("Bios already enabled x2apic, can't enforce nox2apic");
1087 if (!x2apic_preenabled && skip_ioapic_setup) {
1089 "Skipped enabling x2apic and Interrupt-remapping "
1090 "because of skipping io-apic setup\n");
1094 ret = dmar_table_init();
1097 "dmar_table_init() failed with %d:\n", ret);
1099 if (x2apic_preenabled)
1100 panic("x2apic enabled by bios. But IR enabling failed");
1103 "Not enabling x2apic,Intr-remapping\n");
1107 local_irq_save(flags);
1109 save_mask_IO_APIC_setup();
1111 ret = enable_intr_remapping(1);
1113 if (ret && x2apic_preenabled) {
1114 local_irq_restore(flags);
1115 panic("x2apic enabled by bios. But IR enabling failed");
1123 apic_ops = &x2apic_ops;
1129 * IR enabling failed
1131 restore_IO_APIC_setup();
1133 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1136 local_irq_restore(flags);
1139 if (!x2apic_preenabled)
1141 "Enabled x2apic and interrupt-remapping\n");
1144 "Enabled Interrupt-remapping\n");
1147 "Failed to enable Interrupt-remapping and x2apic\n");
1149 if (!cpu_has_x2apic)
1152 if (x2apic_preenabled)
1153 panic("x2apic enabled prior OS handover,"
1154 " enable CONFIG_INTR_REMAP");
1156 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1164 * Detect and enable local APICs on non-SMP boards.
1165 * Original code written by Keir Fraser.
1166 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1167 * not correctly set up (usually the APIC timer won't work etc.)
1169 static int __init detect_init_APIC(void)
1171 if (!cpu_has_apic) {
1172 printk(KERN_INFO "No local APIC present\n");
1176 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1177 boot_cpu_physical_apicid = 0;
1181 void __init early_init_lapic_mapping(void)
1183 unsigned long phys_addr;
1186 * If no local APIC can be found then go out
1187 * : it means there is no mpatable and MADT
1189 if (!smp_found_config)
1192 phys_addr = mp_lapic_addr;
1194 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1195 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1196 APIC_BASE, phys_addr);
1199 * Fetch the APIC ID of the BSP in case we have a
1200 * default configuration (or the MP table is broken).
1202 boot_cpu_physical_apicid = read_apic_id();
1206 * init_apic_mappings - initialize APIC mappings
1208 void __init init_apic_mappings(void)
1211 boot_cpu_physical_apicid = read_apic_id();
1216 * If no local APIC can be found then set up a fake all
1217 * zeroes page to simulate the local APIC and another
1218 * one for the IO-APIC.
1220 if (!smp_found_config && detect_init_APIC()) {
1221 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1222 apic_phys = __pa(apic_phys);
1224 apic_phys = mp_lapic_addr;
1226 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1227 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1228 APIC_BASE, apic_phys);
1231 * Fetch the APIC ID of the BSP in case we have a
1232 * default configuration (or the MP table is broken).
1234 boot_cpu_physical_apicid = read_apic_id();
1238 * This initializes the IO-APIC and APIC hardware if this is
1241 int apic_version[MAX_APICS];
1243 int __init APIC_init_uniprocessor(void)
1246 printk(KERN_INFO "Apic disabled\n");
1249 if (!cpu_has_apic) {
1251 printk(KERN_INFO "Apic disabled by BIOS\n");
1256 setup_apic_routing();
1258 verify_local_APIC();
1262 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1263 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1268 * Now enable IO-APICs, actually call clear_IO_APIC
1269 * We need clear_IO_APIC before enabling vector on BP
1271 if (!skip_ioapic_setup && nr_ioapics)
1274 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1275 localise_nmi_watchdog();
1276 end_local_APIC_setup();
1278 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1282 setup_boot_APIC_clock();
1283 check_nmi_watchdog();
1288 * Local APIC interrupts
1292 * This interrupt should _never_ happen with our APIC/SMP architecture
1294 asmlinkage void smp_spurious_interrupt(void)
1300 * Check if this really is a spurious interrupt and ACK it
1301 * if it is a vectored one. Just in case...
1302 * Spurious interrupts should not be ACKed.
1304 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1305 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1308 add_pda(irq_spurious_count, 1);
1313 * This interrupt should never happen with our APIC/SMP architecture
1315 asmlinkage void smp_error_interrupt(void)
1321 /* First tickle the hardware, only then report what went on. -- REW */
1322 v = apic_read(APIC_ESR);
1323 apic_write(APIC_ESR, 0);
1324 v1 = apic_read(APIC_ESR);
1326 atomic_inc(&irq_err_count);
1328 /* Here is what the APIC error bits mean:
1331 2: Send accept error
1332 3: Receive accept error
1334 5: Send illegal vector
1335 6: Received illegal vector
1336 7: Illegal register address
1338 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1339 smp_processor_id(), v , v1);
1344 * connect_bsp_APIC - attach the APIC to the interrupt system
1346 void __init connect_bsp_APIC(void)
1348 #ifdef CONFIG_X86_32
1351 * Do not trust the local APIC being empty at bootup.
1355 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1356 * local APIC to INT and NMI lines.
1358 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1359 "enabling APIC mode.\n");
1368 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1369 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1371 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1374 void disconnect_bsp_APIC(int virt_wire_setup)
1378 #ifdef CONFIG_X86_32
1381 * Put the board back into PIC mode (has an effect only on
1382 * certain older boards). Note that APIC interrupts, including
1383 * IPIs, won't work beyond this point! The only exception are
1386 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1387 "entering PIC mode.\n");
1394 /* Go back to Virtual Wire compatibility mode */
1396 /* For the spurious interrupt use vector F, and enable it */
1397 value = apic_read(APIC_SPIV);
1398 value &= ~APIC_VECTOR_MASK;
1399 value |= APIC_SPIV_APIC_ENABLED;
1401 apic_write(APIC_SPIV, value);
1403 if (!virt_wire_setup) {
1405 * For LVT0 make it edge triggered, active high,
1406 * external and enabled
1408 value = apic_read(APIC_LVT0);
1409 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1410 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1411 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1412 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1413 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1414 apic_write(APIC_LVT0, value);
1417 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1421 * For LVT1 make it edge triggered, active high,
1424 value = apic_read(APIC_LVT1);
1425 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1426 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1427 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1428 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1429 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1430 apic_write(APIC_LVT1, value);
1433 void __cpuinit generic_processor_info(int apicid, int version)
1441 if (version == 0x0) {
1442 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1443 "fixing up to 0x10. (tell your hw vendor)\n",
1447 apic_version[apicid] = version;
1449 if (num_processors >= NR_CPUS) {
1450 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1451 " Processor ignored.\n", NR_CPUS);
1456 cpus_complement(tmp_map, cpu_present_map);
1457 cpu = first_cpu(tmp_map);
1459 physid_set(apicid, phys_cpu_present_map);
1460 if (apicid == boot_cpu_physical_apicid) {
1462 * x86_bios_cpu_apicid is required to have processors listed
1463 * in same order as logical cpu numbers. Hence the first
1464 * entry is BSP, and so on.
1468 if (apicid > max_physical_apicid)
1469 max_physical_apicid = apicid;
1471 #ifdef CONFIG_X86_32
1473 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1474 * but we need to work other dependencies like SMP_SUSPEND etc
1475 * before this can be done without some confusion.
1476 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1477 * - Ashok Raj <ashok.raj@intel.com>
1479 if (max_physical_apicid >= 8) {
1480 switch (boot_cpu_data.x86_vendor) {
1481 case X86_VENDOR_INTEL:
1482 if (!APIC_XAPIC(version)) {
1486 /* If P4 and above fall through */
1487 case X86_VENDOR_AMD:
1493 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1494 /* are we being called early in kernel startup? */
1495 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1496 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1497 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1499 cpu_to_apicid[cpu] = apicid;
1500 bios_cpu_apicid[cpu] = apicid;
1502 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1503 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1507 cpu_set(cpu, cpu_possible_map);
1508 cpu_set(cpu, cpu_present_map);
1511 int hard_smp_processor_id(void)
1513 return read_apic_id();
1523 * 'active' is true if the local APIC was enabled by us and
1524 * not the BIOS; this signifies that we are also responsible
1525 * for disabling it before entering apm/acpi suspend
1528 /* r/w apic fields */
1529 unsigned int apic_id;
1530 unsigned int apic_taskpri;
1531 unsigned int apic_ldr;
1532 unsigned int apic_dfr;
1533 unsigned int apic_spiv;
1534 unsigned int apic_lvtt;
1535 unsigned int apic_lvtpc;
1536 unsigned int apic_lvt0;
1537 unsigned int apic_lvt1;
1538 unsigned int apic_lvterr;
1539 unsigned int apic_tmict;
1540 unsigned int apic_tdcr;
1541 unsigned int apic_thmr;
1544 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1546 unsigned long flags;
1549 if (!apic_pm_state.active)
1552 maxlvt = lapic_get_maxlvt();
1554 apic_pm_state.apic_id = apic_read(APIC_ID);
1555 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1556 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1557 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1558 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1559 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1561 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1562 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1563 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1564 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1565 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1566 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1567 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1569 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1572 local_irq_save(flags);
1573 disable_local_APIC();
1574 local_irq_restore(flags);
1578 static int lapic_resume(struct sys_device *dev)
1581 unsigned long flags;
1584 if (!apic_pm_state.active)
1587 maxlvt = lapic_get_maxlvt();
1589 local_irq_save(flags);
1591 #ifdef CONFIG_X86_64
1598 * Make sure the APICBASE points to the right address
1600 * FIXME! This will be wrong if we ever support suspend on
1601 * SMP! We'll need to do this as part of the CPU restore!
1603 rdmsr(MSR_IA32_APICBASE, l, h);
1604 l &= ~MSR_IA32_APICBASE_BASE;
1605 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1606 wrmsr(MSR_IA32_APICBASE, l, h);
1609 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1610 apic_write(APIC_ID, apic_pm_state.apic_id);
1611 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1612 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1613 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1614 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1615 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1616 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1617 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1619 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1622 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1623 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1624 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1625 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1626 apic_write(APIC_ESR, 0);
1627 apic_read(APIC_ESR);
1628 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1629 apic_write(APIC_ESR, 0);
1630 apic_read(APIC_ESR);
1632 local_irq_restore(flags);
1638 * This device has no shutdown method - fully functioning local APICs
1639 * are needed on every CPU up until machine_halt/restart/poweroff.
1642 static struct sysdev_class lapic_sysclass = {
1644 .resume = lapic_resume,
1645 .suspend = lapic_suspend,
1648 static struct sys_device device_lapic = {
1650 .cls = &lapic_sysclass,
1653 static void __cpuinit apic_pm_activate(void)
1655 apic_pm_state.active = 1;
1658 static int __init init_lapic_sysfs(void)
1664 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1666 error = sysdev_class_register(&lapic_sysclass);
1668 error = sysdev_register(&device_lapic);
1671 device_initcall(init_lapic_sysfs);
1673 #else /* CONFIG_PM */
1675 static void apic_pm_activate(void) { }
1677 #endif /* CONFIG_PM */
1680 * apic_is_clustered_box() -- Check if we can expect good TSC
1682 * Thus far, the major user of this is IBM's Summit2 series:
1684 * Clustered boxes may have unsynced TSC problems if they are
1685 * multi-chassis. Use available data to take a good guess.
1686 * If in doubt, go HPET.
1688 __cpuinit int apic_is_clustered_box(void)
1690 int i, clusters, zeros;
1692 u16 *bios_cpu_apicid;
1693 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1696 * there is not this kind of box with AMD CPU yet.
1697 * Some AMD box with quadcore cpu and 8 sockets apicid
1698 * will be [4, 0x23] or [8, 0x27] could be thought to
1699 * vsmp box still need checking...
1701 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1704 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1705 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1707 for (i = 0; i < NR_CPUS; i++) {
1708 /* are we being called early in kernel startup? */
1709 if (bios_cpu_apicid) {
1710 id = bios_cpu_apicid[i];
1712 else if (i < nr_cpu_ids) {
1714 id = per_cpu(x86_bios_cpu_apicid, i);
1721 if (id != BAD_APICID)
1722 __set_bit(APIC_CLUSTERID(id), clustermap);
1725 /* Problem: Partially populated chassis may not have CPUs in some of
1726 * the APIC clusters they have been allocated. Only present CPUs have
1727 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1728 * Since clusters are allocated sequentially, count zeros only if
1729 * they are bounded by ones.
1733 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1734 if (test_bit(i, clustermap)) {
1735 clusters += 1 + zeros;
1741 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1742 * not guaranteed to be synced between boards
1744 if (is_vsmp_box() && clusters > 1)
1748 * If clusters > 2, then should be multi-chassis.
1749 * May have to revisit this when multi-core + hyperthreaded CPUs come
1750 * out, but AFAIK this will work even for them.
1752 return (clusters > 2);
1755 static __init int setup_nox2apic(char *str)
1758 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1761 early_param("nox2apic", setup_nox2apic);
1765 * APIC command line parameters
1767 static int __init setup_disableapic(char *arg)
1770 setup_clear_cpu_cap(X86_FEATURE_APIC);
1773 early_param("disableapic", setup_disableapic);
1775 /* same as disableapic, for compatibility */
1776 static int __init setup_nolapic(char *arg)
1778 return setup_disableapic(arg);
1780 early_param("nolapic", setup_nolapic);
1782 static int __init parse_lapic_timer_c2_ok(char *arg)
1784 local_apic_timer_c2_ok = 1;
1787 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1789 static int __init parse_disable_apic_timer(char *arg)
1791 disable_apic_timer = 1;
1794 early_param("noapictimer", parse_disable_apic_timer);
1796 static int __init parse_nolapic_timer(char *arg)
1798 disable_apic_timer = 1;
1801 early_param("nolapic_timer", parse_nolapic_timer);
1803 static __init int setup_apicpmtimer(char *s)
1805 apic_calibrate_pmtmr = 1;
1809 __setup("apicpmtimer", setup_apicpmtimer);
1811 static int __init apic_set_verbosity(char *arg)
1814 #ifdef CONFIG_X86_64
1815 skip_ioapic_setup = 0;
1822 if (strcmp("debug", arg) == 0)
1823 apic_verbosity = APIC_DEBUG;
1824 else if (strcmp("verbose", arg) == 0)
1825 apic_verbosity = APIC_VERBOSE;
1827 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1828 " use apic=verbose or apic=debug\n", arg);
1834 early_param("apic", apic_set_verbosity);
1836 static int __init lapic_insert_resource(void)
1841 /* Put local APIC into the resource map. */
1842 lapic_resource.start = apic_phys;
1843 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1844 insert_resource(&iomem_resource, &lapic_resource);
1850 * need call insert after e820_reserve_resources()
1851 * that is using request_resource
1853 late_initcall(lapic_insert_resource);