2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
52 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
53 # error SPURIOUS_APIC_VECTOR definition error
56 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
57 static int disable_apic_timer __cpuinitdata;
58 static int apic_calibrate_pmtmr __initdata;
63 /* x2apic enabled before OS handover */
64 int x2apic_preenabled;
66 /* Local APIC timer works in C2 */
67 int local_apic_timer_c2_ok;
68 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
70 int first_system_vector = 0xfe;
72 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
75 * Debug level, exported for io_apic.c
77 unsigned int apic_verbosity;
79 /* Have we found an MP table */
82 static struct resource lapic_resource = {
84 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
87 static unsigned int calibration_result;
89 static int lapic_next_event(unsigned long delta,
90 struct clock_event_device *evt);
91 static void lapic_timer_setup(enum clock_event_mode mode,
92 struct clock_event_device *evt);
93 static void lapic_timer_broadcast(cpumask_t mask);
94 static void apic_pm_activate(void);
97 * The local apic timer can be used for any function which is CPU local.
99 static struct clock_event_device lapic_clockevent = {
101 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
102 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
104 .set_mode = lapic_timer_setup,
105 .set_next_event = lapic_next_event,
106 .broadcast = lapic_timer_broadcast,
110 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
112 static unsigned long apic_phys;
114 unsigned long mp_lapic_addr;
117 * Get the LAPIC version
119 static inline int lapic_get_version(void)
121 return GET_APIC_VERSION(apic_read(APIC_LVR));
125 * Check, if the APIC is integrated or a separate chip
127 static inline int lapic_is_integrated(void)
132 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
143 boot_cpu_data.x86 >= 0xf)
145 return lapic_get_version() >= 0x14;
149 * Paravirt kernels also might be using these below ops. So we still
150 * use generic apic_read()/apic_write(), which might be pointing to different
151 * ops in PARAVIRT case.
153 void xapic_wait_icr_idle(void)
155 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
159 u32 safe_xapic_wait_icr_idle(void)
166 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
170 } while (timeout++ < 1000);
175 void xapic_icr_write(u32 low, u32 id)
177 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
178 apic_write(APIC_ICR, low);
181 u64 xapic_icr_read(void)
185 icr2 = apic_read(APIC_ICR2);
186 icr1 = apic_read(APIC_ICR);
188 return icr1 | ((u64)icr2 << 32);
191 static struct apic_ops xapic_ops = {
192 .read = native_apic_mem_read,
193 .write = native_apic_mem_write,
194 .icr_read = xapic_icr_read,
195 .icr_write = xapic_icr_write,
196 .wait_icr_idle = xapic_wait_icr_idle,
197 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
200 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
201 EXPORT_SYMBOL_GPL(apic_ops);
203 static void x2apic_wait_icr_idle(void)
205 /* no need to wait for icr idle in x2apic */
209 static u32 safe_x2apic_wait_icr_idle(void)
211 /* no need to wait for icr idle in x2apic */
215 void x2apic_icr_write(u32 low, u32 id)
217 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
220 u64 x2apic_icr_read(void)
224 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
228 static struct apic_ops x2apic_ops = {
229 .read = native_apic_msr_read,
230 .write = native_apic_msr_write,
231 .icr_read = x2apic_icr_read,
232 .icr_write = x2apic_icr_write,
233 .wait_icr_idle = x2apic_wait_icr_idle,
234 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
238 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
240 void __cpuinit enable_NMI_through_LVT0(void)
244 /* unmask and set to NMI */
247 /* Level triggered for 82489DX (32bit mode) */
248 if (!lapic_is_integrated())
249 v |= APIC_LVT_LEVEL_TRIGGER;
251 apic_write(APIC_LVT0, v);
256 * get_physical_broadcast - Get number of physical broadcast IDs
258 int get_physical_broadcast(void)
260 return modern_apic() ? 0xff : 0xf;
265 * lapic_get_maxlvt - get the maximum number of local vector table entries
267 int lapic_get_maxlvt(void)
271 v = apic_read(APIC_LVR);
273 * - we always have APIC integrated on 64bit mode
274 * - 82489DXs do not report # of LVT entries
276 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
285 #define APIC_DIVISOR 1
287 #define APIC_DIVISOR 16
291 * This function sets up the local APIC timer, with a timeout of
292 * 'clocks' APIC bus clock. During calibration we actually call
293 * this function twice on the boot CPU, once with a bogus timeout
294 * value, second time for real. The other (noncalibrating) CPUs
295 * call this function only once, with the real, calibrated value.
297 * We do reads before writes even if unnecessary, to get around the
298 * P5 APIC double write bug.
300 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
302 unsigned int lvtt_value, tmp_value;
304 lvtt_value = LOCAL_TIMER_VECTOR;
306 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
307 if (!lapic_is_integrated())
308 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
311 lvtt_value |= APIC_LVT_MASKED;
313 apic_write(APIC_LVTT, lvtt_value);
318 tmp_value = apic_read(APIC_TDCR);
319 apic_write(APIC_TDCR,
320 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
324 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
328 * Setup extended LVT, AMD specific (K8, family 10h)
330 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
331 * MCE interrupts are supported. Thus MCE offset must be set to 0.
333 * If mask=1, the LVT entry does not generate interrupts while mask=0
334 * enables the vector. See also the BKDGs.
337 #define APIC_EILVT_LVTOFF_MCE 0
338 #define APIC_EILVT_LVTOFF_IBS 1
340 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
342 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
343 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
348 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
350 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
351 return APIC_EILVT_LVTOFF_MCE;
354 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
356 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
357 return APIC_EILVT_LVTOFF_IBS;
359 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
362 * Program the next event, relative to now
364 static int lapic_next_event(unsigned long delta,
365 struct clock_event_device *evt)
367 apic_write(APIC_TMICT, delta);
372 * Setup the lapic timer in periodic or oneshot mode
374 static void lapic_timer_setup(enum clock_event_mode mode,
375 struct clock_event_device *evt)
380 /* Lapic used as dummy for broadcast ? */
381 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
384 local_irq_save(flags);
387 case CLOCK_EVT_MODE_PERIODIC:
388 case CLOCK_EVT_MODE_ONESHOT:
389 __setup_APIC_LVTT(calibration_result,
390 mode != CLOCK_EVT_MODE_PERIODIC, 1);
392 case CLOCK_EVT_MODE_UNUSED:
393 case CLOCK_EVT_MODE_SHUTDOWN:
394 v = apic_read(APIC_LVTT);
395 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
396 apic_write(APIC_LVTT, v);
398 case CLOCK_EVT_MODE_RESUME:
399 /* Nothing to do here */
403 local_irq_restore(flags);
407 * Local APIC timer broadcast function
409 static void lapic_timer_broadcast(cpumask_t mask)
412 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
417 * Setup the local APIC timer for this CPU. Copy the initilized values
418 * of the boot CPU and register the clock event in the framework.
420 static void __cpuinit setup_APIC_timer(void)
422 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
424 memcpy(levt, &lapic_clockevent, sizeof(*levt));
425 levt->cpumask = cpumask_of_cpu(smp_processor_id());
427 clockevents_register_device(levt);
431 * In this function we calibrate APIC bus clocks to the external
432 * timer. Unfortunately we cannot use jiffies and the timer irq
433 * to calibrate, since some later bootup code depends on getting
434 * the first irq? Ugh.
436 * We want to do the calibration only once since we
437 * want to have local timer irqs syncron. CPUs connected
438 * by the same APIC bus have the very same bus frequency.
439 * And we want to have irqs off anyways, no accidental
443 #define TICK_COUNT 100000000
445 static int __init calibrate_APIC_clock(void)
447 unsigned apic, apic_start;
448 unsigned long tsc, tsc_start;
454 * Put whatever arbitrary (but long enough) timeout
455 * value into the APIC clock, we just want to get the
456 * counter running for calibration.
458 * No interrupt enable !
460 __setup_APIC_LVTT(250000000, 0, 0);
462 apic_start = apic_read(APIC_TMCCT);
463 #ifdef CONFIG_X86_PM_TIMER
464 if (apic_calibrate_pmtmr && pmtmr_ioport) {
465 pmtimer_wait(5000); /* 5ms wait */
466 apic = apic_read(APIC_TMCCT);
467 result = (apic_start - apic) * 1000L / 5;
474 apic = apic_read(APIC_TMCCT);
476 } while ((tsc - tsc_start) < TICK_COUNT &&
477 (apic_start - apic) < TICK_COUNT);
479 result = (apic_start - apic) * 1000L * tsc_khz /
485 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
487 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
488 result / 1000 / 1000, result / 1000 % 1000);
490 /* Calculate the scaled math multiplication factor */
491 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
492 lapic_clockevent.shift);
493 lapic_clockevent.max_delta_ns =
494 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
495 lapic_clockevent.min_delta_ns =
496 clockevent_delta2ns(0xF, &lapic_clockevent);
498 calibration_result = (result * APIC_DIVISOR) / HZ;
501 * Do a sanity check on the APIC calibration result
503 if (calibration_result < (1000000 / HZ)) {
505 "APIC frequency too slow, disabling apic timer\n");
513 * Setup the boot APIC
515 * Calibrate and verify the result.
517 void __init setup_boot_APIC_clock(void)
520 * The local apic timer can be disabled via the kernel
521 * commandline or from the CPU detection code. Register the lapic
522 * timer as a dummy clock event source on SMP systems, so the
523 * broadcast mechanism is used. On UP systems simply ignore it.
525 if (disable_apic_timer) {
526 printk(KERN_INFO "Disabling APIC timer\n");
527 /* No broadcast on UP ! */
528 if (num_possible_cpus() > 1) {
529 lapic_clockevent.mult = 1;
535 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
536 "calibrating APIC timer ...\n");
538 if (calibrate_APIC_clock()) {
539 /* No broadcast on UP ! */
540 if (num_possible_cpus() > 1)
546 * If nmi_watchdog is set to IO_APIC, we need the
547 * PIT/HPET going. Otherwise register lapic as a dummy
550 if (nmi_watchdog != NMI_IO_APIC)
551 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
553 printk(KERN_WARNING "APIC timer registered as dummy,"
554 " due to nmi_watchdog=%d!\n", nmi_watchdog);
556 /* Setup the lapic or request the broadcast */
560 void __cpuinit setup_secondary_APIC_clock(void)
566 * The guts of the apic timer interrupt
568 static void local_apic_timer_interrupt(void)
570 int cpu = smp_processor_id();
571 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
574 * Normally we should not be here till LAPIC has been initialized but
575 * in some cases like kdump, its possible that there is a pending LAPIC
576 * timer interrupt from previous kernel's context and is delivered in
577 * new kernel the moment interrupts are enabled.
579 * Interrupts are enabled early and LAPIC is setup much later, hence
580 * its possible that when we get here evt->event_handler is NULL.
581 * Check for event_handler being NULL and discard the interrupt as
584 if (!evt->event_handler) {
586 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
588 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
593 * the NMI deadlock-detector uses this.
596 add_pda(apic_timer_irqs, 1);
598 per_cpu(irq_stat, cpu).apic_timer_irqs++;
601 evt->event_handler(evt);
605 * Local APIC timer interrupt. This is the most natural way for doing
606 * local interrupts, but local timer interrupts can be emulated by
607 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
609 * [ if a single-CPU system runs an SMP kernel then we call the local
610 * interrupt as well. Thus we cannot inline the local irq ... ]
612 void smp_apic_timer_interrupt(struct pt_regs *regs)
614 struct pt_regs *old_regs = set_irq_regs(regs);
617 * NOTE! We'd better ACK the irq immediately,
618 * because timer handling can be slow.
622 * update_process_times() expects us to have done irq_enter().
623 * Besides, if we don't timer interrupts ignore the global
624 * interrupt lock, which is the WrongThing (tm) to do.
628 local_apic_timer_interrupt();
631 set_irq_regs(old_regs);
634 int setup_profiling_timer(unsigned int multiplier)
641 * Local APIC start and shutdown
645 * clear_local_APIC - shutdown the local APIC
647 * This is called, when a CPU is disabled and before rebooting, so the state of
648 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
649 * leftovers during boot.
651 void clear_local_APIC(void)
656 /* APIC hasn't been mapped yet */
660 maxlvt = lapic_get_maxlvt();
662 * Masking an LVT entry can trigger a local APIC error
663 * if the vector is zero. Mask LVTERR first to prevent this.
666 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
667 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
670 * Careful: we have to set masks only first to deassert
671 * any level-triggered sources.
673 v = apic_read(APIC_LVTT);
674 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
675 v = apic_read(APIC_LVT0);
676 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
677 v = apic_read(APIC_LVT1);
678 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
680 v = apic_read(APIC_LVTPC);
681 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
684 /* lets not touch this if we didn't frob it */
685 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
687 v = apic_read(APIC_LVTTHMR);
688 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
692 * Clean APIC state for other OSs:
694 apic_write(APIC_LVTT, APIC_LVT_MASKED);
695 apic_write(APIC_LVT0, APIC_LVT_MASKED);
696 apic_write(APIC_LVT1, APIC_LVT_MASKED);
698 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
700 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
702 /* Integrated APIC (!82489DX) ? */
703 if (lapic_is_integrated()) {
705 /* Clear ESR due to Pentium errata 3AP and 11AP */
706 apic_write(APIC_ESR, 0);
712 * disable_local_APIC - clear and disable the local APIC
714 void disable_local_APIC(void)
721 * Disable APIC (implies clearing of registers
724 value = apic_read(APIC_SPIV);
725 value &= ~APIC_SPIV_APIC_ENABLED;
726 apic_write(APIC_SPIV, value);
730 * When LAPIC was disabled by the BIOS and enabled by the kernel,
731 * restore the disabled state.
733 if (enabled_via_apicbase) {
736 rdmsr(MSR_IA32_APICBASE, l, h);
737 l &= ~MSR_IA32_APICBASE_ENABLE;
738 wrmsr(MSR_IA32_APICBASE, l, h);
744 * If Linux enabled the LAPIC against the BIOS default disable it down before
745 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
746 * not power-off. Additionally clear all LVT entries before disable_local_APIC
747 * for the case where Linux didn't enable the LAPIC.
749 void lapic_shutdown(void)
756 local_irq_save(flags);
759 if (!enabled_via_apicbase)
763 disable_local_APIC();
766 local_irq_restore(flags);
770 * This is to verify that we're looking at a real local APIC.
771 * Check these against your board if the CPUs aren't getting
772 * started for no apparent reason.
774 int __init verify_local_APIC(void)
776 unsigned int reg0, reg1;
779 * The version register is read-only in a real APIC.
781 reg0 = apic_read(APIC_LVR);
782 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
783 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
784 reg1 = apic_read(APIC_LVR);
785 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
788 * The two version reads above should print the same
789 * numbers. If the second one is different, then we
790 * poke at a non-APIC.
796 * Check if the version looks reasonably.
798 reg1 = GET_APIC_VERSION(reg0);
799 if (reg1 == 0x00 || reg1 == 0xff)
801 reg1 = lapic_get_maxlvt();
802 if (reg1 < 0x02 || reg1 == 0xff)
806 * The ID register is read/write in a real APIC.
808 reg0 = apic_read(APIC_ID);
809 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
810 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
811 reg1 = apic_read(APIC_ID);
812 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
813 apic_write(APIC_ID, reg0);
814 if (reg1 != (reg0 ^ APIC_ID_MASK))
818 * The next two are just to see if we have sane values.
819 * They're only really relevant if we're in Virtual Wire
820 * compatibility mode, but most boxes are anymore.
822 reg0 = apic_read(APIC_LVT0);
823 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
824 reg1 = apic_read(APIC_LVT1);
825 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
831 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
833 void __init sync_Arb_IDs(void)
836 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
839 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
845 apic_wait_icr_idle();
847 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
848 apic_write(APIC_ICR, APIC_DEST_ALLINC |
849 APIC_INT_LEVELTRIG | APIC_DM_INIT);
853 * An initial setup of the virtual wire mode.
855 void __init init_bsp_APIC(void)
860 * Don't do the setup now if we have a SMP BIOS as the
861 * through-I/O-APIC virtual wire mode might be active.
863 if (smp_found_config || !cpu_has_apic)
867 * Do not trust the local APIC being empty at bootup.
874 value = apic_read(APIC_SPIV);
875 value &= ~APIC_VECTOR_MASK;
876 value |= APIC_SPIV_APIC_ENABLED;
879 /* This bit is reserved on P4/Xeon and should be cleared */
880 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
881 (boot_cpu_data.x86 == 15))
882 value &= ~APIC_SPIV_FOCUS_DISABLED;
885 value |= APIC_SPIV_FOCUS_DISABLED;
886 value |= SPURIOUS_APIC_VECTOR;
887 apic_write(APIC_SPIV, value);
890 * Set up the virtual wire mode.
892 apic_write(APIC_LVT0, APIC_DM_EXTINT);
894 if (!lapic_is_integrated()) /* 82489DX */
895 value |= APIC_LVT_LEVEL_TRIGGER;
896 apic_write(APIC_LVT1, value);
899 static void __cpuinit lapic_setup_esr(void)
901 unsigned long oldvalue, value, maxlvt;
902 if (lapic_is_integrated() && !esr_disable) {
905 * Something untraceable is creating bad interrupts on
906 * secondary quads ... for the moment, just leave the
907 * ESR disabled - we can't do anything useful with the
908 * errors anyway - mbligh
910 printk(KERN_INFO "Leaving ESR disabled.\n");
914 maxlvt = lapic_get_maxlvt();
915 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
916 apic_write(APIC_ESR, 0);
917 oldvalue = apic_read(APIC_ESR);
919 /* enables sending errors */
920 value = ERROR_APIC_VECTOR;
921 apic_write(APIC_LVTERR, value);
923 * spec says clear errors after enabling vector.
926 apic_write(APIC_ESR, 0);
927 value = apic_read(APIC_ESR);
928 if (value != oldvalue)
929 apic_printk(APIC_VERBOSE, "ESR value before enabling "
930 "vector: 0x%08lx after: 0x%08lx\n",
933 printk(KERN_INFO "No ESR for 82489DX.\n");
939 * setup_local_APIC - setup the local APIC
941 void __cpuinit setup_local_APIC(void)
947 value = apic_read(APIC_LVR);
950 * Double-check whether this APIC is really registered.
951 * This is meaningless in clustered apic mode, so we skip it.
953 if (!apic_id_registered())
957 * Intel recommends to set DFR, LDR and TPR before enabling
958 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
959 * document number 292116). So here it goes...
964 * Set Task Priority to 'accept all'. We never change this
967 value = apic_read(APIC_TASKPRI);
968 value &= ~APIC_TPRI_MASK;
969 apic_write(APIC_TASKPRI, value);
972 * After a crash, we no longer service the interrupts and a pending
973 * interrupt from previous kernel might still have ISR bit set.
975 * Most probably by now CPU has serviced that pending interrupt and
976 * it might not have done the ack_APIC_irq() because it thought,
977 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
978 * does not clear the ISR bit and cpu thinks it has already serivced
979 * the interrupt. Hence a vector might get locked. It was noticed
980 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
982 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
983 value = apic_read(APIC_ISR + i*0x10);
984 for (j = 31; j >= 0; j--) {
991 * Now that we are all set up, enable the APIC
993 value = apic_read(APIC_SPIV);
994 value &= ~APIC_VECTOR_MASK;
998 value |= APIC_SPIV_APIC_ENABLED;
1000 /* We always use processor focus */
1003 * Set spurious IRQ vector
1005 value |= SPURIOUS_APIC_VECTOR;
1006 apic_write(APIC_SPIV, value);
1009 * Set up LVT0, LVT1:
1011 * set up through-local-APIC on the BP's LINT0. This is not
1012 * strictly necessary in pure symmetric-IO mode, but sometimes
1013 * we delegate interrupts to the 8259A.
1016 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1018 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1019 if (!smp_processor_id() && !value) {
1020 value = APIC_DM_EXTINT;
1021 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1022 smp_processor_id());
1024 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1025 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1026 smp_processor_id());
1028 apic_write(APIC_LVT0, value);
1031 * only the BP should see the LINT1 NMI signal, obviously.
1033 if (!smp_processor_id())
1034 value = APIC_DM_NMI;
1036 value = APIC_DM_NMI | APIC_LVT_MASKED;
1037 apic_write(APIC_LVT1, value);
1041 void __cpuinit end_local_APIC_setup(void)
1045 #ifdef CONFIG_X86_32
1048 /* Disable the local apic timer */
1049 value = apic_read(APIC_LVTT);
1050 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1051 apic_write(APIC_LVTT, value);
1055 setup_apic_nmi_watchdog(NULL);
1059 void check_x2apic(void)
1063 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1065 if (msr & X2APIC_ENABLE) {
1066 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1067 x2apic_preenabled = x2apic = 1;
1068 apic_ops = &x2apic_ops;
1072 void enable_x2apic(void)
1076 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1077 if (!(msr & X2APIC_ENABLE)) {
1078 printk("Enabling x2apic\n");
1079 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1083 void enable_IR_x2apic(void)
1085 #ifdef CONFIG_INTR_REMAP
1087 unsigned long flags;
1089 if (!cpu_has_x2apic)
1092 if (!x2apic_preenabled && disable_x2apic) {
1094 "Skipped enabling x2apic and Interrupt-remapping "
1095 "because of nox2apic\n");
1099 if (x2apic_preenabled && disable_x2apic)
1100 panic("Bios already enabled x2apic, can't enforce nox2apic");
1102 if (!x2apic_preenabled && skip_ioapic_setup) {
1104 "Skipped enabling x2apic and Interrupt-remapping "
1105 "because of skipping io-apic setup\n");
1109 ret = dmar_table_init();
1112 "dmar_table_init() failed with %d:\n", ret);
1114 if (x2apic_preenabled)
1115 panic("x2apic enabled by bios. But IR enabling failed");
1118 "Not enabling x2apic,Intr-remapping\n");
1122 local_irq_save(flags);
1124 save_mask_IO_APIC_setup();
1126 ret = enable_intr_remapping(1);
1128 if (ret && x2apic_preenabled) {
1129 local_irq_restore(flags);
1130 panic("x2apic enabled by bios. But IR enabling failed");
1138 apic_ops = &x2apic_ops;
1144 * IR enabling failed
1146 restore_IO_APIC_setup();
1148 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1151 local_irq_restore(flags);
1154 if (!x2apic_preenabled)
1156 "Enabled x2apic and interrupt-remapping\n");
1159 "Enabled Interrupt-remapping\n");
1162 "Failed to enable Interrupt-remapping and x2apic\n");
1164 if (!cpu_has_x2apic)
1167 if (x2apic_preenabled)
1168 panic("x2apic enabled prior OS handover,"
1169 " enable CONFIG_INTR_REMAP");
1171 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1179 * Detect and enable local APICs on non-SMP boards.
1180 * Original code written by Keir Fraser.
1181 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1182 * not correctly set up (usually the APIC timer won't work etc.)
1184 static int __init detect_init_APIC(void)
1186 if (!cpu_has_apic) {
1187 printk(KERN_INFO "No local APIC present\n");
1191 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1192 boot_cpu_physical_apicid = 0;
1196 void __init early_init_lapic_mapping(void)
1198 unsigned long phys_addr;
1201 * If no local APIC can be found then go out
1202 * : it means there is no mpatable and MADT
1204 if (!smp_found_config)
1207 phys_addr = mp_lapic_addr;
1209 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1210 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1211 APIC_BASE, phys_addr);
1214 * Fetch the APIC ID of the BSP in case we have a
1215 * default configuration (or the MP table is broken).
1217 boot_cpu_physical_apicid = read_apic_id();
1221 * init_apic_mappings - initialize APIC mappings
1223 void __init init_apic_mappings(void)
1226 boot_cpu_physical_apicid = read_apic_id();
1231 * If no local APIC can be found then set up a fake all
1232 * zeroes page to simulate the local APIC and another
1233 * one for the IO-APIC.
1235 if (!smp_found_config && detect_init_APIC()) {
1236 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1237 apic_phys = __pa(apic_phys);
1239 apic_phys = mp_lapic_addr;
1241 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1242 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1243 APIC_BASE, apic_phys);
1246 * Fetch the APIC ID of the BSP in case we have a
1247 * default configuration (or the MP table is broken).
1249 boot_cpu_physical_apicid = read_apic_id();
1253 * This initializes the IO-APIC and APIC hardware if this is
1256 int apic_version[MAX_APICS];
1258 int __init APIC_init_uniprocessor(void)
1261 printk(KERN_INFO "Apic disabled\n");
1264 if (!cpu_has_apic) {
1266 printk(KERN_INFO "Apic disabled by BIOS\n");
1271 setup_apic_routing();
1273 verify_local_APIC();
1277 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1278 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1283 * Now enable IO-APICs, actually call clear_IO_APIC
1284 * We need clear_IO_APIC before enabling vector on BP
1286 if (!skip_ioapic_setup && nr_ioapics)
1289 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1290 localise_nmi_watchdog();
1291 end_local_APIC_setup();
1293 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1297 setup_boot_APIC_clock();
1298 check_nmi_watchdog();
1303 * Local APIC interrupts
1307 * This interrupt should _never_ happen with our APIC/SMP architecture
1309 asmlinkage void smp_spurious_interrupt(void)
1315 * Check if this really is a spurious interrupt and ACK it
1316 * if it is a vectored one. Just in case...
1317 * Spurious interrupts should not be ACKed.
1319 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1320 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1323 add_pda(irq_spurious_count, 1);
1328 * This interrupt should never happen with our APIC/SMP architecture
1330 asmlinkage void smp_error_interrupt(void)
1336 /* First tickle the hardware, only then report what went on. -- REW */
1337 v = apic_read(APIC_ESR);
1338 apic_write(APIC_ESR, 0);
1339 v1 = apic_read(APIC_ESR);
1341 atomic_inc(&irq_err_count);
1343 /* Here is what the APIC error bits mean:
1346 2: Send accept error
1347 3: Receive accept error
1349 5: Send illegal vector
1350 6: Received illegal vector
1351 7: Illegal register address
1353 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1354 smp_processor_id(), v , v1);
1359 * connect_bsp_APIC - attach the APIC to the interrupt system
1361 void __init connect_bsp_APIC(void)
1363 #ifdef CONFIG_X86_32
1366 * Do not trust the local APIC being empty at bootup.
1370 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1371 * local APIC to INT and NMI lines.
1373 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1374 "enabling APIC mode.\n");
1383 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1384 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1386 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1389 void disconnect_bsp_APIC(int virt_wire_setup)
1393 #ifdef CONFIG_X86_32
1396 * Put the board back into PIC mode (has an effect only on
1397 * certain older boards). Note that APIC interrupts, including
1398 * IPIs, won't work beyond this point! The only exception are
1401 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1402 "entering PIC mode.\n");
1409 /* Go back to Virtual Wire compatibility mode */
1411 /* For the spurious interrupt use vector F, and enable it */
1412 value = apic_read(APIC_SPIV);
1413 value &= ~APIC_VECTOR_MASK;
1414 value |= APIC_SPIV_APIC_ENABLED;
1416 apic_write(APIC_SPIV, value);
1418 if (!virt_wire_setup) {
1420 * For LVT0 make it edge triggered, active high,
1421 * external and enabled
1423 value = apic_read(APIC_LVT0);
1424 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1425 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1426 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1427 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1428 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1429 apic_write(APIC_LVT0, value);
1432 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1436 * For LVT1 make it edge triggered, active high,
1439 value = apic_read(APIC_LVT1);
1440 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1441 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1442 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1443 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1444 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1445 apic_write(APIC_LVT1, value);
1448 void __cpuinit generic_processor_info(int apicid, int version)
1456 if (version == 0x0) {
1457 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1458 "fixing up to 0x10. (tell your hw vendor)\n",
1462 apic_version[apicid] = version;
1464 if (num_processors >= NR_CPUS) {
1465 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1466 " Processor ignored.\n", NR_CPUS);
1471 cpus_complement(tmp_map, cpu_present_map);
1472 cpu = first_cpu(tmp_map);
1474 physid_set(apicid, phys_cpu_present_map);
1475 if (apicid == boot_cpu_physical_apicid) {
1477 * x86_bios_cpu_apicid is required to have processors listed
1478 * in same order as logical cpu numbers. Hence the first
1479 * entry is BSP, and so on.
1483 if (apicid > max_physical_apicid)
1484 max_physical_apicid = apicid;
1486 #ifdef CONFIG_X86_32
1488 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1489 * but we need to work other dependencies like SMP_SUSPEND etc
1490 * before this can be done without some confusion.
1491 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1492 * - Ashok Raj <ashok.raj@intel.com>
1494 if (max_physical_apicid >= 8) {
1495 switch (boot_cpu_data.x86_vendor) {
1496 case X86_VENDOR_INTEL:
1497 if (!APIC_XAPIC(version)) {
1501 /* If P4 and above fall through */
1502 case X86_VENDOR_AMD:
1508 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1509 /* are we being called early in kernel startup? */
1510 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1511 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1512 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1514 cpu_to_apicid[cpu] = apicid;
1515 bios_cpu_apicid[cpu] = apicid;
1517 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1518 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1522 cpu_set(cpu, cpu_possible_map);
1523 cpu_set(cpu, cpu_present_map);
1526 int hard_smp_processor_id(void)
1528 return read_apic_id();
1538 * 'active' is true if the local APIC was enabled by us and
1539 * not the BIOS; this signifies that we are also responsible
1540 * for disabling it before entering apm/acpi suspend
1543 /* r/w apic fields */
1544 unsigned int apic_id;
1545 unsigned int apic_taskpri;
1546 unsigned int apic_ldr;
1547 unsigned int apic_dfr;
1548 unsigned int apic_spiv;
1549 unsigned int apic_lvtt;
1550 unsigned int apic_lvtpc;
1551 unsigned int apic_lvt0;
1552 unsigned int apic_lvt1;
1553 unsigned int apic_lvterr;
1554 unsigned int apic_tmict;
1555 unsigned int apic_tdcr;
1556 unsigned int apic_thmr;
1559 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1561 unsigned long flags;
1564 if (!apic_pm_state.active)
1567 maxlvt = lapic_get_maxlvt();
1569 apic_pm_state.apic_id = apic_read(APIC_ID);
1570 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1571 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1572 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1573 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1574 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1576 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1577 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1578 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1579 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1580 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1581 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1582 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1584 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1587 local_irq_save(flags);
1588 disable_local_APIC();
1589 local_irq_restore(flags);
1593 static int lapic_resume(struct sys_device *dev)
1596 unsigned long flags;
1599 if (!apic_pm_state.active)
1602 maxlvt = lapic_get_maxlvt();
1604 local_irq_save(flags);
1606 #ifdef CONFIG_X86_64
1613 * Make sure the APICBASE points to the right address
1615 * FIXME! This will be wrong if we ever support suspend on
1616 * SMP! We'll need to do this as part of the CPU restore!
1618 rdmsr(MSR_IA32_APICBASE, l, h);
1619 l &= ~MSR_IA32_APICBASE_BASE;
1620 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1621 wrmsr(MSR_IA32_APICBASE, l, h);
1624 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1625 apic_write(APIC_ID, apic_pm_state.apic_id);
1626 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1627 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1628 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1629 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1630 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1631 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1632 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1634 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1637 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1638 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1639 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1640 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1641 apic_write(APIC_ESR, 0);
1642 apic_read(APIC_ESR);
1643 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1644 apic_write(APIC_ESR, 0);
1645 apic_read(APIC_ESR);
1647 local_irq_restore(flags);
1653 * This device has no shutdown method - fully functioning local APICs
1654 * are needed on every CPU up until machine_halt/restart/poweroff.
1657 static struct sysdev_class lapic_sysclass = {
1659 .resume = lapic_resume,
1660 .suspend = lapic_suspend,
1663 static struct sys_device device_lapic = {
1665 .cls = &lapic_sysclass,
1668 static void __cpuinit apic_pm_activate(void)
1670 apic_pm_state.active = 1;
1673 static int __init init_lapic_sysfs(void)
1679 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1681 error = sysdev_class_register(&lapic_sysclass);
1683 error = sysdev_register(&device_lapic);
1686 device_initcall(init_lapic_sysfs);
1688 #else /* CONFIG_PM */
1690 static void apic_pm_activate(void) { }
1692 #endif /* CONFIG_PM */
1695 * apic_is_clustered_box() -- Check if we can expect good TSC
1697 * Thus far, the major user of this is IBM's Summit2 series:
1699 * Clustered boxes may have unsynced TSC problems if they are
1700 * multi-chassis. Use available data to take a good guess.
1701 * If in doubt, go HPET.
1703 __cpuinit int apic_is_clustered_box(void)
1705 int i, clusters, zeros;
1707 u16 *bios_cpu_apicid;
1708 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1711 * there is not this kind of box with AMD CPU yet.
1712 * Some AMD box with quadcore cpu and 8 sockets apicid
1713 * will be [4, 0x23] or [8, 0x27] could be thought to
1714 * vsmp box still need checking...
1716 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1719 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1720 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1722 for (i = 0; i < NR_CPUS; i++) {
1723 /* are we being called early in kernel startup? */
1724 if (bios_cpu_apicid) {
1725 id = bios_cpu_apicid[i];
1727 else if (i < nr_cpu_ids) {
1729 id = per_cpu(x86_bios_cpu_apicid, i);
1736 if (id != BAD_APICID)
1737 __set_bit(APIC_CLUSTERID(id), clustermap);
1740 /* Problem: Partially populated chassis may not have CPUs in some of
1741 * the APIC clusters they have been allocated. Only present CPUs have
1742 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1743 * Since clusters are allocated sequentially, count zeros only if
1744 * they are bounded by ones.
1748 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1749 if (test_bit(i, clustermap)) {
1750 clusters += 1 + zeros;
1756 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1757 * not guaranteed to be synced between boards
1759 if (is_vsmp_box() && clusters > 1)
1763 * If clusters > 2, then should be multi-chassis.
1764 * May have to revisit this when multi-core + hyperthreaded CPUs come
1765 * out, but AFAIK this will work even for them.
1767 return (clusters > 2);
1770 static __init int setup_nox2apic(char *str)
1773 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1776 early_param("nox2apic", setup_nox2apic);
1780 * APIC command line parameters
1782 static int __init setup_disableapic(char *arg)
1785 setup_clear_cpu_cap(X86_FEATURE_APIC);
1788 early_param("disableapic", setup_disableapic);
1790 /* same as disableapic, for compatibility */
1791 static int __init setup_nolapic(char *arg)
1793 return setup_disableapic(arg);
1795 early_param("nolapic", setup_nolapic);
1797 static int __init parse_lapic_timer_c2_ok(char *arg)
1799 local_apic_timer_c2_ok = 1;
1802 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1804 static int __init parse_disable_apic_timer(char *arg)
1806 disable_apic_timer = 1;
1809 early_param("noapictimer", parse_disable_apic_timer);
1811 static int __init parse_nolapic_timer(char *arg)
1813 disable_apic_timer = 1;
1816 early_param("nolapic_timer", parse_nolapic_timer);
1818 #ifdef CONFIG_X86_64
1819 static __init int setup_apicpmtimer(char *s)
1821 apic_calibrate_pmtmr = 1;
1825 __setup("apicpmtimer", setup_apicpmtimer);
1828 static int __init apic_set_verbosity(char *arg)
1831 #ifdef CONFIG_X86_64
1832 skip_ioapic_setup = 0;
1838 if (strcmp("debug", arg) == 0)
1839 apic_verbosity = APIC_DEBUG;
1840 else if (strcmp("verbose", arg) == 0)
1841 apic_verbosity = APIC_VERBOSE;
1843 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1844 " use apic=verbose or apic=debug\n", arg);
1850 early_param("apic", apic_set_verbosity);
1852 static int __init lapic_insert_resource(void)
1857 /* Put local APIC into the resource map. */
1858 lapic_resource.start = apic_phys;
1859 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1860 insert_resource(&iomem_resource, &lapic_resource);
1866 * need call insert after e820_reserve_resources()
1867 * that is using request_resource
1869 late_initcall(lapic_insert_resource);