2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
38 #include <asm/pgalloc.h>
41 #include <asm/proto.h>
42 #include <asm/timex.h>
44 #include <asm/i8259.h>
47 #include <mach_apic.h>
52 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
53 # error SPURIOUS_APIC_VECTOR definition error
56 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
57 static int disable_apic_timer __cpuinitdata;
58 static int apic_calibrate_pmtmr __initdata;
63 /* x2apic enabled before OS handover */
64 int x2apic_preenabled;
66 /* Local APIC timer works in C2 */
67 int local_apic_timer_c2_ok;
68 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
70 int first_system_vector = 0xfe;
72 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
75 * Debug level, exported for io_apic.c
77 unsigned int apic_verbosity;
81 /* Have we found an MP table */
84 static struct resource lapic_resource = {
86 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
89 static unsigned int calibration_result;
91 static int lapic_next_event(unsigned long delta,
92 struct clock_event_device *evt);
93 static void lapic_timer_setup(enum clock_event_mode mode,
94 struct clock_event_device *evt);
95 static void lapic_timer_broadcast(cpumask_t mask);
96 static void apic_pm_activate(void);
99 * The local apic timer can be used for any function which is CPU local.
101 static struct clock_event_device lapic_clockevent = {
103 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
104 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
106 .set_mode = lapic_timer_setup,
107 .set_next_event = lapic_next_event,
108 .broadcast = lapic_timer_broadcast,
112 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
114 static unsigned long apic_phys;
116 unsigned long mp_lapic_addr;
119 * Get the LAPIC version
121 static inline int lapic_get_version(void)
123 return GET_APIC_VERSION(apic_read(APIC_LVR));
127 * Check, if the APIC is integrated or a separate chip
129 static inline int lapic_is_integrated(void)
134 return APIC_INTEGRATED(lapic_get_version());
139 * Check, whether this is a modern or a first generation APIC
141 static int modern_apic(void)
143 /* AMD systems use old APIC versions, so check the CPU */
144 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
145 boot_cpu_data.x86 >= 0xf)
147 return lapic_get_version() >= 0x14;
151 * Paravirt kernels also might be using these below ops. So we still
152 * use generic apic_read()/apic_write(), which might be pointing to different
153 * ops in PARAVIRT case.
155 void xapic_wait_icr_idle(void)
157 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
161 u32 safe_xapic_wait_icr_idle(void)
168 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
172 } while (timeout++ < 1000);
177 void xapic_icr_write(u32 low, u32 id)
179 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
180 apic_write(APIC_ICR, low);
183 u64 xapic_icr_read(void)
187 icr2 = apic_read(APIC_ICR2);
188 icr1 = apic_read(APIC_ICR);
190 return icr1 | ((u64)icr2 << 32);
193 static struct apic_ops xapic_ops = {
194 .read = native_apic_mem_read,
195 .write = native_apic_mem_write,
196 .icr_read = xapic_icr_read,
197 .icr_write = xapic_icr_write,
198 .wait_icr_idle = xapic_wait_icr_idle,
199 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
202 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
203 EXPORT_SYMBOL_GPL(apic_ops);
205 static void x2apic_wait_icr_idle(void)
207 /* no need to wait for icr idle in x2apic */
211 static u32 safe_x2apic_wait_icr_idle(void)
213 /* no need to wait for icr idle in x2apic */
217 void x2apic_icr_write(u32 low, u32 id)
219 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
222 u64 x2apic_icr_read(void)
226 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
230 static struct apic_ops x2apic_ops = {
231 .read = native_apic_msr_read,
232 .write = native_apic_msr_write,
233 .icr_read = x2apic_icr_read,
234 .icr_write = x2apic_icr_write,
235 .wait_icr_idle = x2apic_wait_icr_idle,
236 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
240 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
242 void __cpuinit enable_NMI_through_LVT0(void)
246 /* unmask and set to NMI */
249 /* Level triggered for 82489DX (32bit mode) */
250 if (!lapic_is_integrated())
251 v |= APIC_LVT_LEVEL_TRIGGER;
253 apic_write(APIC_LVT0, v);
258 * get_physical_broadcast - Get number of physical broadcast IDs
260 int get_physical_broadcast(void)
262 return modern_apic() ? 0xff : 0xf;
267 * lapic_get_maxlvt - get the maximum number of local vector table entries
269 int lapic_get_maxlvt(void)
273 v = apic_read(APIC_LVR);
275 * - we always have APIC integrated on 64bit mode
276 * - 82489DXs do not report # of LVT entries
278 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
287 #define APIC_DIVISOR 1
289 #define APIC_DIVISOR 16
293 * This function sets up the local APIC timer, with a timeout of
294 * 'clocks' APIC bus clock. During calibration we actually call
295 * this function twice on the boot CPU, once with a bogus timeout
296 * value, second time for real. The other (noncalibrating) CPUs
297 * call this function only once, with the real, calibrated value.
299 * We do reads before writes even if unnecessary, to get around the
300 * P5 APIC double write bug.
302 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
304 unsigned int lvtt_value, tmp_value;
306 lvtt_value = LOCAL_TIMER_VECTOR;
308 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
309 if (!lapic_is_integrated())
310 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
313 lvtt_value |= APIC_LVT_MASKED;
315 apic_write(APIC_LVTT, lvtt_value);
320 tmp_value = apic_read(APIC_TDCR);
321 apic_write(APIC_TDCR,
322 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
326 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
330 * Setup extended LVT, AMD specific (K8, family 10h)
332 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
333 * MCE interrupts are supported. Thus MCE offset must be set to 0.
335 * If mask=1, the LVT entry does not generate interrupts while mask=0
336 * enables the vector. See also the BKDGs.
339 #define APIC_EILVT_LVTOFF_MCE 0
340 #define APIC_EILVT_LVTOFF_IBS 1
342 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
344 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
345 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
350 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
352 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
353 return APIC_EILVT_LVTOFF_MCE;
356 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
358 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
359 return APIC_EILVT_LVTOFF_IBS;
361 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
364 * Program the next event, relative to now
366 static int lapic_next_event(unsigned long delta,
367 struct clock_event_device *evt)
369 apic_write(APIC_TMICT, delta);
374 * Setup the lapic timer in periodic or oneshot mode
376 static void lapic_timer_setup(enum clock_event_mode mode,
377 struct clock_event_device *evt)
382 /* Lapic used as dummy for broadcast ? */
383 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
386 local_irq_save(flags);
389 case CLOCK_EVT_MODE_PERIODIC:
390 case CLOCK_EVT_MODE_ONESHOT:
391 __setup_APIC_LVTT(calibration_result,
392 mode != CLOCK_EVT_MODE_PERIODIC, 1);
394 case CLOCK_EVT_MODE_UNUSED:
395 case CLOCK_EVT_MODE_SHUTDOWN:
396 v = apic_read(APIC_LVTT);
397 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
398 apic_write(APIC_LVTT, v);
400 case CLOCK_EVT_MODE_RESUME:
401 /* Nothing to do here */
405 local_irq_restore(flags);
409 * Local APIC timer broadcast function
411 static void lapic_timer_broadcast(cpumask_t mask)
414 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
419 * Setup the local APIC timer for this CPU. Copy the initilized values
420 * of the boot CPU and register the clock event in the framework.
422 static void __cpuinit setup_APIC_timer(void)
424 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
426 memcpy(levt, &lapic_clockevent, sizeof(*levt));
427 levt->cpumask = cpumask_of_cpu(smp_processor_id());
429 clockevents_register_device(levt);
433 * In this function we calibrate APIC bus clocks to the external
434 * timer. Unfortunately we cannot use jiffies and the timer irq
435 * to calibrate, since some later bootup code depends on getting
436 * the first irq? Ugh.
438 * We want to do the calibration only once since we
439 * want to have local timer irqs syncron. CPUs connected
440 * by the same APIC bus have the very same bus frequency.
441 * And we want to have irqs off anyways, no accidental
445 #define TICK_COUNT 100000000
447 static int __init calibrate_APIC_clock(void)
449 unsigned apic, apic_start;
450 unsigned long tsc, tsc_start;
456 * Put whatever arbitrary (but long enough) timeout
457 * value into the APIC clock, we just want to get the
458 * counter running for calibration.
460 * No interrupt enable !
462 __setup_APIC_LVTT(250000000, 0, 0);
464 apic_start = apic_read(APIC_TMCCT);
465 #ifdef CONFIG_X86_PM_TIMER
466 if (apic_calibrate_pmtmr && pmtmr_ioport) {
467 pmtimer_wait(5000); /* 5ms wait */
468 apic = apic_read(APIC_TMCCT);
469 result = (apic_start - apic) * 1000L / 5;
476 apic = apic_read(APIC_TMCCT);
478 } while ((tsc - tsc_start) < TICK_COUNT &&
479 (apic_start - apic) < TICK_COUNT);
481 result = (apic_start - apic) * 1000L * tsc_khz /
487 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
489 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
490 result / 1000 / 1000, result / 1000 % 1000);
492 /* Calculate the scaled math multiplication factor */
493 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
494 lapic_clockevent.shift);
495 lapic_clockevent.max_delta_ns =
496 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
497 lapic_clockevent.min_delta_ns =
498 clockevent_delta2ns(0xF, &lapic_clockevent);
500 calibration_result = (result * APIC_DIVISOR) / HZ;
503 * Do a sanity check on the APIC calibration result
505 if (calibration_result < (1000000 / HZ)) {
507 "APIC frequency too slow, disabling apic timer\n");
515 * Setup the boot APIC
517 * Calibrate and verify the result.
519 void __init setup_boot_APIC_clock(void)
522 * The local apic timer can be disabled via the kernel
523 * commandline or from the CPU detection code. Register the lapic
524 * timer as a dummy clock event source on SMP systems, so the
525 * broadcast mechanism is used. On UP systems simply ignore it.
527 if (disable_apic_timer) {
528 printk(KERN_INFO "Disabling APIC timer\n");
529 /* No broadcast on UP ! */
530 if (num_possible_cpus() > 1) {
531 lapic_clockevent.mult = 1;
537 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
538 "calibrating APIC timer ...\n");
540 if (calibrate_APIC_clock()) {
541 /* No broadcast on UP ! */
542 if (num_possible_cpus() > 1)
548 * If nmi_watchdog is set to IO_APIC, we need the
549 * PIT/HPET going. Otherwise register lapic as a dummy
552 if (nmi_watchdog != NMI_IO_APIC)
553 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
555 printk(KERN_WARNING "APIC timer registered as dummy,"
556 " due to nmi_watchdog=%d!\n", nmi_watchdog);
558 /* Setup the lapic or request the broadcast */
562 void __cpuinit setup_secondary_APIC_clock(void)
568 * The guts of the apic timer interrupt
570 static void local_apic_timer_interrupt(void)
572 int cpu = smp_processor_id();
573 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
576 * Normally we should not be here till LAPIC has been initialized but
577 * in some cases like kdump, its possible that there is a pending LAPIC
578 * timer interrupt from previous kernel's context and is delivered in
579 * new kernel the moment interrupts are enabled.
581 * Interrupts are enabled early and LAPIC is setup much later, hence
582 * its possible that when we get here evt->event_handler is NULL.
583 * Check for event_handler being NULL and discard the interrupt as
586 if (!evt->event_handler) {
588 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
590 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
595 * the NMI deadlock-detector uses this.
598 add_pda(apic_timer_irqs, 1);
600 per_cpu(irq_stat, cpu).apic_timer_irqs++;
603 evt->event_handler(evt);
607 * Local APIC timer interrupt. This is the most natural way for doing
608 * local interrupts, but local timer interrupts can be emulated by
609 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
611 * [ if a single-CPU system runs an SMP kernel then we call the local
612 * interrupt as well. Thus we cannot inline the local irq ... ]
614 void smp_apic_timer_interrupt(struct pt_regs *regs)
616 struct pt_regs *old_regs = set_irq_regs(regs);
619 * NOTE! We'd better ACK the irq immediately,
620 * because timer handling can be slow.
624 * update_process_times() expects us to have done irq_enter().
625 * Besides, if we don't timer interrupts ignore the global
626 * interrupt lock, which is the WrongThing (tm) to do.
630 local_apic_timer_interrupt();
633 set_irq_regs(old_regs);
636 int setup_profiling_timer(unsigned int multiplier)
643 * Local APIC start and shutdown
647 * clear_local_APIC - shutdown the local APIC
649 * This is called, when a CPU is disabled and before rebooting, so the state of
650 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
651 * leftovers during boot.
653 void clear_local_APIC(void)
658 /* APIC hasn't been mapped yet */
662 maxlvt = lapic_get_maxlvt();
664 * Masking an LVT entry can trigger a local APIC error
665 * if the vector is zero. Mask LVTERR first to prevent this.
668 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
669 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
672 * Careful: we have to set masks only first to deassert
673 * any level-triggered sources.
675 v = apic_read(APIC_LVTT);
676 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
677 v = apic_read(APIC_LVT0);
678 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
679 v = apic_read(APIC_LVT1);
680 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
682 v = apic_read(APIC_LVTPC);
683 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
686 /* lets not touch this if we didn't frob it */
687 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
689 v = apic_read(APIC_LVTTHMR);
690 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
694 * Clean APIC state for other OSs:
696 apic_write(APIC_LVTT, APIC_LVT_MASKED);
697 apic_write(APIC_LVT0, APIC_LVT_MASKED);
698 apic_write(APIC_LVT1, APIC_LVT_MASKED);
700 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
702 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
704 /* Integrated APIC (!82489DX) ? */
705 if (lapic_is_integrated()) {
707 /* Clear ESR due to Pentium errata 3AP and 11AP */
708 apic_write(APIC_ESR, 0);
714 * disable_local_APIC - clear and disable the local APIC
716 void disable_local_APIC(void)
723 * Disable APIC (implies clearing of registers
726 value = apic_read(APIC_SPIV);
727 value &= ~APIC_SPIV_APIC_ENABLED;
728 apic_write(APIC_SPIV, value);
732 * When LAPIC was disabled by the BIOS and enabled by the kernel,
733 * restore the disabled state.
735 if (enabled_via_apicbase) {
738 rdmsr(MSR_IA32_APICBASE, l, h);
739 l &= ~MSR_IA32_APICBASE_ENABLE;
740 wrmsr(MSR_IA32_APICBASE, l, h);
746 * If Linux enabled the LAPIC against the BIOS default disable it down before
747 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
748 * not power-off. Additionally clear all LVT entries before disable_local_APIC
749 * for the case where Linux didn't enable the LAPIC.
751 void lapic_shutdown(void)
758 local_irq_save(flags);
761 if (!enabled_via_apicbase)
765 disable_local_APIC();
768 local_irq_restore(flags);
772 * This is to verify that we're looking at a real local APIC.
773 * Check these against your board if the CPUs aren't getting
774 * started for no apparent reason.
776 int __init verify_local_APIC(void)
778 unsigned int reg0, reg1;
781 * The version register is read-only in a real APIC.
783 reg0 = apic_read(APIC_LVR);
784 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
785 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
786 reg1 = apic_read(APIC_LVR);
787 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
790 * The two version reads above should print the same
791 * numbers. If the second one is different, then we
792 * poke at a non-APIC.
798 * Check if the version looks reasonably.
800 reg1 = GET_APIC_VERSION(reg0);
801 if (reg1 == 0x00 || reg1 == 0xff)
803 reg1 = lapic_get_maxlvt();
804 if (reg1 < 0x02 || reg1 == 0xff)
808 * The ID register is read/write in a real APIC.
810 reg0 = apic_read(APIC_ID);
811 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
812 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
813 reg1 = apic_read(APIC_ID);
814 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
815 apic_write(APIC_ID, reg0);
816 if (reg1 != (reg0 ^ APIC_ID_MASK))
820 * The next two are just to see if we have sane values.
821 * They're only really relevant if we're in Virtual Wire
822 * compatibility mode, but most boxes are anymore.
824 reg0 = apic_read(APIC_LVT0);
825 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
826 reg1 = apic_read(APIC_LVT1);
827 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
833 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
835 void __init sync_Arb_IDs(void)
838 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
841 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
847 apic_wait_icr_idle();
849 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
850 apic_write(APIC_ICR, APIC_DEST_ALLINC |
851 APIC_INT_LEVELTRIG | APIC_DM_INIT);
855 * An initial setup of the virtual wire mode.
857 void __init init_bsp_APIC(void)
862 * Don't do the setup now if we have a SMP BIOS as the
863 * through-I/O-APIC virtual wire mode might be active.
865 if (smp_found_config || !cpu_has_apic)
869 * Do not trust the local APIC being empty at bootup.
876 value = apic_read(APIC_SPIV);
877 value &= ~APIC_VECTOR_MASK;
878 value |= APIC_SPIV_APIC_ENABLED;
881 /* This bit is reserved on P4/Xeon and should be cleared */
882 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
883 (boot_cpu_data.x86 == 15))
884 value &= ~APIC_SPIV_FOCUS_DISABLED;
887 value |= APIC_SPIV_FOCUS_DISABLED;
888 value |= SPURIOUS_APIC_VECTOR;
889 apic_write(APIC_SPIV, value);
892 * Set up the virtual wire mode.
894 apic_write(APIC_LVT0, APIC_DM_EXTINT);
896 if (!lapic_is_integrated()) /* 82489DX */
897 value |= APIC_LVT_LEVEL_TRIGGER;
898 apic_write(APIC_LVT1, value);
901 static void __cpuinit lapic_setup_esr(void)
903 unsigned long oldvalue, value, maxlvt;
904 if (lapic_is_integrated() && !esr_disable) {
907 * Something untraceable is creating bad interrupts on
908 * secondary quads ... for the moment, just leave the
909 * ESR disabled - we can't do anything useful with the
910 * errors anyway - mbligh
912 printk(KERN_INFO "Leaving ESR disabled.\n");
916 maxlvt = lapic_get_maxlvt();
917 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
918 apic_write(APIC_ESR, 0);
919 oldvalue = apic_read(APIC_ESR);
921 /* enables sending errors */
922 value = ERROR_APIC_VECTOR;
923 apic_write(APIC_LVTERR, value);
925 * spec says clear errors after enabling vector.
928 apic_write(APIC_ESR, 0);
929 value = apic_read(APIC_ESR);
930 if (value != oldvalue)
931 apic_printk(APIC_VERBOSE, "ESR value before enabling "
932 "vector: 0x%08lx after: 0x%08lx\n",
935 printk(KERN_INFO "No ESR for 82489DX.\n");
941 * setup_local_APIC - setup the local APIC
943 void __cpuinit setup_local_APIC(void)
949 /* Pound the ESR really hard over the head with a big hammer - mbligh */
951 apic_write(APIC_ESR, 0);
952 apic_write(APIC_ESR, 0);
953 apic_write(APIC_ESR, 0);
954 apic_write(APIC_ESR, 0);
961 * Double-check whether this APIC is really registered.
962 * This is meaningless in clustered apic mode, so we skip it.
964 if (!apic_id_registered())
968 * Intel recommends to set DFR, LDR and TPR before enabling
969 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
970 * document number 292116). So here it goes...
975 * Set Task Priority to 'accept all'. We never change this
978 value = apic_read(APIC_TASKPRI);
979 value &= ~APIC_TPRI_MASK;
980 apic_write(APIC_TASKPRI, value);
983 * After a crash, we no longer service the interrupts and a pending
984 * interrupt from previous kernel might still have ISR bit set.
986 * Most probably by now CPU has serviced that pending interrupt and
987 * it might not have done the ack_APIC_irq() because it thought,
988 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
989 * does not clear the ISR bit and cpu thinks it has already serivced
990 * the interrupt. Hence a vector might get locked. It was noticed
991 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
993 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
994 value = apic_read(APIC_ISR + i*0x10);
995 for (j = 31; j >= 0; j--) {
1002 * Now that we are all set up, enable the APIC
1004 value = apic_read(APIC_SPIV);
1005 value &= ~APIC_VECTOR_MASK;
1009 value |= APIC_SPIV_APIC_ENABLED;
1011 #ifdef CONFIG_X86_32
1013 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1014 * certain networking cards. If high frequency interrupts are
1015 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1016 * entry is masked/unmasked at a high rate as well then sooner or
1017 * later IOAPIC line gets 'stuck', no more interrupts are received
1018 * from the device. If focus CPU is disabled then the hang goes
1021 * [ This bug can be reproduced easily with a level-triggered
1022 * PCI Ne2000 networking cards and PII/PIII processors, dual
1026 * Actually disabling the focus CPU check just makes the hang less
1027 * frequent as it makes the interrupt distributon model be more
1028 * like LRU than MRU (the short-term load is more even across CPUs).
1029 * See also the comment in end_level_ioapic_irq(). --macro
1033 * - enable focus processor (bit==0)
1034 * - 64bit mode always use processor focus
1035 * so no need to set it
1037 value &= ~APIC_SPIV_FOCUS_DISABLED;
1041 * Set spurious IRQ vector
1043 value |= SPURIOUS_APIC_VECTOR;
1044 apic_write(APIC_SPIV, value);
1047 * Set up LVT0, LVT1:
1049 * set up through-local-APIC on the BP's LINT0. This is not
1050 * strictly necessary in pure symmetric-IO mode, but sometimes
1051 * we delegate interrupts to the 8259A.
1054 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1056 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1057 if (!smp_processor_id() && (pic_mode || !value)) {
1058 value = APIC_DM_EXTINT;
1059 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1060 smp_processor_id());
1062 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1063 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1064 smp_processor_id());
1066 apic_write(APIC_LVT0, value);
1069 * only the BP should see the LINT1 NMI signal, obviously.
1071 if (!smp_processor_id())
1072 value = APIC_DM_NMI;
1074 value = APIC_DM_NMI | APIC_LVT_MASKED;
1075 if (!lapic_is_integrated()) /* 82489DX */
1076 value |= APIC_LVT_LEVEL_TRIGGER;
1077 apic_write(APIC_LVT1, value);
1082 void __cpuinit end_local_APIC_setup(void)
1086 #ifdef CONFIG_X86_32
1089 /* Disable the local apic timer */
1090 value = apic_read(APIC_LVTT);
1091 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1092 apic_write(APIC_LVTT, value);
1096 setup_apic_nmi_watchdog(NULL);
1100 void check_x2apic(void)
1104 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1106 if (msr & X2APIC_ENABLE) {
1107 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1108 x2apic_preenabled = x2apic = 1;
1109 apic_ops = &x2apic_ops;
1113 void enable_x2apic(void)
1117 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1118 if (!(msr & X2APIC_ENABLE)) {
1119 printk("Enabling x2apic\n");
1120 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1124 void enable_IR_x2apic(void)
1126 #ifdef CONFIG_INTR_REMAP
1128 unsigned long flags;
1130 if (!cpu_has_x2apic)
1133 if (!x2apic_preenabled && disable_x2apic) {
1135 "Skipped enabling x2apic and Interrupt-remapping "
1136 "because of nox2apic\n");
1140 if (x2apic_preenabled && disable_x2apic)
1141 panic("Bios already enabled x2apic, can't enforce nox2apic");
1143 if (!x2apic_preenabled && skip_ioapic_setup) {
1145 "Skipped enabling x2apic and Interrupt-remapping "
1146 "because of skipping io-apic setup\n");
1150 ret = dmar_table_init();
1153 "dmar_table_init() failed with %d:\n", ret);
1155 if (x2apic_preenabled)
1156 panic("x2apic enabled by bios. But IR enabling failed");
1159 "Not enabling x2apic,Intr-remapping\n");
1163 local_irq_save(flags);
1165 save_mask_IO_APIC_setup();
1167 ret = enable_intr_remapping(1);
1169 if (ret && x2apic_preenabled) {
1170 local_irq_restore(flags);
1171 panic("x2apic enabled by bios. But IR enabling failed");
1179 apic_ops = &x2apic_ops;
1185 * IR enabling failed
1187 restore_IO_APIC_setup();
1189 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1192 local_irq_restore(flags);
1195 if (!x2apic_preenabled)
1197 "Enabled x2apic and interrupt-remapping\n");
1200 "Enabled Interrupt-remapping\n");
1203 "Failed to enable Interrupt-remapping and x2apic\n");
1205 if (!cpu_has_x2apic)
1208 if (x2apic_preenabled)
1209 panic("x2apic enabled prior OS handover,"
1210 " enable CONFIG_INTR_REMAP");
1212 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1220 * Detect and enable local APICs on non-SMP boards.
1221 * Original code written by Keir Fraser.
1222 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1223 * not correctly set up (usually the APIC timer won't work etc.)
1225 static int __init detect_init_APIC(void)
1227 if (!cpu_has_apic) {
1228 printk(KERN_INFO "No local APIC present\n");
1232 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1233 boot_cpu_physical_apicid = 0;
1237 void __init early_init_lapic_mapping(void)
1239 unsigned long phys_addr;
1242 * If no local APIC can be found then go out
1243 * : it means there is no mpatable and MADT
1245 if (!smp_found_config)
1248 phys_addr = mp_lapic_addr;
1250 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1251 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1252 APIC_BASE, phys_addr);
1255 * Fetch the APIC ID of the BSP in case we have a
1256 * default configuration (or the MP table is broken).
1258 boot_cpu_physical_apicid = read_apic_id();
1262 * init_apic_mappings - initialize APIC mappings
1264 void __init init_apic_mappings(void)
1267 boot_cpu_physical_apicid = read_apic_id();
1272 * If no local APIC can be found then set up a fake all
1273 * zeroes page to simulate the local APIC and another
1274 * one for the IO-APIC.
1276 if (!smp_found_config && detect_init_APIC()) {
1277 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1278 apic_phys = __pa(apic_phys);
1280 apic_phys = mp_lapic_addr;
1282 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1283 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1284 APIC_BASE, apic_phys);
1287 * Fetch the APIC ID of the BSP in case we have a
1288 * default configuration (or the MP table is broken).
1290 boot_cpu_physical_apicid = read_apic_id();
1294 * This initializes the IO-APIC and APIC hardware if this is
1297 int apic_version[MAX_APICS];
1299 int __init APIC_init_uniprocessor(void)
1302 printk(KERN_INFO "Apic disabled\n");
1305 if (!cpu_has_apic) {
1307 printk(KERN_INFO "Apic disabled by BIOS\n");
1312 setup_apic_routing();
1314 verify_local_APIC();
1318 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1319 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1324 * Now enable IO-APICs, actually call clear_IO_APIC
1325 * We need clear_IO_APIC before enabling vector on BP
1327 if (!skip_ioapic_setup && nr_ioapics)
1330 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1331 localise_nmi_watchdog();
1332 end_local_APIC_setup();
1334 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1338 setup_boot_APIC_clock();
1339 check_nmi_watchdog();
1344 * Local APIC interrupts
1348 * This interrupt should _never_ happen with our APIC/SMP architecture
1350 asmlinkage void smp_spurious_interrupt(void)
1356 * Check if this really is a spurious interrupt and ACK it
1357 * if it is a vectored one. Just in case...
1358 * Spurious interrupts should not be ACKed.
1360 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1361 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1364 add_pda(irq_spurious_count, 1);
1369 * This interrupt should never happen with our APIC/SMP architecture
1371 asmlinkage void smp_error_interrupt(void)
1377 /* First tickle the hardware, only then report what went on. -- REW */
1378 v = apic_read(APIC_ESR);
1379 apic_write(APIC_ESR, 0);
1380 v1 = apic_read(APIC_ESR);
1382 atomic_inc(&irq_err_count);
1384 /* Here is what the APIC error bits mean:
1387 2: Send accept error
1388 3: Receive accept error
1390 5: Send illegal vector
1391 6: Received illegal vector
1392 7: Illegal register address
1394 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1395 smp_processor_id(), v , v1);
1400 * connect_bsp_APIC - attach the APIC to the interrupt system
1402 void __init connect_bsp_APIC(void)
1404 #ifdef CONFIG_X86_32
1407 * Do not trust the local APIC being empty at bootup.
1411 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1412 * local APIC to INT and NMI lines.
1414 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1415 "enabling APIC mode.\n");
1424 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1425 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1427 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1430 void disconnect_bsp_APIC(int virt_wire_setup)
1434 #ifdef CONFIG_X86_32
1437 * Put the board back into PIC mode (has an effect only on
1438 * certain older boards). Note that APIC interrupts, including
1439 * IPIs, won't work beyond this point! The only exception are
1442 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1443 "entering PIC mode.\n");
1450 /* Go back to Virtual Wire compatibility mode */
1452 /* For the spurious interrupt use vector F, and enable it */
1453 value = apic_read(APIC_SPIV);
1454 value &= ~APIC_VECTOR_MASK;
1455 value |= APIC_SPIV_APIC_ENABLED;
1457 apic_write(APIC_SPIV, value);
1459 if (!virt_wire_setup) {
1461 * For LVT0 make it edge triggered, active high,
1462 * external and enabled
1464 value = apic_read(APIC_LVT0);
1465 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1466 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1467 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1468 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1469 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1470 apic_write(APIC_LVT0, value);
1473 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1477 * For LVT1 make it edge triggered, active high,
1480 value = apic_read(APIC_LVT1);
1481 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1482 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1483 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1484 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1485 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1486 apic_write(APIC_LVT1, value);
1489 void __cpuinit generic_processor_info(int apicid, int version)
1497 if (version == 0x0) {
1498 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1499 "fixing up to 0x10. (tell your hw vendor)\n",
1503 apic_version[apicid] = version;
1505 if (num_processors >= NR_CPUS) {
1506 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1507 " Processor ignored.\n", NR_CPUS);
1512 cpus_complement(tmp_map, cpu_present_map);
1513 cpu = first_cpu(tmp_map);
1515 physid_set(apicid, phys_cpu_present_map);
1516 if (apicid == boot_cpu_physical_apicid) {
1518 * x86_bios_cpu_apicid is required to have processors listed
1519 * in same order as logical cpu numbers. Hence the first
1520 * entry is BSP, and so on.
1524 if (apicid > max_physical_apicid)
1525 max_physical_apicid = apicid;
1527 #ifdef CONFIG_X86_32
1529 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1530 * but we need to work other dependencies like SMP_SUSPEND etc
1531 * before this can be done without some confusion.
1532 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1533 * - Ashok Raj <ashok.raj@intel.com>
1535 if (max_physical_apicid >= 8) {
1536 switch (boot_cpu_data.x86_vendor) {
1537 case X86_VENDOR_INTEL:
1538 if (!APIC_XAPIC(version)) {
1542 /* If P4 and above fall through */
1543 case X86_VENDOR_AMD:
1549 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1550 /* are we being called early in kernel startup? */
1551 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1552 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1553 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1555 cpu_to_apicid[cpu] = apicid;
1556 bios_cpu_apicid[cpu] = apicid;
1558 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1559 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1563 cpu_set(cpu, cpu_possible_map);
1564 cpu_set(cpu, cpu_present_map);
1567 int hard_smp_processor_id(void)
1569 return read_apic_id();
1579 * 'active' is true if the local APIC was enabled by us and
1580 * not the BIOS; this signifies that we are also responsible
1581 * for disabling it before entering apm/acpi suspend
1584 /* r/w apic fields */
1585 unsigned int apic_id;
1586 unsigned int apic_taskpri;
1587 unsigned int apic_ldr;
1588 unsigned int apic_dfr;
1589 unsigned int apic_spiv;
1590 unsigned int apic_lvtt;
1591 unsigned int apic_lvtpc;
1592 unsigned int apic_lvt0;
1593 unsigned int apic_lvt1;
1594 unsigned int apic_lvterr;
1595 unsigned int apic_tmict;
1596 unsigned int apic_tdcr;
1597 unsigned int apic_thmr;
1600 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1602 unsigned long flags;
1605 if (!apic_pm_state.active)
1608 maxlvt = lapic_get_maxlvt();
1610 apic_pm_state.apic_id = apic_read(APIC_ID);
1611 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1612 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1613 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1614 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1615 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1617 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1618 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1619 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1620 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1621 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1622 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1623 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1625 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1628 local_irq_save(flags);
1629 disable_local_APIC();
1630 local_irq_restore(flags);
1634 static int lapic_resume(struct sys_device *dev)
1637 unsigned long flags;
1640 if (!apic_pm_state.active)
1643 maxlvt = lapic_get_maxlvt();
1645 local_irq_save(flags);
1647 #ifdef CONFIG_X86_64
1654 * Make sure the APICBASE points to the right address
1656 * FIXME! This will be wrong if we ever support suspend on
1657 * SMP! We'll need to do this as part of the CPU restore!
1659 rdmsr(MSR_IA32_APICBASE, l, h);
1660 l &= ~MSR_IA32_APICBASE_BASE;
1661 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1662 wrmsr(MSR_IA32_APICBASE, l, h);
1665 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1666 apic_write(APIC_ID, apic_pm_state.apic_id);
1667 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1668 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1669 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1670 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1671 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1672 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1673 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1675 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1678 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1679 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1680 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1681 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1682 apic_write(APIC_ESR, 0);
1683 apic_read(APIC_ESR);
1684 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1685 apic_write(APIC_ESR, 0);
1686 apic_read(APIC_ESR);
1688 local_irq_restore(flags);
1694 * This device has no shutdown method - fully functioning local APICs
1695 * are needed on every CPU up until machine_halt/restart/poweroff.
1698 static struct sysdev_class lapic_sysclass = {
1700 .resume = lapic_resume,
1701 .suspend = lapic_suspend,
1704 static struct sys_device device_lapic = {
1706 .cls = &lapic_sysclass,
1709 static void __cpuinit apic_pm_activate(void)
1711 apic_pm_state.active = 1;
1714 static int __init init_lapic_sysfs(void)
1720 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1722 error = sysdev_class_register(&lapic_sysclass);
1724 error = sysdev_register(&device_lapic);
1727 device_initcall(init_lapic_sysfs);
1729 #else /* CONFIG_PM */
1731 static void apic_pm_activate(void) { }
1733 #endif /* CONFIG_PM */
1736 * apic_is_clustered_box() -- Check if we can expect good TSC
1738 * Thus far, the major user of this is IBM's Summit2 series:
1740 * Clustered boxes may have unsynced TSC problems if they are
1741 * multi-chassis. Use available data to take a good guess.
1742 * If in doubt, go HPET.
1744 __cpuinit int apic_is_clustered_box(void)
1746 int i, clusters, zeros;
1748 u16 *bios_cpu_apicid;
1749 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1752 * there is not this kind of box with AMD CPU yet.
1753 * Some AMD box with quadcore cpu and 8 sockets apicid
1754 * will be [4, 0x23] or [8, 0x27] could be thought to
1755 * vsmp box still need checking...
1757 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1760 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1761 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1763 for (i = 0; i < NR_CPUS; i++) {
1764 /* are we being called early in kernel startup? */
1765 if (bios_cpu_apicid) {
1766 id = bios_cpu_apicid[i];
1768 else if (i < nr_cpu_ids) {
1770 id = per_cpu(x86_bios_cpu_apicid, i);
1777 if (id != BAD_APICID)
1778 __set_bit(APIC_CLUSTERID(id), clustermap);
1781 /* Problem: Partially populated chassis may not have CPUs in some of
1782 * the APIC clusters they have been allocated. Only present CPUs have
1783 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1784 * Since clusters are allocated sequentially, count zeros only if
1785 * they are bounded by ones.
1789 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1790 if (test_bit(i, clustermap)) {
1791 clusters += 1 + zeros;
1797 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1798 * not guaranteed to be synced between boards
1800 if (is_vsmp_box() && clusters > 1)
1804 * If clusters > 2, then should be multi-chassis.
1805 * May have to revisit this when multi-core + hyperthreaded CPUs come
1806 * out, but AFAIK this will work even for them.
1808 return (clusters > 2);
1811 static __init int setup_nox2apic(char *str)
1814 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1817 early_param("nox2apic", setup_nox2apic);
1821 * APIC command line parameters
1823 static int __init setup_disableapic(char *arg)
1826 setup_clear_cpu_cap(X86_FEATURE_APIC);
1829 early_param("disableapic", setup_disableapic);
1831 /* same as disableapic, for compatibility */
1832 static int __init setup_nolapic(char *arg)
1834 return setup_disableapic(arg);
1836 early_param("nolapic", setup_nolapic);
1838 static int __init parse_lapic_timer_c2_ok(char *arg)
1840 local_apic_timer_c2_ok = 1;
1843 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1845 static int __init parse_disable_apic_timer(char *arg)
1847 disable_apic_timer = 1;
1850 early_param("noapictimer", parse_disable_apic_timer);
1852 static int __init parse_nolapic_timer(char *arg)
1854 disable_apic_timer = 1;
1857 early_param("nolapic_timer", parse_nolapic_timer);
1859 #ifdef CONFIG_X86_64
1860 static __init int setup_apicpmtimer(char *s)
1862 apic_calibrate_pmtmr = 1;
1866 __setup("apicpmtimer", setup_apicpmtimer);
1869 static int __init apic_set_verbosity(char *arg)
1872 #ifdef CONFIG_X86_64
1873 skip_ioapic_setup = 0;
1879 if (strcmp("debug", arg) == 0)
1880 apic_verbosity = APIC_DEBUG;
1881 else if (strcmp("verbose", arg) == 0)
1882 apic_verbosity = APIC_VERBOSE;
1884 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1885 " use apic=verbose or apic=debug\n", arg);
1891 early_param("apic", apic_set_verbosity);
1893 static int __init lapic_insert_resource(void)
1898 /* Put local APIC into the resource map. */
1899 lapic_resource.start = apic_phys;
1900 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1901 insert_resource(&iomem_resource, &lapic_resource);
1907 * need call insert after e820_reserve_resources()
1908 * that is using request_resource
1910 late_initcall(lapic_insert_resource);