2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
71 int first_system_vector = 0xfe;
73 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
76 * Debug level, exported for io_apic.c
78 unsigned int apic_verbosity;
82 /* Have we found an MP table */
85 static struct resource lapic_resource = {
87 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
90 static unsigned int calibration_result;
92 static int lapic_next_event(unsigned long delta,
93 struct clock_event_device *evt);
94 static void lapic_timer_setup(enum clock_event_mode mode,
95 struct clock_event_device *evt);
96 static void lapic_timer_broadcast(cpumask_t mask);
97 static void apic_pm_activate(void);
100 * The local apic timer can be used for any function which is CPU local.
102 static struct clock_event_device lapic_clockevent = {
104 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
105 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
107 .set_mode = lapic_timer_setup,
108 .set_next_event = lapic_next_event,
109 .broadcast = lapic_timer_broadcast,
113 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase;
118 static unsigned long apic_phys;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
133 return APIC_INTEGRATED(lapic_get_version());
137 * Check, whether this is a modern or a first generation APIC
139 static int modern_apic(void)
141 /* AMD systems use old APIC versions, so check the CPU */
142 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
143 boot_cpu_data.x86 >= 0xf)
145 return lapic_get_version() >= 0x14;
149 * Paravirt kernels also might be using these below ops. So we still
150 * use generic apic_read()/apic_write(), which might be pointing to different
151 * ops in PARAVIRT case.
153 void xapic_wait_icr_idle(void)
155 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
159 u32 safe_xapic_wait_icr_idle(void)
166 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
170 } while (timeout++ < 1000);
175 void xapic_icr_write(u32 low, u32 id)
177 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(id));
178 apic_write_around(APIC_ICR, low);
181 u64 xapic_icr_read(void)
185 icr2 = apic_read(APIC_ICR2);
186 icr1 = apic_read(APIC_ICR);
188 return icr1 | ((u64)icr2 << 32);
191 static struct apic_ops xapic_ops = {
192 .read = native_apic_mem_read,
193 .write = native_apic_mem_write,
194 .write_atomic = native_apic_mem_write_atomic,
195 .icr_read = xapic_icr_read,
196 .icr_write = xapic_icr_write,
197 .wait_icr_idle = xapic_wait_icr_idle,
198 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
201 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
202 EXPORT_SYMBOL_GPL(apic_ops);
205 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
207 void __cpuinit enable_NMI_through_LVT0(void)
209 unsigned int v = APIC_DM_NMI;
211 /* Level triggered for 82489DX */
212 if (!lapic_is_integrated())
213 v |= APIC_LVT_LEVEL_TRIGGER;
214 apic_write(APIC_LVT0, v);
218 * get_physical_broadcast - Get number of physical broadcast IDs
220 int get_physical_broadcast(void)
222 return modern_apic() ? 0xff : 0xf;
226 * lapic_get_maxlvt - get the maximum number of local vector table entries
228 int lapic_get_maxlvt(void)
230 unsigned int v = apic_read(APIC_LVR);
232 /* 82489DXs do not report # of LVT entries. */
233 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
240 /* Clock divisor is set to 16 */
241 #define APIC_DIVISOR 16
244 * This function sets up the local APIC timer, with a timeout of
245 * 'clocks' APIC bus clock. During calibration we actually call
246 * this function twice on the boot CPU, once with a bogus timeout
247 * value, second time for real. The other (noncalibrating) CPUs
248 * call this function only once, with the real, calibrated value.
250 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
252 unsigned int lvtt_value, tmp_value;
254 lvtt_value = LOCAL_TIMER_VECTOR;
256 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
257 if (!lapic_is_integrated())
258 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
261 lvtt_value |= APIC_LVT_MASKED;
263 apic_write(APIC_LVTT, lvtt_value);
268 tmp_value = apic_read(APIC_TDCR);
269 apic_write(APIC_TDCR,
270 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
274 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
278 * Program the next event, relative to now
280 static int lapic_next_event(unsigned long delta,
281 struct clock_event_device *evt)
283 apic_write(APIC_TMICT, delta);
288 * Setup the lapic timer in periodic or oneshot mode
290 static void lapic_timer_setup(enum clock_event_mode mode,
291 struct clock_event_device *evt)
296 /* Lapic used for broadcast ? */
297 if (!local_apic_timer_verify_ok)
300 local_irq_save(flags);
303 case CLOCK_EVT_MODE_PERIODIC:
304 case CLOCK_EVT_MODE_ONESHOT:
305 __setup_APIC_LVTT(calibration_result,
306 mode != CLOCK_EVT_MODE_PERIODIC, 1);
308 case CLOCK_EVT_MODE_UNUSED:
309 case CLOCK_EVT_MODE_SHUTDOWN:
310 v = apic_read(APIC_LVTT);
311 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
312 apic_write(APIC_LVTT, v);
314 case CLOCK_EVT_MODE_RESUME:
315 /* Nothing to do here */
319 local_irq_restore(flags);
323 * Local APIC timer broadcast function
325 static void lapic_timer_broadcast(cpumask_t mask)
328 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
333 * Setup the local APIC timer for this CPU. Copy the initilized values
334 * of the boot CPU and register the clock event in the framework.
336 static void __devinit setup_APIC_timer(void)
338 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
340 memcpy(levt, &lapic_clockevent, sizeof(*levt));
341 levt->cpumask = cpumask_of_cpu(smp_processor_id());
343 clockevents_register_device(levt);
347 * In this functions we calibrate APIC bus clocks to the external timer.
349 * We want to do the calibration only once since we want to have local timer
350 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
353 * This was previously done by reading the PIT/HPET and waiting for a wrap
354 * around to find out, that a tick has elapsed. I have a box, where the PIT
355 * readout is broken, so it never gets out of the wait loop again. This was
356 * also reported by others.
358 * Monitoring the jiffies value is inaccurate and the clockevents
359 * infrastructure allows us to do a simple substitution of the interrupt
362 * The calibration routine also uses the pm_timer when possible, as the PIT
363 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
364 * back to normal later in the boot process).
367 #define LAPIC_CAL_LOOPS (HZ/10)
369 static __initdata int lapic_cal_loops = -1;
370 static __initdata long lapic_cal_t1, lapic_cal_t2;
371 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
372 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
373 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
376 * Temporary interrupt handler.
378 static void __init lapic_cal_handler(struct clock_event_device *dev)
380 unsigned long long tsc = 0;
381 long tapic = apic_read(APIC_TMCCT);
382 unsigned long pm = acpi_pm_read_early();
387 switch (lapic_cal_loops++) {
389 lapic_cal_t1 = tapic;
390 lapic_cal_tsc1 = tsc;
392 lapic_cal_j1 = jiffies;
395 case LAPIC_CAL_LOOPS:
396 lapic_cal_t2 = tapic;
397 lapic_cal_tsc2 = tsc;
398 if (pm < lapic_cal_pm1)
399 pm += ACPI_PM_OVRRUN;
401 lapic_cal_j2 = jiffies;
406 static int __init calibrate_APIC_clock(void)
408 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
409 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
410 const long pm_thresh = pm_100ms/100;
411 void (*real_handler)(struct clock_event_device *dev);
412 unsigned long deltaj;
414 int pm_referenced = 0;
418 /* Replace the global interrupt handler */
419 real_handler = global_clock_event->event_handler;
420 global_clock_event->event_handler = lapic_cal_handler;
423 * Setup the APIC counter to 1e9. There is no way the lapic
424 * can underflow in the 100ms detection time frame
426 __setup_APIC_LVTT(1000000000, 0, 0);
428 /* Let the interrupts run */
431 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
436 /* Restore the real event handler */
437 global_clock_event->event_handler = real_handler;
439 /* Build delta t1-t2 as apic timer counts down */
440 delta = lapic_cal_t1 - lapic_cal_t2;
441 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
443 /* Check, if the PM timer is available */
444 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
445 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
451 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
453 if (deltapm > (pm_100ms - pm_thresh) &&
454 deltapm < (pm_100ms + pm_thresh)) {
455 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
457 res = (((u64) deltapm) * mult) >> 22;
458 do_div(res, 1000000);
459 printk(KERN_WARNING "APIC calibration not consistent "
460 "with PM Timer: %ldms instead of 100ms\n",
462 /* Correct the lapic counter value */
463 res = (((u64) delta) * pm_100ms);
464 do_div(res, deltapm);
465 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
466 "%lu (%ld)\n", (unsigned long) res, delta);
472 /* Calculate the scaled math multiplication factor */
473 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
474 lapic_clockevent.shift);
475 lapic_clockevent.max_delta_ns =
476 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
477 lapic_clockevent.min_delta_ns =
478 clockevent_delta2ns(0xF, &lapic_clockevent);
480 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
482 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
483 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
484 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
488 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
489 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
491 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
492 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
495 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
497 calibration_result / (1000000 / HZ),
498 calibration_result % (1000000 / HZ));
501 * Do a sanity check on the APIC calibration result
503 if (calibration_result < (1000000 / HZ)) {
506 "APIC frequency too slow, disabling apic timer\n");
510 local_apic_timer_verify_ok = 1;
512 /* We trust the pm timer based calibration */
513 if (!pm_referenced) {
514 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
517 * Setup the apic timer manually
519 levt->event_handler = lapic_cal_handler;
520 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
521 lapic_cal_loops = -1;
523 /* Let the interrupts run */
526 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
531 /* Stop the lapic timer */
532 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
537 deltaj = lapic_cal_j2 - lapic_cal_j1;
538 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
540 /* Check, if the jiffies result is consistent */
541 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
542 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
544 local_apic_timer_verify_ok = 0;
548 if (!local_apic_timer_verify_ok) {
550 "APIC timer disabled due to verification failure.\n");
558 * Setup the boot APIC
560 * Calibrate and verify the result.
562 void __init setup_boot_APIC_clock(void)
565 * The local apic timer can be disabled via the kernel
566 * commandline or from the CPU detection code. Register the lapic
567 * timer as a dummy clock event source on SMP systems, so the
568 * broadcast mechanism is used. On UP systems simply ignore it.
570 if (local_apic_timer_disabled) {
571 /* No broadcast on UP ! */
572 if (num_possible_cpus() > 1) {
573 lapic_clockevent.mult = 1;
579 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
580 "calibrating APIC timer ...\n");
582 if (calibrate_APIC_clock()) {
583 /* No broadcast on UP ! */
584 if (num_possible_cpus() > 1)
590 * If nmi_watchdog is set to IO_APIC, we need the
591 * PIT/HPET going. Otherwise register lapic as a dummy
594 if (nmi_watchdog != NMI_IO_APIC)
595 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
597 printk(KERN_WARNING "APIC timer registered as dummy,"
598 " due to nmi_watchdog=%d!\n", nmi_watchdog);
600 /* Setup the lapic or request the broadcast */
604 void __devinit setup_secondary_APIC_clock(void)
610 * The guts of the apic timer interrupt
612 static void local_apic_timer_interrupt(void)
614 int cpu = smp_processor_id();
615 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
618 * Normally we should not be here till LAPIC has been initialized but
619 * in some cases like kdump, its possible that there is a pending LAPIC
620 * timer interrupt from previous kernel's context and is delivered in
621 * new kernel the moment interrupts are enabled.
623 * Interrupts are enabled early and LAPIC is setup much later, hence
624 * its possible that when we get here evt->event_handler is NULL.
625 * Check for event_handler being NULL and discard the interrupt as
628 if (!evt->event_handler) {
630 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
632 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
637 * the NMI deadlock-detector uses this.
639 per_cpu(irq_stat, cpu).apic_timer_irqs++;
641 evt->event_handler(evt);
645 * Local APIC timer interrupt. This is the most natural way for doing
646 * local interrupts, but local timer interrupts can be emulated by
647 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
649 * [ if a single-CPU system runs an SMP kernel then we call the local
650 * interrupt as well. Thus we cannot inline the local irq ... ]
652 void smp_apic_timer_interrupt(struct pt_regs *regs)
654 struct pt_regs *old_regs = set_irq_regs(regs);
657 * NOTE! We'd better ACK the irq immediately,
658 * because timer handling can be slow.
662 * update_process_times() expects us to have done irq_enter().
663 * Besides, if we don't timer interrupts ignore the global
664 * interrupt lock, which is the WrongThing (tm) to do.
667 local_apic_timer_interrupt();
670 set_irq_regs(old_regs);
673 int setup_profiling_timer(unsigned int multiplier)
679 * Setup extended LVT, AMD specific (K8, family 10h)
681 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
682 * MCE interrupts are supported. Thus MCE offset must be set to 0.
685 #define APIC_EILVT_LVTOFF_MCE 0
686 #define APIC_EILVT_LVTOFF_IBS 1
688 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
690 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
691 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
695 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
697 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
698 return APIC_EILVT_LVTOFF_MCE;
701 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
703 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
704 return APIC_EILVT_LVTOFF_IBS;
708 * Local APIC start and shutdown
712 * clear_local_APIC - shutdown the local APIC
714 * This is called, when a CPU is disabled and before rebooting, so the state of
715 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
716 * leftovers during boot.
718 void clear_local_APIC(void)
723 /* APIC hasn't been mapped yet */
727 maxlvt = lapic_get_maxlvt();
729 * Masking an LVT entry can trigger a local APIC error
730 * if the vector is zero. Mask LVTERR first to prevent this.
733 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
734 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
737 * Careful: we have to set masks only first to deassert
738 * any level-triggered sources.
740 v = apic_read(APIC_LVTT);
741 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
742 v = apic_read(APIC_LVT0);
743 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
744 v = apic_read(APIC_LVT1);
745 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
747 v = apic_read(APIC_LVTPC);
748 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
751 /* lets not touch this if we didn't frob it */
752 #ifdef CONFIG_X86_MCE_P4THERMAL
754 v = apic_read(APIC_LVTTHMR);
755 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
759 * Clean APIC state for other OSs:
761 apic_write(APIC_LVTT, APIC_LVT_MASKED);
762 apic_write(APIC_LVT0, APIC_LVT_MASKED);
763 apic_write(APIC_LVT1, APIC_LVT_MASKED);
765 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
767 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
769 #ifdef CONFIG_X86_MCE_P4THERMAL
771 apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
773 /* Integrated APIC (!82489DX) ? */
774 if (lapic_is_integrated()) {
776 /* Clear ESR due to Pentium errata 3AP and 11AP */
777 apic_write(APIC_ESR, 0);
783 * disable_local_APIC - clear and disable the local APIC
785 void disable_local_APIC(void)
792 * Disable APIC (implies clearing of registers
795 value = apic_read(APIC_SPIV);
796 value &= ~APIC_SPIV_APIC_ENABLED;
797 apic_write(APIC_SPIV, value);
800 * When LAPIC was disabled by the BIOS and enabled by the kernel,
801 * restore the disabled state.
803 if (enabled_via_apicbase) {
806 rdmsr(MSR_IA32_APICBASE, l, h);
807 l &= ~MSR_IA32_APICBASE_ENABLE;
808 wrmsr(MSR_IA32_APICBASE, l, h);
813 * If Linux enabled the LAPIC against the BIOS default disable it down before
814 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
815 * not power-off. Additionally clear all LVT entries before disable_local_APIC
816 * for the case where Linux didn't enable the LAPIC.
818 void lapic_shutdown(void)
825 local_irq_save(flags);
828 if (enabled_via_apicbase)
829 disable_local_APIC();
831 local_irq_restore(flags);
835 * This is to verify that we're looking at a real local APIC.
836 * Check these against your board if the CPUs aren't getting
837 * started for no apparent reason.
839 int __init verify_local_APIC(void)
841 unsigned int reg0, reg1;
844 * The version register is read-only in a real APIC.
846 reg0 = apic_read(APIC_LVR);
847 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
848 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
849 reg1 = apic_read(APIC_LVR);
850 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
853 * The two version reads above should print the same
854 * numbers. If the second one is different, then we
855 * poke at a non-APIC.
861 * Check if the version looks reasonably.
863 reg1 = GET_APIC_VERSION(reg0);
864 if (reg1 == 0x00 || reg1 == 0xff)
866 reg1 = lapic_get_maxlvt();
867 if (reg1 < 0x02 || reg1 == 0xff)
871 * The ID register is read/write in a real APIC.
873 reg0 = apic_read(APIC_ID);
874 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
877 * The next two are just to see if we have sane values.
878 * They're only really relevant if we're in Virtual Wire
879 * compatibility mode, but most boxes are anymore.
881 reg0 = apic_read(APIC_LVT0);
882 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
883 reg1 = apic_read(APIC_LVT1);
884 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
890 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
892 void __init sync_Arb_IDs(void)
895 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
898 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
903 apic_wait_icr_idle();
905 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
907 APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
911 * An initial setup of the virtual wire mode.
913 void __init init_bsp_APIC(void)
918 * Don't do the setup now if we have a SMP BIOS as the
919 * through-I/O-APIC virtual wire mode might be active.
921 if (smp_found_config || !cpu_has_apic)
925 * Do not trust the local APIC being empty at bootup.
932 value = apic_read(APIC_SPIV);
933 value &= ~APIC_VECTOR_MASK;
934 value |= APIC_SPIV_APIC_ENABLED;
936 /* This bit is reserved on P4/Xeon and should be cleared */
937 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
938 (boot_cpu_data.x86 == 15))
939 value &= ~APIC_SPIV_FOCUS_DISABLED;
941 value |= APIC_SPIV_FOCUS_DISABLED;
942 value |= SPURIOUS_APIC_VECTOR;
943 apic_write(APIC_SPIV, value);
946 * Set up the virtual wire mode.
948 apic_write(APIC_LVT0, APIC_DM_EXTINT);
950 if (!lapic_is_integrated()) /* 82489DX */
951 value |= APIC_LVT_LEVEL_TRIGGER;
952 apic_write(APIC_LVT1, value);
955 static void __cpuinit lapic_setup_esr(void)
957 unsigned long oldvalue, value, maxlvt;
958 if (lapic_is_integrated() && !esr_disable) {
960 maxlvt = lapic_get_maxlvt();
961 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
962 apic_write(APIC_ESR, 0);
963 oldvalue = apic_read(APIC_ESR);
965 /* enables sending errors */
966 value = ERROR_APIC_VECTOR;
967 apic_write(APIC_LVTERR, value);
969 * spec says clear errors after enabling vector.
972 apic_write(APIC_ESR, 0);
973 value = apic_read(APIC_ESR);
974 if (value != oldvalue)
975 apic_printk(APIC_VERBOSE, "ESR value before enabling "
976 "vector: 0x%08lx after: 0x%08lx\n",
981 * Something untraceable is creating bad interrupts on
982 * secondary quads ... for the moment, just leave the
983 * ESR disabled - we can't do anything useful with the
984 * errors anyway - mbligh
986 printk(KERN_INFO "Leaving ESR disabled.\n");
988 printk(KERN_INFO "No ESR for 82489DX.\n");
994 * setup_local_APIC - setup the local APIC
996 void __cpuinit setup_local_APIC(void)
998 unsigned long value, integrated;
1001 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1003 apic_write(APIC_ESR, 0);
1004 apic_write(APIC_ESR, 0);
1005 apic_write(APIC_ESR, 0);
1006 apic_write(APIC_ESR, 0);
1009 integrated = lapic_is_integrated();
1012 * Double-check whether this APIC is really registered.
1014 if (!apic_id_registered())
1018 * Intel recommends to set DFR, LDR and TPR before enabling
1019 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1020 * document number 292116). So here it goes...
1025 * Set Task Priority to 'accept all'. We never change this
1028 value = apic_read(APIC_TASKPRI);
1029 value &= ~APIC_TPRI_MASK;
1030 apic_write(APIC_TASKPRI, value);
1033 * After a crash, we no longer service the interrupts and a pending
1034 * interrupt from previous kernel might still have ISR bit set.
1036 * Most probably by now CPU has serviced that pending interrupt and
1037 * it might not have done the ack_APIC_irq() because it thought,
1038 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1039 * does not clear the ISR bit and cpu thinks it has already serivced
1040 * the interrupt. Hence a vector might get locked. It was noticed
1041 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1043 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1044 value = apic_read(APIC_ISR + i*0x10);
1045 for (j = 31; j >= 0; j--) {
1052 * Now that we are all set up, enable the APIC
1054 value = apic_read(APIC_SPIV);
1055 value &= ~APIC_VECTOR_MASK;
1059 value |= APIC_SPIV_APIC_ENABLED;
1062 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1063 * certain networking cards. If high frequency interrupts are
1064 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1065 * entry is masked/unmasked at a high rate as well then sooner or
1066 * later IOAPIC line gets 'stuck', no more interrupts are received
1067 * from the device. If focus CPU is disabled then the hang goes
1070 * [ This bug can be reproduced easily with a level-triggered
1071 * PCI Ne2000 networking cards and PII/PIII processors, dual
1075 * Actually disabling the focus CPU check just makes the hang less
1076 * frequent as it makes the interrupt distributon model be more
1077 * like LRU than MRU (the short-term load is more even across CPUs).
1078 * See also the comment in end_level_ioapic_irq(). --macro
1081 /* Enable focus processor (bit==0) */
1082 value &= ~APIC_SPIV_FOCUS_DISABLED;
1085 * Set spurious IRQ vector
1087 value |= SPURIOUS_APIC_VECTOR;
1088 apic_write(APIC_SPIV, value);
1091 * Set up LVT0, LVT1:
1093 * set up through-local-APIC on the BP's LINT0. This is not
1094 * strictly necessary in pure symmetric-IO mode, but sometimes
1095 * we delegate interrupts to the 8259A.
1098 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1100 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1101 if (!smp_processor_id() && (pic_mode || !value)) {
1102 value = APIC_DM_EXTINT;
1103 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1104 smp_processor_id());
1106 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1107 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1108 smp_processor_id());
1110 apic_write(APIC_LVT0, value);
1113 * only the BP should see the LINT1 NMI signal, obviously.
1115 if (!smp_processor_id())
1116 value = APIC_DM_NMI;
1118 value = APIC_DM_NMI | APIC_LVT_MASKED;
1119 if (!integrated) /* 82489DX */
1120 value |= APIC_LVT_LEVEL_TRIGGER;
1121 apic_write(APIC_LVT1, value);
1124 void __cpuinit end_local_APIC_setup(void)
1126 unsigned long value;
1129 /* Disable the local apic timer */
1130 value = apic_read(APIC_LVTT);
1131 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1132 apic_write(APIC_LVTT, value);
1134 setup_apic_nmi_watchdog(NULL);
1139 * Detect and initialize APIC
1141 static int __init detect_init_APIC(void)
1145 /* Disabled by kernel option? */
1149 switch (boot_cpu_data.x86_vendor) {
1150 case X86_VENDOR_AMD:
1151 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1152 (boot_cpu_data.x86 == 15))
1155 case X86_VENDOR_INTEL:
1156 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1157 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1164 if (!cpu_has_apic) {
1166 * Over-ride BIOS and try to enable the local APIC only if
1167 * "lapic" specified.
1169 if (!force_enable_local_apic) {
1170 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1171 "you can enable it with \"lapic\"\n");
1175 * Some BIOSes disable the local APIC in the APIC_BASE
1176 * MSR. This can only be done in software for Intel P6 or later
1177 * and AMD K7 (Model > 1) or later.
1179 rdmsr(MSR_IA32_APICBASE, l, h);
1180 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1182 "Local APIC disabled by BIOS -- reenabling.\n");
1183 l &= ~MSR_IA32_APICBASE_BASE;
1184 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1185 wrmsr(MSR_IA32_APICBASE, l, h);
1186 enabled_via_apicbase = 1;
1190 * The APIC feature bit should now be enabled
1193 features = cpuid_edx(1);
1194 if (!(features & (1 << X86_FEATURE_APIC))) {
1195 printk(KERN_WARNING "Could not enable APIC!\n");
1198 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1199 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1201 /* The BIOS may have set up the APIC at some other address */
1202 rdmsr(MSR_IA32_APICBASE, l, h);
1203 if (l & MSR_IA32_APICBASE_ENABLE)
1204 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1206 printk(KERN_INFO "Found and enabled local APIC!\n");
1213 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1218 * init_apic_mappings - initialize APIC mappings
1220 void __init init_apic_mappings(void)
1223 * If no local APIC can be found then set up a fake all
1224 * zeroes page to simulate the local APIC and another
1225 * one for the IO-APIC.
1227 if (!smp_found_config && detect_init_APIC()) {
1228 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1229 apic_phys = __pa(apic_phys);
1231 apic_phys = mp_lapic_addr;
1233 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1234 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1238 * Fetch the APIC ID of the BSP in case we have a
1239 * default configuration (or the MP table is broken).
1241 if (boot_cpu_physical_apicid == -1U)
1242 boot_cpu_physical_apicid = read_apic_id();
1247 * This initializes the IO-APIC and APIC hardware if this is
1251 int apic_version[MAX_APICS];
1253 int __init APIC_init_uniprocessor(void)
1256 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1258 if (!smp_found_config && !cpu_has_apic)
1262 * Complain if the BIOS pretends there is one.
1264 if (!cpu_has_apic &&
1265 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1266 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1267 boot_cpu_physical_apicid);
1268 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1272 verify_local_APIC();
1277 * Hack: In case of kdump, after a crash, kernel might be booting
1278 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1279 * might be zero if read from MP tables. Get it from LAPIC.
1281 #ifdef CONFIG_CRASH_DUMP
1282 boot_cpu_physical_apicid = read_apic_id();
1284 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1288 #ifdef CONFIG_X86_IO_APIC
1289 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1291 localise_nmi_watchdog();
1292 end_local_APIC_setup();
1293 #ifdef CONFIG_X86_IO_APIC
1294 if (smp_found_config)
1295 if (!skip_ioapic_setup && nr_ioapics)
1304 * Local APIC interrupts
1308 * This interrupt should _never_ happen with our APIC/SMP architecture
1310 void smp_spurious_interrupt(struct pt_regs *regs)
1316 * Check if this really is a spurious interrupt and ACK it
1317 * if it is a vectored one. Just in case...
1318 * Spurious interrupts should not be ACKed.
1320 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1321 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1324 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1325 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1326 "should never happen.\n", smp_processor_id());
1327 __get_cpu_var(irq_stat).irq_spurious_count++;
1332 * This interrupt should never happen with our APIC/SMP architecture
1334 void smp_error_interrupt(struct pt_regs *regs)
1336 unsigned long v, v1;
1339 /* First tickle the hardware, only then report what went on. -- REW */
1340 v = apic_read(APIC_ESR);
1341 apic_write(APIC_ESR, 0);
1342 v1 = apic_read(APIC_ESR);
1344 atomic_inc(&irq_err_count);
1346 /* Here is what the APIC error bits mean:
1349 2: Send accept error
1350 3: Receive accept error
1352 5: Send illegal vector
1353 6: Received illegal vector
1354 7: Illegal register address
1356 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1357 smp_processor_id(), v , v1);
1362 void __init smp_intr_init(void)
1365 * IRQ0 must be given a fixed assignment and initialized,
1366 * because it's used before the IO-APIC is set up.
1368 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1371 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1372 * IPI, driven by wakeup.
1374 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1376 /* IPI for invalidation */
1377 alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1379 /* IPI for generic function call */
1380 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1382 /* IPI for single call function */
1383 set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
1384 call_function_single_interrupt);
1389 * Initialize APIC interrupts
1391 void __init apic_intr_init(void)
1396 /* self generated IPI for local APIC timer */
1397 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1399 /* IPI vectors for APIC spurious and error interrupts */
1400 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1401 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1403 /* thermal monitor LVT interrupt */
1404 #ifdef CONFIG_X86_MCE_P4THERMAL
1405 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1410 * connect_bsp_APIC - attach the APIC to the interrupt system
1412 void __init connect_bsp_APIC(void)
1416 * Do not trust the local APIC being empty at bootup.
1420 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1421 * local APIC to INT and NMI lines.
1423 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1424 "enabling APIC mode.\n");
1432 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1433 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1435 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1438 void disconnect_bsp_APIC(int virt_wire_setup)
1442 * Put the board back into PIC mode (has an effect only on
1443 * certain older boards). Note that APIC interrupts, including
1444 * IPIs, won't work beyond this point! The only exception are
1447 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1448 "entering PIC mode.\n");
1452 /* Go back to Virtual Wire compatibility mode */
1453 unsigned long value;
1455 /* For the spurious interrupt use vector F, and enable it */
1456 value = apic_read(APIC_SPIV);
1457 value &= ~APIC_VECTOR_MASK;
1458 value |= APIC_SPIV_APIC_ENABLED;
1460 apic_write(APIC_SPIV, value);
1462 if (!virt_wire_setup) {
1464 * For LVT0 make it edge triggered, active high,
1465 * external and enabled
1467 value = apic_read(APIC_LVT0);
1468 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1469 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1470 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1471 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1472 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1473 apic_write(APIC_LVT0, value);
1476 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1480 * For LVT1 make it edge triggered, active high, nmi and
1483 value = apic_read(APIC_LVT1);
1485 APIC_MODE_MASK | APIC_SEND_PENDING |
1486 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1487 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1488 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1489 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1490 apic_write(APIC_LVT1, value);
1494 unsigned int __cpuinitdata maxcpus = NR_CPUS;
1496 void __cpuinit generic_processor_info(int apicid, int version)
1500 physid_mask_t phys_cpu;
1505 if (version == 0x0) {
1506 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1507 "fixing up to 0x10. (tell your hw vendor)\n",
1511 apic_version[apicid] = version;
1513 phys_cpu = apicid_to_cpu_present(apicid);
1514 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1516 if (num_processors >= NR_CPUS) {
1517 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1518 " Processor ignored.\n", NR_CPUS);
1522 if (num_processors >= maxcpus) {
1523 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1524 " Processor ignored.\n", maxcpus);
1529 cpus_complement(tmp_map, cpu_present_map);
1530 cpu = first_cpu(tmp_map);
1532 if (apicid == boot_cpu_physical_apicid)
1534 * x86_bios_cpu_apicid is required to have processors listed
1535 * in same order as logical cpu numbers. Hence the first
1536 * entry is BSP, and so on.
1540 if (apicid > max_physical_apicid)
1541 max_physical_apicid = apicid;
1544 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1545 * but we need to work other dependencies like SMP_SUSPEND etc
1546 * before this can be done without some confusion.
1547 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1548 * - Ashok Raj <ashok.raj@intel.com>
1550 if (max_physical_apicid >= 8) {
1551 switch (boot_cpu_data.x86_vendor) {
1552 case X86_VENDOR_INTEL:
1553 if (!APIC_XAPIC(version)) {
1557 /* If P4 and above fall through */
1558 case X86_VENDOR_AMD:
1563 /* are we being called early in kernel startup? */
1564 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1565 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1566 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1568 cpu_to_apicid[cpu] = apicid;
1569 bios_cpu_apicid[cpu] = apicid;
1571 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1572 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1575 cpu_set(cpu, cpu_possible_map);
1576 cpu_set(cpu, cpu_present_map);
1586 /* r/w apic fields */
1587 unsigned int apic_id;
1588 unsigned int apic_taskpri;
1589 unsigned int apic_ldr;
1590 unsigned int apic_dfr;
1591 unsigned int apic_spiv;
1592 unsigned int apic_lvtt;
1593 unsigned int apic_lvtpc;
1594 unsigned int apic_lvt0;
1595 unsigned int apic_lvt1;
1596 unsigned int apic_lvterr;
1597 unsigned int apic_tmict;
1598 unsigned int apic_tdcr;
1599 unsigned int apic_thmr;
1602 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1604 unsigned long flags;
1607 if (!apic_pm_state.active)
1610 maxlvt = lapic_get_maxlvt();
1612 apic_pm_state.apic_id = apic_read(APIC_ID);
1613 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1614 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1615 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1616 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1617 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1619 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1620 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1621 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1622 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1623 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1624 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1625 #ifdef CONFIG_X86_MCE_P4THERMAL
1627 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1630 local_irq_save(flags);
1631 disable_local_APIC();
1632 local_irq_restore(flags);
1636 static int lapic_resume(struct sys_device *dev)
1639 unsigned long flags;
1642 if (!apic_pm_state.active)
1645 maxlvt = lapic_get_maxlvt();
1647 local_irq_save(flags);
1650 * Make sure the APICBASE points to the right address
1652 * FIXME! This will be wrong if we ever support suspend on
1653 * SMP! We'll need to do this as part of the CPU restore!
1655 rdmsr(MSR_IA32_APICBASE, l, h);
1656 l &= ~MSR_IA32_APICBASE_BASE;
1657 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1658 wrmsr(MSR_IA32_APICBASE, l, h);
1660 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1661 apic_write(APIC_ID, apic_pm_state.apic_id);
1662 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1663 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1664 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1665 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1666 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1667 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1668 #ifdef CONFIG_X86_MCE_P4THERMAL
1670 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1673 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1674 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1675 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1676 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1677 apic_write(APIC_ESR, 0);
1678 apic_read(APIC_ESR);
1679 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1680 apic_write(APIC_ESR, 0);
1681 apic_read(APIC_ESR);
1682 local_irq_restore(flags);
1687 * This device has no shutdown method - fully functioning local APICs
1688 * are needed on every CPU up until machine_halt/restart/poweroff.
1691 static struct sysdev_class lapic_sysclass = {
1693 .resume = lapic_resume,
1694 .suspend = lapic_suspend,
1697 static struct sys_device device_lapic = {
1699 .cls = &lapic_sysclass,
1702 static void __devinit apic_pm_activate(void)
1704 apic_pm_state.active = 1;
1707 static int __init init_lapic_sysfs(void)
1713 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1715 error = sysdev_class_register(&lapic_sysclass);
1717 error = sysdev_register(&device_lapic);
1720 device_initcall(init_lapic_sysfs);
1722 #else /* CONFIG_PM */
1724 static void apic_pm_activate(void) { }
1726 #endif /* CONFIG_PM */
1729 * APIC command line parameters
1731 static int __init parse_lapic(char *arg)
1733 force_enable_local_apic = 1;
1736 early_param("lapic", parse_lapic);
1738 static int __init parse_nolapic(char *arg)
1741 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1744 early_param("nolapic", parse_nolapic);
1746 static int __init parse_disable_lapic_timer(char *arg)
1748 local_apic_timer_disabled = 1;
1751 early_param("nolapic_timer", parse_disable_lapic_timer);
1753 static int __init parse_lapic_timer_c2_ok(char *arg)
1755 local_apic_timer_c2_ok = 1;
1758 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1760 static int __init apic_set_verbosity(char *str)
1762 if (strcmp("debug", str) == 0)
1763 apic_verbosity = APIC_DEBUG;
1764 else if (strcmp("verbose", str) == 0)
1765 apic_verbosity = APIC_VERBOSE;
1768 __setup("apic=", apic_set_verbosity);
1770 static int __init lapic_insert_resource(void)
1775 /* Put local APIC into the resource map. */
1776 lapic_resource.start = apic_phys;
1777 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1778 insert_resource(&iomem_resource, &lapic_resource);
1784 * need call insert after e820_reserve_resources()
1785 * that is using request_resource
1787 late_initcall(lapic_insert_resource);