2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic;
63 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
64 static int disable_apic_timer __cpuinitdata;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
69 int first_system_vector = 0xfe;
71 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
74 * Debug level, exported for io_apic.c
76 unsigned int apic_verbosity;
80 /* Have we found an MP table */
83 static struct resource lapic_resource = {
85 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
88 static unsigned int calibration_result;
90 static int lapic_next_event(unsigned long delta,
91 struct clock_event_device *evt);
92 static void lapic_timer_setup(enum clock_event_mode mode,
93 struct clock_event_device *evt);
94 static void lapic_timer_broadcast(cpumask_t mask);
95 static void apic_pm_activate(void);
98 * The local apic timer can be used for any function which is CPU local.
100 static struct clock_event_device lapic_clockevent = {
102 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
103 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
105 .set_mode = lapic_timer_setup,
106 .set_next_event = lapic_next_event,
107 .broadcast = lapic_timer_broadcast,
111 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase;
116 static unsigned long apic_phys;
117 unsigned int __cpuinitdata maxcpus = NR_CPUS;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
136 return APIC_INTEGRATED(lapic_get_version());
141 * Check, whether this is a modern or a first generation APIC
143 static int modern_apic(void)
145 /* AMD systems use old APIC versions, so check the CPU */
146 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
147 boot_cpu_data.x86 >= 0xf)
149 return lapic_get_version() >= 0x14;
153 * Paravirt kernels also might be using these below ops. So we still
154 * use generic apic_read()/apic_write(), which might be pointing to different
155 * ops in PARAVIRT case.
157 void xapic_wait_icr_idle(void)
159 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
163 u32 safe_xapic_wait_icr_idle(void)
170 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
174 } while (timeout++ < 1000);
179 void xapic_icr_write(u32 low, u32 id)
181 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
182 apic_write(APIC_ICR, low);
185 u64 xapic_icr_read(void)
189 icr2 = apic_read(APIC_ICR2);
190 icr1 = apic_read(APIC_ICR);
192 return icr1 | ((u64)icr2 << 32);
195 static struct apic_ops xapic_ops = {
196 .read = native_apic_mem_read,
197 .write = native_apic_mem_write,
198 .icr_read = xapic_icr_read,
199 .icr_write = xapic_icr_write,
200 .wait_icr_idle = xapic_wait_icr_idle,
201 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
204 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
205 EXPORT_SYMBOL_GPL(apic_ops);
208 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
210 void __cpuinit enable_NMI_through_LVT0(void)
214 /* unmask and set to NMI */
217 /* Level triggered for 82489DX (32bit mode) */
218 if (!lapic_is_integrated())
219 v |= APIC_LVT_LEVEL_TRIGGER;
221 apic_write(APIC_LVT0, v);
225 * get_physical_broadcast - Get number of physical broadcast IDs
227 int get_physical_broadcast(void)
229 return modern_apic() ? 0xff : 0xf;
233 * lapic_get_maxlvt - get the maximum number of local vector table entries
235 int lapic_get_maxlvt(void)
239 v = apic_read(APIC_LVR);
241 * - we always have APIC integrated on 64bit mode
242 * - 82489DXs do not report # of LVT entries
244 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
251 /* Clock divisor is set to 16 */
252 #define APIC_DIVISOR 16
255 * This function sets up the local APIC timer, with a timeout of
256 * 'clocks' APIC bus clock. During calibration we actually call
257 * this function twice on the boot CPU, once with a bogus timeout
258 * value, second time for real. The other (noncalibrating) CPUs
259 * call this function only once, with the real, calibrated value.
261 * We do reads before writes even if unnecessary, to get around the
262 * P5 APIC double write bug.
264 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
266 unsigned int lvtt_value, tmp_value;
268 lvtt_value = LOCAL_TIMER_VECTOR;
270 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
271 if (!lapic_is_integrated())
272 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
275 lvtt_value |= APIC_LVT_MASKED;
277 apic_write(APIC_LVTT, lvtt_value);
282 tmp_value = apic_read(APIC_TDCR);
283 apic_write(APIC_TDCR,
284 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
288 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
292 * Setup extended LVT, AMD specific (K8, family 10h)
294 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
295 * MCE interrupts are supported. Thus MCE offset must be set to 0.
298 #define APIC_EILVT_LVTOFF_MCE 0
299 #define APIC_EILVT_LVTOFF_IBS 1
301 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
303 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
304 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
309 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
311 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
312 return APIC_EILVT_LVTOFF_MCE;
315 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
317 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
318 return APIC_EILVT_LVTOFF_IBS;
322 * Program the next event, relative to now
324 static int lapic_next_event(unsigned long delta,
325 struct clock_event_device *evt)
327 apic_write(APIC_TMICT, delta);
332 * Setup the lapic timer in periodic or oneshot mode
334 static void lapic_timer_setup(enum clock_event_mode mode,
335 struct clock_event_device *evt)
340 /* Lapic used as dummy for broadcast ? */
341 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
344 local_irq_save(flags);
347 case CLOCK_EVT_MODE_PERIODIC:
348 case CLOCK_EVT_MODE_ONESHOT:
349 __setup_APIC_LVTT(calibration_result,
350 mode != CLOCK_EVT_MODE_PERIODIC, 1);
352 case CLOCK_EVT_MODE_UNUSED:
353 case CLOCK_EVT_MODE_SHUTDOWN:
354 v = apic_read(APIC_LVTT);
355 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
356 apic_write(APIC_LVTT, v);
358 case CLOCK_EVT_MODE_RESUME:
359 /* Nothing to do here */
363 local_irq_restore(flags);
367 * Local APIC timer broadcast function
369 static void lapic_timer_broadcast(cpumask_t mask)
372 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
377 * Setup the local APIC timer for this CPU. Copy the initilized values
378 * of the boot CPU and register the clock event in the framework.
380 static void __devinit setup_APIC_timer(void)
382 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
384 memcpy(levt, &lapic_clockevent, sizeof(*levt));
385 levt->cpumask = cpumask_of_cpu(smp_processor_id());
387 clockevents_register_device(levt);
391 * In this functions we calibrate APIC bus clocks to the external timer.
393 * We want to do the calibration only once since we want to have local timer
394 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
397 * This was previously done by reading the PIT/HPET and waiting for a wrap
398 * around to find out, that a tick has elapsed. I have a box, where the PIT
399 * readout is broken, so it never gets out of the wait loop again. This was
400 * also reported by others.
402 * Monitoring the jiffies value is inaccurate and the clockevents
403 * infrastructure allows us to do a simple substitution of the interrupt
406 * The calibration routine also uses the pm_timer when possible, as the PIT
407 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
408 * back to normal later in the boot process).
411 #define LAPIC_CAL_LOOPS (HZ/10)
413 static __initdata int lapic_cal_loops = -1;
414 static __initdata long lapic_cal_t1, lapic_cal_t2;
415 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
416 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
417 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
420 * Temporary interrupt handler.
422 static void __init lapic_cal_handler(struct clock_event_device *dev)
424 unsigned long long tsc = 0;
425 long tapic = apic_read(APIC_TMCCT);
426 unsigned long pm = acpi_pm_read_early();
431 switch (lapic_cal_loops++) {
433 lapic_cal_t1 = tapic;
434 lapic_cal_tsc1 = tsc;
436 lapic_cal_j1 = jiffies;
439 case LAPIC_CAL_LOOPS:
440 lapic_cal_t2 = tapic;
441 lapic_cal_tsc2 = tsc;
442 if (pm < lapic_cal_pm1)
443 pm += ACPI_PM_OVRRUN;
445 lapic_cal_j2 = jiffies;
450 static int __init calibrate_APIC_clock(void)
452 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
453 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
454 const long pm_thresh = pm_100ms/100;
455 void (*real_handler)(struct clock_event_device *dev);
456 unsigned long deltaj;
458 int pm_referenced = 0;
462 /* Replace the global interrupt handler */
463 real_handler = global_clock_event->event_handler;
464 global_clock_event->event_handler = lapic_cal_handler;
467 * Setup the APIC counter to 1e9. There is no way the lapic
468 * can underflow in the 100ms detection time frame
470 __setup_APIC_LVTT(1000000000, 0, 0);
472 /* Let the interrupts run */
475 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
480 /* Restore the real event handler */
481 global_clock_event->event_handler = real_handler;
483 /* Build delta t1-t2 as apic timer counts down */
484 delta = lapic_cal_t1 - lapic_cal_t2;
485 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
487 /* Check, if the PM timer is available */
488 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
489 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
495 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
497 if (deltapm > (pm_100ms - pm_thresh) &&
498 deltapm < (pm_100ms + pm_thresh)) {
499 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
501 res = (((u64) deltapm) * mult) >> 22;
502 do_div(res, 1000000);
503 printk(KERN_WARNING "APIC calibration not consistent "
504 "with PM Timer: %ldms instead of 100ms\n",
506 /* Correct the lapic counter value */
507 res = (((u64) delta) * pm_100ms);
508 do_div(res, deltapm);
509 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
510 "%lu (%ld)\n", (unsigned long) res, delta);
516 /* Calculate the scaled math multiplication factor */
517 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
518 lapic_clockevent.shift);
519 lapic_clockevent.max_delta_ns =
520 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
521 lapic_clockevent.min_delta_ns =
522 clockevent_delta2ns(0xF, &lapic_clockevent);
524 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
526 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
527 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
528 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
532 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
533 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
535 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
536 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
539 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
541 calibration_result / (1000000 / HZ),
542 calibration_result % (1000000 / HZ));
545 * Do a sanity check on the APIC calibration result
547 if (calibration_result < (1000000 / HZ)) {
550 "APIC frequency too slow, disabling apic timer\n");
554 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
556 /* We trust the pm timer based calibration */
557 if (!pm_referenced) {
558 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
561 * Setup the apic timer manually
563 levt->event_handler = lapic_cal_handler;
564 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
565 lapic_cal_loops = -1;
567 /* Let the interrupts run */
570 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
575 /* Stop the lapic timer */
576 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
581 deltaj = lapic_cal_j2 - lapic_cal_j1;
582 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
584 /* Check, if the jiffies result is consistent */
585 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
586 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
588 levt->features |= CLOCK_EVT_FEAT_DUMMY;
592 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
594 "APIC timer disabled due to verification failure.\n");
602 * Setup the boot APIC
604 * Calibrate and verify the result.
606 void __init setup_boot_APIC_clock(void)
609 * The local apic timer can be disabled via the kernel
610 * commandline or from the CPU detection code. Register the lapic
611 * timer as a dummy clock event source on SMP systems, so the
612 * broadcast mechanism is used. On UP systems simply ignore it.
614 if (disable_apic_timer) {
615 /* No broadcast on UP ! */
616 if (num_possible_cpus() > 1) {
617 lapic_clockevent.mult = 1;
623 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
624 "calibrating APIC timer ...\n");
626 if (calibrate_APIC_clock()) {
627 /* No broadcast on UP ! */
628 if (num_possible_cpus() > 1)
634 * If nmi_watchdog is set to IO_APIC, we need the
635 * PIT/HPET going. Otherwise register lapic as a dummy
638 if (nmi_watchdog != NMI_IO_APIC)
639 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
641 printk(KERN_WARNING "APIC timer registered as dummy,"
642 " due to nmi_watchdog=%d!\n", nmi_watchdog);
644 /* Setup the lapic or request the broadcast */
648 void __devinit setup_secondary_APIC_clock(void)
654 * The guts of the apic timer interrupt
656 static void local_apic_timer_interrupt(void)
658 int cpu = smp_processor_id();
659 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
662 * Normally we should not be here till LAPIC has been initialized but
663 * in some cases like kdump, its possible that there is a pending LAPIC
664 * timer interrupt from previous kernel's context and is delivered in
665 * new kernel the moment interrupts are enabled.
667 * Interrupts are enabled early and LAPIC is setup much later, hence
668 * its possible that when we get here evt->event_handler is NULL.
669 * Check for event_handler being NULL and discard the interrupt as
672 if (!evt->event_handler) {
674 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
676 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
681 * the NMI deadlock-detector uses this.
683 per_cpu(irq_stat, cpu).apic_timer_irqs++;
685 evt->event_handler(evt);
689 * Local APIC timer interrupt. This is the most natural way for doing
690 * local interrupts, but local timer interrupts can be emulated by
691 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
693 * [ if a single-CPU system runs an SMP kernel then we call the local
694 * interrupt as well. Thus we cannot inline the local irq ... ]
696 void smp_apic_timer_interrupt(struct pt_regs *regs)
698 struct pt_regs *old_regs = set_irq_regs(regs);
701 * NOTE! We'd better ACK the irq immediately,
702 * because timer handling can be slow.
706 * update_process_times() expects us to have done irq_enter().
707 * Besides, if we don't timer interrupts ignore the global
708 * interrupt lock, which is the WrongThing (tm) to do.
711 local_apic_timer_interrupt();
714 set_irq_regs(old_regs);
717 int setup_profiling_timer(unsigned int multiplier)
723 * Local APIC start and shutdown
727 * clear_local_APIC - shutdown the local APIC
729 * This is called, when a CPU is disabled and before rebooting, so the state of
730 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
731 * leftovers during boot.
733 void clear_local_APIC(void)
738 /* APIC hasn't been mapped yet */
742 maxlvt = lapic_get_maxlvt();
744 * Masking an LVT entry can trigger a local APIC error
745 * if the vector is zero. Mask LVTERR first to prevent this.
748 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
749 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
752 * Careful: we have to set masks only first to deassert
753 * any level-triggered sources.
755 v = apic_read(APIC_LVTT);
756 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
757 v = apic_read(APIC_LVT0);
758 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
759 v = apic_read(APIC_LVT1);
760 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
762 v = apic_read(APIC_LVTPC);
763 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
766 /* lets not touch this if we didn't frob it */
767 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
769 v = apic_read(APIC_LVTTHMR);
770 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
774 * Clean APIC state for other OSs:
776 apic_write(APIC_LVTT, APIC_LVT_MASKED);
777 apic_write(APIC_LVT0, APIC_LVT_MASKED);
778 apic_write(APIC_LVT1, APIC_LVT_MASKED);
780 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
782 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
784 /* Integrated APIC (!82489DX) ? */
785 if (lapic_is_integrated()) {
787 /* Clear ESR due to Pentium errata 3AP and 11AP */
788 apic_write(APIC_ESR, 0);
794 * disable_local_APIC - clear and disable the local APIC
796 void disable_local_APIC(void)
803 * Disable APIC (implies clearing of registers
806 value = apic_read(APIC_SPIV);
807 value &= ~APIC_SPIV_APIC_ENABLED;
808 apic_write(APIC_SPIV, value);
811 * When LAPIC was disabled by the BIOS and enabled by the kernel,
812 * restore the disabled state.
814 if (enabled_via_apicbase) {
817 rdmsr(MSR_IA32_APICBASE, l, h);
818 l &= ~MSR_IA32_APICBASE_ENABLE;
819 wrmsr(MSR_IA32_APICBASE, l, h);
824 * If Linux enabled the LAPIC against the BIOS default disable it down before
825 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
826 * not power-off. Additionally clear all LVT entries before disable_local_APIC
827 * for the case where Linux didn't enable the LAPIC.
829 void lapic_shutdown(void)
836 local_irq_save(flags);
838 if (enabled_via_apicbase)
839 disable_local_APIC();
843 local_irq_restore(flags);
847 * This is to verify that we're looking at a real local APIC.
848 * Check these against your board if the CPUs aren't getting
849 * started for no apparent reason.
851 int __init verify_local_APIC(void)
853 unsigned int reg0, reg1;
856 * The version register is read-only in a real APIC.
858 reg0 = apic_read(APIC_LVR);
859 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
860 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
861 reg1 = apic_read(APIC_LVR);
862 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
865 * The two version reads above should print the same
866 * numbers. If the second one is different, then we
867 * poke at a non-APIC.
873 * Check if the version looks reasonably.
875 reg1 = GET_APIC_VERSION(reg0);
876 if (reg1 == 0x00 || reg1 == 0xff)
878 reg1 = lapic_get_maxlvt();
879 if (reg1 < 0x02 || reg1 == 0xff)
883 * The ID register is read/write in a real APIC.
885 reg0 = apic_read(APIC_ID);
886 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
887 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
888 reg1 = apic_read(APIC_ID);
889 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
890 apic_write(APIC_ID, reg0);
891 if (reg1 != (reg0 ^ APIC_ID_MASK))
895 * The next two are just to see if we have sane values.
896 * They're only really relevant if we're in Virtual Wire
897 * compatibility mode, but most boxes are anymore.
899 reg0 = apic_read(APIC_LVT0);
900 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
901 reg1 = apic_read(APIC_LVT1);
902 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
908 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
910 void __init sync_Arb_IDs(void)
913 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
916 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
922 apic_wait_icr_idle();
924 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
925 apic_write(APIC_ICR, APIC_DEST_ALLINC |
926 APIC_INT_LEVELTRIG | APIC_DM_INIT);
930 * An initial setup of the virtual wire mode.
932 void __init init_bsp_APIC(void)
937 * Don't do the setup now if we have a SMP BIOS as the
938 * through-I/O-APIC virtual wire mode might be active.
940 if (smp_found_config || !cpu_has_apic)
944 * Do not trust the local APIC being empty at bootup.
951 value = apic_read(APIC_SPIV);
952 value &= ~APIC_VECTOR_MASK;
953 value |= APIC_SPIV_APIC_ENABLED;
956 /* This bit is reserved on P4/Xeon and should be cleared */
957 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
958 (boot_cpu_data.x86 == 15))
959 value &= ~APIC_SPIV_FOCUS_DISABLED;
962 value |= APIC_SPIV_FOCUS_DISABLED;
963 value |= SPURIOUS_APIC_VECTOR;
964 apic_write(APIC_SPIV, value);
967 * Set up the virtual wire mode.
969 apic_write(APIC_LVT0, APIC_DM_EXTINT);
971 if (!lapic_is_integrated()) /* 82489DX */
972 value |= APIC_LVT_LEVEL_TRIGGER;
973 apic_write(APIC_LVT1, value);
976 static void __cpuinit lapic_setup_esr(void)
978 unsigned long oldvalue, value, maxlvt;
979 if (lapic_is_integrated() && !esr_disable) {
981 maxlvt = lapic_get_maxlvt();
982 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
983 apic_write(APIC_ESR, 0);
984 oldvalue = apic_read(APIC_ESR);
986 /* enables sending errors */
987 value = ERROR_APIC_VECTOR;
988 apic_write(APIC_LVTERR, value);
990 * spec says clear errors after enabling vector.
993 apic_write(APIC_ESR, 0);
994 value = apic_read(APIC_ESR);
995 if (value != oldvalue)
996 apic_printk(APIC_VERBOSE, "ESR value before enabling "
997 "vector: 0x%08lx after: 0x%08lx\n",
1002 * Something untraceable is creating bad interrupts on
1003 * secondary quads ... for the moment, just leave the
1004 * ESR disabled - we can't do anything useful with the
1005 * errors anyway - mbligh
1007 printk(KERN_INFO "Leaving ESR disabled.\n");
1009 printk(KERN_INFO "No ESR for 82489DX.\n");
1015 * setup_local_APIC - setup the local APIC
1017 void __cpuinit setup_local_APIC(void)
1019 unsigned long value, integrated;
1022 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1024 apic_write(APIC_ESR, 0);
1025 apic_write(APIC_ESR, 0);
1026 apic_write(APIC_ESR, 0);
1027 apic_write(APIC_ESR, 0);
1030 integrated = lapic_is_integrated();
1033 * Double-check whether this APIC is really registered.
1035 if (!apic_id_registered())
1039 * Intel recommends to set DFR, LDR and TPR before enabling
1040 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1041 * document number 292116). So here it goes...
1046 * Set Task Priority to 'accept all'. We never change this
1049 value = apic_read(APIC_TASKPRI);
1050 value &= ~APIC_TPRI_MASK;
1051 apic_write(APIC_TASKPRI, value);
1054 * After a crash, we no longer service the interrupts and a pending
1055 * interrupt from previous kernel might still have ISR bit set.
1057 * Most probably by now CPU has serviced that pending interrupt and
1058 * it might not have done the ack_APIC_irq() because it thought,
1059 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1060 * does not clear the ISR bit and cpu thinks it has already serivced
1061 * the interrupt. Hence a vector might get locked. It was noticed
1062 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1064 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1065 value = apic_read(APIC_ISR + i*0x10);
1066 for (j = 31; j >= 0; j--) {
1073 * Now that we are all set up, enable the APIC
1075 value = apic_read(APIC_SPIV);
1076 value &= ~APIC_VECTOR_MASK;
1080 value |= APIC_SPIV_APIC_ENABLED;
1083 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1084 * certain networking cards. If high frequency interrupts are
1085 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1086 * entry is masked/unmasked at a high rate as well then sooner or
1087 * later IOAPIC line gets 'stuck', no more interrupts are received
1088 * from the device. If focus CPU is disabled then the hang goes
1091 * [ This bug can be reproduced easily with a level-triggered
1092 * PCI Ne2000 networking cards and PII/PIII processors, dual
1096 * Actually disabling the focus CPU check just makes the hang less
1097 * frequent as it makes the interrupt distributon model be more
1098 * like LRU than MRU (the short-term load is more even across CPUs).
1099 * See also the comment in end_level_ioapic_irq(). --macro
1102 /* Enable focus processor (bit==0) */
1103 value &= ~APIC_SPIV_FOCUS_DISABLED;
1106 * Set spurious IRQ vector
1108 value |= SPURIOUS_APIC_VECTOR;
1109 apic_write(APIC_SPIV, value);
1112 * Set up LVT0, LVT1:
1114 * set up through-local-APIC on the BP's LINT0. This is not
1115 * strictly necessary in pure symmetric-IO mode, but sometimes
1116 * we delegate interrupts to the 8259A.
1119 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1121 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1122 if (!smp_processor_id() && (pic_mode || !value)) {
1123 value = APIC_DM_EXTINT;
1124 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1125 smp_processor_id());
1127 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1128 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1129 smp_processor_id());
1131 apic_write(APIC_LVT0, value);
1134 * only the BP should see the LINT1 NMI signal, obviously.
1136 if (!smp_processor_id())
1137 value = APIC_DM_NMI;
1139 value = APIC_DM_NMI | APIC_LVT_MASKED;
1140 if (!integrated) /* 82489DX */
1141 value |= APIC_LVT_LEVEL_TRIGGER;
1142 apic_write(APIC_LVT1, value);
1145 void __cpuinit end_local_APIC_setup(void)
1147 unsigned long value;
1150 /* Disable the local apic timer */
1151 value = apic_read(APIC_LVTT);
1152 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1153 apic_write(APIC_LVTT, value);
1155 setup_apic_nmi_watchdog(NULL);
1160 * Detect and initialize APIC
1162 static int __init detect_init_APIC(void)
1166 /* Disabled by kernel option? */
1170 switch (boot_cpu_data.x86_vendor) {
1171 case X86_VENDOR_AMD:
1172 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1173 (boot_cpu_data.x86 == 15))
1176 case X86_VENDOR_INTEL:
1177 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1178 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1185 if (!cpu_has_apic) {
1187 * Over-ride BIOS and try to enable the local APIC only if
1188 * "lapic" specified.
1190 if (!force_enable_local_apic) {
1191 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1192 "you can enable it with \"lapic\"\n");
1196 * Some BIOSes disable the local APIC in the APIC_BASE
1197 * MSR. This can only be done in software for Intel P6 or later
1198 * and AMD K7 (Model > 1) or later.
1200 rdmsr(MSR_IA32_APICBASE, l, h);
1201 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1203 "Local APIC disabled by BIOS -- reenabling.\n");
1204 l &= ~MSR_IA32_APICBASE_BASE;
1205 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1206 wrmsr(MSR_IA32_APICBASE, l, h);
1207 enabled_via_apicbase = 1;
1211 * The APIC feature bit should now be enabled
1214 features = cpuid_edx(1);
1215 if (!(features & (1 << X86_FEATURE_APIC))) {
1216 printk(KERN_WARNING "Could not enable APIC!\n");
1219 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1220 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1222 /* The BIOS may have set up the APIC at some other address */
1223 rdmsr(MSR_IA32_APICBASE, l, h);
1224 if (l & MSR_IA32_APICBASE_ENABLE)
1225 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1227 printk(KERN_INFO "Found and enabled local APIC!\n");
1234 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1239 * init_apic_mappings - initialize APIC mappings
1241 void __init init_apic_mappings(void)
1244 * If no local APIC can be found then set up a fake all
1245 * zeroes page to simulate the local APIC and another
1246 * one for the IO-APIC.
1248 if (!smp_found_config && detect_init_APIC()) {
1249 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1250 apic_phys = __pa(apic_phys);
1252 apic_phys = mp_lapic_addr;
1254 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1255 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1259 * Fetch the APIC ID of the BSP in case we have a
1260 * default configuration (or the MP table is broken).
1262 if (boot_cpu_physical_apicid == -1U)
1263 boot_cpu_physical_apicid = read_apic_id();
1268 * This initializes the IO-APIC and APIC hardware if this is
1272 int apic_version[MAX_APICS];
1274 int __init APIC_init_uniprocessor(void)
1276 if (!smp_found_config && !cpu_has_apic)
1280 * Complain if the BIOS pretends there is one.
1282 if (!cpu_has_apic &&
1283 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1284 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1285 boot_cpu_physical_apicid);
1286 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1290 verify_local_APIC();
1295 * Hack: In case of kdump, after a crash, kernel might be booting
1296 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1297 * might be zero if read from MP tables. Get it from LAPIC.
1299 #ifdef CONFIG_CRASH_DUMP
1300 boot_cpu_physical_apicid = read_apic_id();
1302 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1306 #ifdef CONFIG_X86_IO_APIC
1307 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1309 localise_nmi_watchdog();
1310 end_local_APIC_setup();
1311 #ifdef CONFIG_X86_IO_APIC
1312 if (smp_found_config)
1313 if (!skip_ioapic_setup && nr_ioapics)
1322 * Local APIC interrupts
1326 * This interrupt should _never_ happen with our APIC/SMP architecture
1328 void smp_spurious_interrupt(struct pt_regs *regs)
1334 * Check if this really is a spurious interrupt and ACK it
1335 * if it is a vectored one. Just in case...
1336 * Spurious interrupts should not be ACKed.
1338 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1339 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1342 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1343 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1344 "should never happen.\n", smp_processor_id());
1345 __get_cpu_var(irq_stat).irq_spurious_count++;
1350 * This interrupt should never happen with our APIC/SMP architecture
1352 void smp_error_interrupt(struct pt_regs *regs)
1354 unsigned long v, v1;
1357 /* First tickle the hardware, only then report what went on. -- REW */
1358 v = apic_read(APIC_ESR);
1359 apic_write(APIC_ESR, 0);
1360 v1 = apic_read(APIC_ESR);
1362 atomic_inc(&irq_err_count);
1364 /* Here is what the APIC error bits mean:
1367 2: Send accept error
1368 3: Receive accept error
1370 5: Send illegal vector
1371 6: Received illegal vector
1372 7: Illegal register address
1374 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1375 smp_processor_id(), v , v1);
1380 * connect_bsp_APIC - attach the APIC to the interrupt system
1382 void __init connect_bsp_APIC(void)
1386 * Do not trust the local APIC being empty at bootup.
1390 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1391 * local APIC to INT and NMI lines.
1393 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1394 "enabling APIC mode.\n");
1402 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1403 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1405 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1408 void disconnect_bsp_APIC(int virt_wire_setup)
1412 * Put the board back into PIC mode (has an effect only on
1413 * certain older boards). Note that APIC interrupts, including
1414 * IPIs, won't work beyond this point! The only exception are
1417 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1418 "entering PIC mode.\n");
1422 /* Go back to Virtual Wire compatibility mode */
1423 unsigned long value;
1425 /* For the spurious interrupt use vector F, and enable it */
1426 value = apic_read(APIC_SPIV);
1427 value &= ~APIC_VECTOR_MASK;
1428 value |= APIC_SPIV_APIC_ENABLED;
1430 apic_write(APIC_SPIV, value);
1432 if (!virt_wire_setup) {
1434 * For LVT0 make it edge triggered, active high,
1435 * external and enabled
1437 value = apic_read(APIC_LVT0);
1438 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1439 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1440 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1441 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1442 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1443 apic_write(APIC_LVT0, value);
1446 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1450 * For LVT1 make it edge triggered, active high, nmi and
1453 value = apic_read(APIC_LVT1);
1455 APIC_MODE_MASK | APIC_SEND_PENDING |
1456 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1457 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1458 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1459 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1460 apic_write(APIC_LVT1, value);
1464 void __cpuinit generic_processor_info(int apicid, int version)
1468 physid_mask_t phys_cpu;
1473 if (version == 0x0) {
1474 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1475 "fixing up to 0x10. (tell your hw vendor)\n",
1479 apic_version[apicid] = version;
1481 phys_cpu = apicid_to_cpu_present(apicid);
1482 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1484 if (num_processors >= NR_CPUS) {
1485 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1486 " Processor ignored.\n", NR_CPUS);
1490 if (num_processors >= maxcpus) {
1491 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1492 " Processor ignored.\n", maxcpus);
1497 cpus_complement(tmp_map, cpu_present_map);
1498 cpu = first_cpu(tmp_map);
1500 if (apicid == boot_cpu_physical_apicid)
1502 * x86_bios_cpu_apicid is required to have processors listed
1503 * in same order as logical cpu numbers. Hence the first
1504 * entry is BSP, and so on.
1508 if (apicid > max_physical_apicid)
1509 max_physical_apicid = apicid;
1512 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1513 * but we need to work other dependencies like SMP_SUSPEND etc
1514 * before this can be done without some confusion.
1515 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1516 * - Ashok Raj <ashok.raj@intel.com>
1518 if (max_physical_apicid >= 8) {
1519 switch (boot_cpu_data.x86_vendor) {
1520 case X86_VENDOR_INTEL:
1521 if (!APIC_XAPIC(version)) {
1525 /* If P4 and above fall through */
1526 case X86_VENDOR_AMD:
1531 /* are we being called early in kernel startup? */
1532 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1533 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1534 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1536 cpu_to_apicid[cpu] = apicid;
1537 bios_cpu_apicid[cpu] = apicid;
1539 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1540 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1543 cpu_set(cpu, cpu_possible_map);
1544 cpu_set(cpu, cpu_present_map);
1554 * 'active' is true if the local APIC was enabled by us and
1555 * not the BIOS; this signifies that we are also responsible
1556 * for disabling it before entering apm/acpi suspend
1559 /* r/w apic fields */
1560 unsigned int apic_id;
1561 unsigned int apic_taskpri;
1562 unsigned int apic_ldr;
1563 unsigned int apic_dfr;
1564 unsigned int apic_spiv;
1565 unsigned int apic_lvtt;
1566 unsigned int apic_lvtpc;
1567 unsigned int apic_lvt0;
1568 unsigned int apic_lvt1;
1569 unsigned int apic_lvterr;
1570 unsigned int apic_tmict;
1571 unsigned int apic_tdcr;
1572 unsigned int apic_thmr;
1575 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1577 unsigned long flags;
1580 if (!apic_pm_state.active)
1583 maxlvt = lapic_get_maxlvt();
1585 apic_pm_state.apic_id = apic_read(APIC_ID);
1586 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1587 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1588 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1589 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1590 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1592 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1593 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1594 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1595 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1596 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1597 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1598 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1600 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1603 local_irq_save(flags);
1604 disable_local_APIC();
1605 local_irq_restore(flags);
1609 static int lapic_resume(struct sys_device *dev)
1612 unsigned long flags;
1615 if (!apic_pm_state.active)
1618 maxlvt = lapic_get_maxlvt();
1620 local_irq_save(flags);
1622 #ifdef CONFIG_X86_64
1628 * Make sure the APICBASE points to the right address
1630 * FIXME! This will be wrong if we ever support suspend on
1631 * SMP! We'll need to do this as part of the CPU restore!
1633 rdmsr(MSR_IA32_APICBASE, l, h);
1634 l &= ~MSR_IA32_APICBASE_BASE;
1635 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1636 wrmsr(MSR_IA32_APICBASE, l, h);
1638 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1639 apic_write(APIC_ID, apic_pm_state.apic_id);
1640 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1641 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1642 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1643 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1644 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1645 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1646 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1648 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1651 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1652 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1653 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1654 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1655 apic_write(APIC_ESR, 0);
1656 apic_read(APIC_ESR);
1657 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1658 apic_write(APIC_ESR, 0);
1659 apic_read(APIC_ESR);
1661 local_irq_restore(flags);
1667 * This device has no shutdown method - fully functioning local APICs
1668 * are needed on every CPU up until machine_halt/restart/poweroff.
1671 static struct sysdev_class lapic_sysclass = {
1673 .resume = lapic_resume,
1674 .suspend = lapic_suspend,
1677 static struct sys_device device_lapic = {
1679 .cls = &lapic_sysclass,
1682 static void __devinit apic_pm_activate(void)
1684 apic_pm_state.active = 1;
1687 static int __init init_lapic_sysfs(void)
1693 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1695 error = sysdev_class_register(&lapic_sysclass);
1697 error = sysdev_register(&device_lapic);
1700 device_initcall(init_lapic_sysfs);
1702 #else /* CONFIG_PM */
1704 static void apic_pm_activate(void) { }
1706 #endif /* CONFIG_PM */
1709 * APIC command line parameters
1711 static int __init parse_lapic(char *arg)
1713 force_enable_local_apic = 1;
1716 early_param("lapic", parse_lapic);
1718 static int __init parse_nolapic(char *arg)
1721 setup_clear_cpu_cap(X86_FEATURE_APIC);
1724 early_param("nolapic", parse_nolapic);
1726 static int __init parse_disable_apic_timer(char *arg)
1728 disable_apic_timer = 1;
1731 early_param("noapictimer", parse_disable_apic_timer);
1733 static int __init parse_nolapic_timer(char *arg)
1735 disable_apic_timer = 1;
1738 early_param("nolapic_timer", parse_nolapic_timer);
1740 static int __init parse_lapic_timer_c2_ok(char *arg)
1742 local_apic_timer_c2_ok = 1;
1745 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1747 static int __init apic_set_verbosity(char *arg)
1752 if (strcmp(arg, "debug") == 0)
1753 apic_verbosity = APIC_DEBUG;
1754 else if (strcmp(arg, "verbose") == 0)
1755 apic_verbosity = APIC_VERBOSE;
1759 early_param("apic", apic_set_verbosity);
1761 static int __init lapic_insert_resource(void)
1766 /* Put local APIC into the resource map. */
1767 lapic_resource.start = apic_phys;
1768 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1769 insert_resource(&iomem_resource, &lapic_resource);
1775 * need call insert after e820_reserve_resources()
1776 * that is using request_resource
1778 late_initcall(lapic_insert_resource);