2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
71 int first_system_vector = 0xfe;
73 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
76 * Debug level, exported for io_apic.c
82 /* Have we found an MP table */
85 static unsigned int calibration_result;
87 static int lapic_next_event(unsigned long delta,
88 struct clock_event_device *evt);
89 static void lapic_timer_setup(enum clock_event_mode mode,
90 struct clock_event_device *evt);
91 static void lapic_timer_broadcast(cpumask_t mask);
92 static void apic_pm_activate(void);
95 * The local apic timer can be used for any function which is CPU local.
97 static struct clock_event_device lapic_clockevent = {
99 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
100 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
102 .set_mode = lapic_timer_setup,
103 .set_next_event = lapic_next_event,
104 .broadcast = lapic_timer_broadcast,
108 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
110 /* Local APIC was disabled by the BIOS and enabled by the kernel */
111 static int enabled_via_apicbase;
113 static unsigned long apic_phys;
116 * Get the LAPIC version
118 static inline int lapic_get_version(void)
120 return GET_APIC_VERSION(apic_read(APIC_LVR));
124 * Check, if the APIC is integrated or a separate chip
126 static inline int lapic_is_integrated(void)
128 return APIC_INTEGRATED(lapic_get_version());
132 * Check, whether this is a modern or a first generation APIC
134 static int modern_apic(void)
136 /* AMD systems use old APIC versions, so check the CPU */
137 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
138 boot_cpu_data.x86 >= 0xf)
140 return lapic_get_version() >= 0x14;
143 void apic_wait_icr_idle(void)
145 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
149 u32 safe_apic_wait_icr_idle(void)
156 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
160 } while (timeout++ < 1000);
166 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
168 void __cpuinit enable_NMI_through_LVT0(void)
170 unsigned int v = APIC_DM_NMI;
172 /* Level triggered for 82489DX */
173 if (!lapic_is_integrated())
174 v |= APIC_LVT_LEVEL_TRIGGER;
175 apic_write_around(APIC_LVT0, v);
179 * get_physical_broadcast - Get number of physical broadcast IDs
181 int get_physical_broadcast(void)
183 return modern_apic() ? 0xff : 0xf;
187 * lapic_get_maxlvt - get the maximum number of local vector table entries
189 int lapic_get_maxlvt(void)
191 unsigned int v = apic_read(APIC_LVR);
193 /* 82489DXs do not report # of LVT entries. */
194 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
201 /* Clock divisor is set to 16 */
202 #define APIC_DIVISOR 16
205 * This function sets up the local APIC timer, with a timeout of
206 * 'clocks' APIC bus clock. During calibration we actually call
207 * this function twice on the boot CPU, once with a bogus timeout
208 * value, second time for real. The other (noncalibrating) CPUs
209 * call this function only once, with the real, calibrated value.
211 * We do reads before writes even if unnecessary, to get around the
212 * P5 APIC double write bug.
214 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
216 unsigned int lvtt_value, tmp_value;
218 lvtt_value = LOCAL_TIMER_VECTOR;
220 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
221 if (!lapic_is_integrated())
222 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
225 lvtt_value |= APIC_LVT_MASKED;
227 apic_write_around(APIC_LVTT, lvtt_value);
232 tmp_value = apic_read(APIC_TDCR);
233 apic_write_around(APIC_TDCR, (tmp_value
234 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
238 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
242 * Program the next event, relative to now
244 static int lapic_next_event(unsigned long delta,
245 struct clock_event_device *evt)
247 apic_write_around(APIC_TMICT, delta);
252 * Setup the lapic timer in periodic or oneshot mode
254 static void lapic_timer_setup(enum clock_event_mode mode,
255 struct clock_event_device *evt)
260 /* Lapic used for broadcast ? */
261 if (!local_apic_timer_verify_ok)
264 local_irq_save(flags);
267 case CLOCK_EVT_MODE_PERIODIC:
268 case CLOCK_EVT_MODE_ONESHOT:
269 __setup_APIC_LVTT(calibration_result,
270 mode != CLOCK_EVT_MODE_PERIODIC, 1);
272 case CLOCK_EVT_MODE_UNUSED:
273 case CLOCK_EVT_MODE_SHUTDOWN:
274 v = apic_read(APIC_LVTT);
275 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
276 apic_write_around(APIC_LVTT, v);
278 case CLOCK_EVT_MODE_RESUME:
279 /* Nothing to do here */
283 local_irq_restore(flags);
287 * Local APIC timer broadcast function
289 static void lapic_timer_broadcast(cpumask_t mask)
292 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
297 * Setup the local APIC timer for this CPU. Copy the initilized values
298 * of the boot CPU and register the clock event in the framework.
300 static void __devinit setup_APIC_timer(void)
302 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
304 memcpy(levt, &lapic_clockevent, sizeof(*levt));
305 levt->cpumask = cpumask_of_cpu(smp_processor_id());
307 clockevents_register_device(levt);
311 * In this functions we calibrate APIC bus clocks to the external timer.
313 * We want to do the calibration only once since we want to have local timer
314 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
317 * This was previously done by reading the PIT/HPET and waiting for a wrap
318 * around to find out, that a tick has elapsed. I have a box, where the PIT
319 * readout is broken, so it never gets out of the wait loop again. This was
320 * also reported by others.
322 * Monitoring the jiffies value is inaccurate and the clockevents
323 * infrastructure allows us to do a simple substitution of the interrupt
326 * The calibration routine also uses the pm_timer when possible, as the PIT
327 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
328 * back to normal later in the boot process).
331 #define LAPIC_CAL_LOOPS (HZ/10)
333 static __initdata int lapic_cal_loops = -1;
334 static __initdata long lapic_cal_t1, lapic_cal_t2;
335 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
336 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
337 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
340 * Temporary interrupt handler.
342 static void __init lapic_cal_handler(struct clock_event_device *dev)
344 unsigned long long tsc = 0;
345 long tapic = apic_read(APIC_TMCCT);
346 unsigned long pm = acpi_pm_read_early();
351 switch (lapic_cal_loops++) {
353 lapic_cal_t1 = tapic;
354 lapic_cal_tsc1 = tsc;
356 lapic_cal_j1 = jiffies;
359 case LAPIC_CAL_LOOPS:
360 lapic_cal_t2 = tapic;
361 lapic_cal_tsc2 = tsc;
362 if (pm < lapic_cal_pm1)
363 pm += ACPI_PM_OVRRUN;
365 lapic_cal_j2 = jiffies;
371 * Setup the boot APIC
373 * Calibrate and verify the result.
375 void __init setup_boot_APIC_clock(void)
377 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
378 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
379 const long pm_thresh = pm_100ms/100;
380 void (*real_handler)(struct clock_event_device *dev);
381 unsigned long deltaj;
383 int pm_referenced = 0;
386 * The local apic timer can be disabled via the kernel
387 * commandline or from the CPU detection code. Register the lapic
388 * timer as a dummy clock event source on SMP systems, so the
389 * broadcast mechanism is used. On UP systems simply ignore it.
391 if (local_apic_timer_disabled) {
392 /* No broadcast on UP ! */
393 if (num_possible_cpus() > 1) {
394 lapic_clockevent.mult = 1;
400 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
401 "calibrating APIC timer ...\n");
405 /* Replace the global interrupt handler */
406 real_handler = global_clock_event->event_handler;
407 global_clock_event->event_handler = lapic_cal_handler;
410 * Setup the APIC counter to 1e9. There is no way the lapic
411 * can underflow in the 100ms detection time frame
413 __setup_APIC_LVTT(1000000000, 0, 0);
415 /* Let the interrupts run */
418 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
423 /* Restore the real event handler */
424 global_clock_event->event_handler = real_handler;
426 /* Build delta t1-t2 as apic timer counts down */
427 delta = lapic_cal_t1 - lapic_cal_t2;
428 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
430 /* Check, if the PM timer is available */
431 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
432 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
438 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
440 if (deltapm > (pm_100ms - pm_thresh) &&
441 deltapm < (pm_100ms + pm_thresh)) {
442 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
444 res = (((u64) deltapm) * mult) >> 22;
445 do_div(res, 1000000);
446 printk(KERN_WARNING "APIC calibration not consistent "
447 "with PM Timer: %ldms instead of 100ms\n",
449 /* Correct the lapic counter value */
450 res = (((u64) delta) * pm_100ms);
451 do_div(res, deltapm);
452 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
453 "%lu (%ld)\n", (unsigned long) res, delta);
459 /* Calculate the scaled math multiplication factor */
460 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
461 lapic_clockevent.shift);
462 lapic_clockevent.max_delta_ns =
463 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
464 lapic_clockevent.min_delta_ns =
465 clockevent_delta2ns(0xF, &lapic_clockevent);
467 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
469 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
470 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
471 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
475 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
476 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
478 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
479 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
482 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
484 calibration_result / (1000000 / HZ),
485 calibration_result % (1000000 / HZ));
487 local_apic_timer_verify_ok = 1;
490 * Do a sanity check on the APIC calibration result
492 if (calibration_result < (1000000 / HZ)) {
495 "APIC frequency too slow, disabling apic timer\n");
496 /* No broadcast on UP ! */
497 if (num_possible_cpus() > 1)
502 /* We trust the pm timer based calibration */
503 if (!pm_referenced) {
504 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
507 * Setup the apic timer manually
509 levt->event_handler = lapic_cal_handler;
510 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
511 lapic_cal_loops = -1;
513 /* Let the interrupts run */
516 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
521 /* Stop the lapic timer */
522 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
527 deltaj = lapic_cal_j2 - lapic_cal_j1;
528 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
530 /* Check, if the jiffies result is consistent */
531 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
532 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
534 local_apic_timer_verify_ok = 0;
538 if (!local_apic_timer_verify_ok) {
540 "APIC timer disabled due to verification failure.\n");
541 /* No broadcast on UP ! */
542 if (num_possible_cpus() == 1)
546 * If nmi_watchdog is set to IO_APIC, we need the
547 * PIT/HPET going. Otherwise register lapic as a dummy
550 if (nmi_watchdog != NMI_IO_APIC)
551 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
553 printk(KERN_WARNING "APIC timer registered as dummy,"
554 " due to nmi_watchdog=%d!\n", nmi_watchdog);
557 /* Setup the lapic or request the broadcast */
561 void __devinit setup_secondary_APIC_clock(void)
567 * The guts of the apic timer interrupt
569 static void local_apic_timer_interrupt(void)
571 int cpu = smp_processor_id();
572 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
575 * Normally we should not be here till LAPIC has been initialized but
576 * in some cases like kdump, its possible that there is a pending LAPIC
577 * timer interrupt from previous kernel's context and is delivered in
578 * new kernel the moment interrupts are enabled.
580 * Interrupts are enabled early and LAPIC is setup much later, hence
581 * its possible that when we get here evt->event_handler is NULL.
582 * Check for event_handler being NULL and discard the interrupt as
585 if (!evt->event_handler) {
587 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
589 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
594 * the NMI deadlock-detector uses this.
596 per_cpu(irq_stat, cpu).apic_timer_irqs++;
598 evt->event_handler(evt);
602 * Local APIC timer interrupt. This is the most natural way for doing
603 * local interrupts, but local timer interrupts can be emulated by
604 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
606 * [ if a single-CPU system runs an SMP kernel then we call the local
607 * interrupt as well. Thus we cannot inline the local irq ... ]
609 void smp_apic_timer_interrupt(struct pt_regs *regs)
611 struct pt_regs *old_regs = set_irq_regs(regs);
614 * NOTE! We'd better ACK the irq immediately,
615 * because timer handling can be slow.
619 * update_process_times() expects us to have done irq_enter().
620 * Besides, if we don't timer interrupts ignore the global
621 * interrupt lock, which is the WrongThing (tm) to do.
624 local_apic_timer_interrupt();
627 set_irq_regs(old_regs);
630 int setup_profiling_timer(unsigned int multiplier)
636 * Setup extended LVT, AMD specific (K8, family 10h)
638 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
639 * MCE interrupts are supported. Thus MCE offset must be set to 0.
642 #define APIC_EILVT_LVTOFF_MCE 0
643 #define APIC_EILVT_LVTOFF_IBS 1
645 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
647 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
648 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
652 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
654 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
655 return APIC_EILVT_LVTOFF_MCE;
658 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
660 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
661 return APIC_EILVT_LVTOFF_IBS;
665 * Local APIC start and shutdown
669 * clear_local_APIC - shutdown the local APIC
671 * This is called, when a CPU is disabled and before rebooting, so the state of
672 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
673 * leftovers during boot.
675 void clear_local_APIC(void)
680 /* APIC hasn't been mapped yet */
684 maxlvt = lapic_get_maxlvt();
686 * Masking an LVT entry can trigger a local APIC error
687 * if the vector is zero. Mask LVTERR first to prevent this.
690 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
691 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
694 * Careful: we have to set masks only first to deassert
695 * any level-triggered sources.
697 v = apic_read(APIC_LVTT);
698 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
699 v = apic_read(APIC_LVT0);
700 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
701 v = apic_read(APIC_LVT1);
702 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
704 v = apic_read(APIC_LVTPC);
705 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
708 /* lets not touch this if we didn't frob it */
709 #ifdef CONFIG_X86_MCE_P4THERMAL
711 v = apic_read(APIC_LVTTHMR);
712 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
716 * Clean APIC state for other OSs:
718 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
719 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
720 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
722 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
724 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
726 #ifdef CONFIG_X86_MCE_P4THERMAL
728 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
730 /* Integrated APIC (!82489DX) ? */
731 if (lapic_is_integrated()) {
733 /* Clear ESR due to Pentium errata 3AP and 11AP */
734 apic_write(APIC_ESR, 0);
740 * disable_local_APIC - clear and disable the local APIC
742 void disable_local_APIC(void)
749 * Disable APIC (implies clearing of registers
752 value = apic_read(APIC_SPIV);
753 value &= ~APIC_SPIV_APIC_ENABLED;
754 apic_write_around(APIC_SPIV, value);
757 * When LAPIC was disabled by the BIOS and enabled by the kernel,
758 * restore the disabled state.
760 if (enabled_via_apicbase) {
763 rdmsr(MSR_IA32_APICBASE, l, h);
764 l &= ~MSR_IA32_APICBASE_ENABLE;
765 wrmsr(MSR_IA32_APICBASE, l, h);
770 * If Linux enabled the LAPIC against the BIOS default disable it down before
771 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
772 * not power-off. Additionally clear all LVT entries before disable_local_APIC
773 * for the case where Linux didn't enable the LAPIC.
775 void lapic_shutdown(void)
782 local_irq_save(flags);
785 if (enabled_via_apicbase)
786 disable_local_APIC();
788 local_irq_restore(flags);
792 * This is to verify that we're looking at a real local APIC.
793 * Check these against your board if the CPUs aren't getting
794 * started for no apparent reason.
796 int __init verify_local_APIC(void)
798 unsigned int reg0, reg1;
801 * The version register is read-only in a real APIC.
803 reg0 = apic_read(APIC_LVR);
804 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
805 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
806 reg1 = apic_read(APIC_LVR);
807 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
810 * The two version reads above should print the same
811 * numbers. If the second one is different, then we
812 * poke at a non-APIC.
818 * Check if the version looks reasonably.
820 reg1 = GET_APIC_VERSION(reg0);
821 if (reg1 == 0x00 || reg1 == 0xff)
823 reg1 = lapic_get_maxlvt();
824 if (reg1 < 0x02 || reg1 == 0xff)
828 * The ID register is read/write in a real APIC.
830 reg0 = apic_read(APIC_ID);
831 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
834 * The next two are just to see if we have sane values.
835 * They're only really relevant if we're in Virtual Wire
836 * compatibility mode, but most boxes are anymore.
838 reg0 = apic_read(APIC_LVT0);
839 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
840 reg1 = apic_read(APIC_LVT1);
841 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
847 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
849 void __init sync_Arb_IDs(void)
852 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
855 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
860 apic_wait_icr_idle();
862 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
863 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
868 * An initial setup of the virtual wire mode.
870 void __init init_bsp_APIC(void)
875 * Don't do the setup now if we have a SMP BIOS as the
876 * through-I/O-APIC virtual wire mode might be active.
878 if (smp_found_config || !cpu_has_apic)
882 * Do not trust the local APIC being empty at bootup.
889 value = apic_read(APIC_SPIV);
890 value &= ~APIC_VECTOR_MASK;
891 value |= APIC_SPIV_APIC_ENABLED;
893 /* This bit is reserved on P4/Xeon and should be cleared */
894 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
895 (boot_cpu_data.x86 == 15))
896 value &= ~APIC_SPIV_FOCUS_DISABLED;
898 value |= APIC_SPIV_FOCUS_DISABLED;
899 value |= SPURIOUS_APIC_VECTOR;
900 apic_write_around(APIC_SPIV, value);
903 * Set up the virtual wire mode.
905 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
907 if (!lapic_is_integrated()) /* 82489DX */
908 value |= APIC_LVT_LEVEL_TRIGGER;
909 apic_write_around(APIC_LVT1, value);
912 static void __cpuinit lapic_setup_esr(void)
914 unsigned long oldvalue, value, maxlvt;
915 if (lapic_is_integrated() && !esr_disable) {
917 maxlvt = lapic_get_maxlvt();
918 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
919 apic_write(APIC_ESR, 0);
920 oldvalue = apic_read(APIC_ESR);
922 /* enables sending errors */
923 value = ERROR_APIC_VECTOR;
924 apic_write_around(APIC_LVTERR, value);
926 * spec says clear errors after enabling vector.
929 apic_write(APIC_ESR, 0);
930 value = apic_read(APIC_ESR);
931 if (value != oldvalue)
932 apic_printk(APIC_VERBOSE, "ESR value before enabling "
933 "vector: 0x%08lx after: 0x%08lx\n",
938 * Something untraceable is creating bad interrupts on
939 * secondary quads ... for the moment, just leave the
940 * ESR disabled - we can't do anything useful with the
941 * errors anyway - mbligh
943 printk(KERN_INFO "Leaving ESR disabled.\n");
945 printk(KERN_INFO "No ESR for 82489DX.\n");
951 * setup_local_APIC - setup the local APIC
953 void __cpuinit setup_local_APIC(void)
955 unsigned long value, integrated;
958 /* Pound the ESR really hard over the head with a big hammer - mbligh */
960 apic_write(APIC_ESR, 0);
961 apic_write(APIC_ESR, 0);
962 apic_write(APIC_ESR, 0);
963 apic_write(APIC_ESR, 0);
966 integrated = lapic_is_integrated();
969 * Double-check whether this APIC is really registered.
971 if (!apic_id_registered())
975 * Intel recommends to set DFR, LDR and TPR before enabling
976 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
977 * document number 292116). So here it goes...
982 * Set Task Priority to 'accept all'. We never change this
985 value = apic_read(APIC_TASKPRI);
986 value &= ~APIC_TPRI_MASK;
987 apic_write_around(APIC_TASKPRI, value);
990 * After a crash, we no longer service the interrupts and a pending
991 * interrupt from previous kernel might still have ISR bit set.
993 * Most probably by now CPU has serviced that pending interrupt and
994 * it might not have done the ack_APIC_irq() because it thought,
995 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
996 * does not clear the ISR bit and cpu thinks it has already serivced
997 * the interrupt. Hence a vector might get locked. It was noticed
998 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1000 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1001 value = apic_read(APIC_ISR + i*0x10);
1002 for (j = 31; j >= 0; j--) {
1009 * Now that we are all set up, enable the APIC
1011 value = apic_read(APIC_SPIV);
1012 value &= ~APIC_VECTOR_MASK;
1016 value |= APIC_SPIV_APIC_ENABLED;
1019 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1020 * certain networking cards. If high frequency interrupts are
1021 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1022 * entry is masked/unmasked at a high rate as well then sooner or
1023 * later IOAPIC line gets 'stuck', no more interrupts are received
1024 * from the device. If focus CPU is disabled then the hang goes
1027 * [ This bug can be reproduced easily with a level-triggered
1028 * PCI Ne2000 networking cards and PII/PIII processors, dual
1032 * Actually disabling the focus CPU check just makes the hang less
1033 * frequent as it makes the interrupt distributon model be more
1034 * like LRU than MRU (the short-term load is more even across CPUs).
1035 * See also the comment in end_level_ioapic_irq(). --macro
1038 /* Enable focus processor (bit==0) */
1039 value &= ~APIC_SPIV_FOCUS_DISABLED;
1042 * Set spurious IRQ vector
1044 value |= SPURIOUS_APIC_VECTOR;
1045 apic_write_around(APIC_SPIV, value);
1048 * Set up LVT0, LVT1:
1050 * set up through-local-APIC on the BP's LINT0. This is not
1051 * strictly necessary in pure symmetric-IO mode, but sometimes
1052 * we delegate interrupts to the 8259A.
1055 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1057 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1058 if (!smp_processor_id() && (pic_mode || !value)) {
1059 value = APIC_DM_EXTINT;
1060 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1061 smp_processor_id());
1063 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1064 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1065 smp_processor_id());
1067 apic_write_around(APIC_LVT0, value);
1070 * only the BP should see the LINT1 NMI signal, obviously.
1072 if (!smp_processor_id())
1073 value = APIC_DM_NMI;
1075 value = APIC_DM_NMI | APIC_LVT_MASKED;
1076 if (!integrated) /* 82489DX */
1077 value |= APIC_LVT_LEVEL_TRIGGER;
1078 apic_write_around(APIC_LVT1, value);
1081 void __cpuinit end_local_APIC_setup(void)
1083 unsigned long value;
1086 /* Disable the local apic timer */
1087 value = apic_read(APIC_LVTT);
1088 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1089 apic_write_around(APIC_LVTT, value);
1091 setup_apic_nmi_watchdog(NULL);
1096 * Detect and initialize APIC
1098 static int __init detect_init_APIC(void)
1102 /* Disabled by kernel option? */
1106 switch (boot_cpu_data.x86_vendor) {
1107 case X86_VENDOR_AMD:
1108 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1109 (boot_cpu_data.x86 == 15))
1112 case X86_VENDOR_INTEL:
1113 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1114 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1121 if (!cpu_has_apic) {
1123 * Over-ride BIOS and try to enable the local APIC only if
1124 * "lapic" specified.
1126 if (!force_enable_local_apic) {
1127 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1128 "you can enable it with \"lapic\"\n");
1132 * Some BIOSes disable the local APIC in the APIC_BASE
1133 * MSR. This can only be done in software for Intel P6 or later
1134 * and AMD K7 (Model > 1) or later.
1136 rdmsr(MSR_IA32_APICBASE, l, h);
1137 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1139 "Local APIC disabled by BIOS -- reenabling.\n");
1140 l &= ~MSR_IA32_APICBASE_BASE;
1141 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1142 wrmsr(MSR_IA32_APICBASE, l, h);
1143 enabled_via_apicbase = 1;
1147 * The APIC feature bit should now be enabled
1150 features = cpuid_edx(1);
1151 if (!(features & (1 << X86_FEATURE_APIC))) {
1152 printk(KERN_WARNING "Could not enable APIC!\n");
1155 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1156 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1158 /* The BIOS may have set up the APIC at some other address */
1159 rdmsr(MSR_IA32_APICBASE, l, h);
1160 if (l & MSR_IA32_APICBASE_ENABLE)
1161 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1163 printk(KERN_INFO "Found and enabled local APIC!\n");
1170 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1175 * init_apic_mappings - initialize APIC mappings
1177 void __init init_apic_mappings(void)
1180 * If no local APIC can be found then set up a fake all
1181 * zeroes page to simulate the local APIC and another
1182 * one for the IO-APIC.
1184 if (!smp_found_config && detect_init_APIC()) {
1185 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1186 apic_phys = __pa(apic_phys);
1188 apic_phys = mp_lapic_addr;
1190 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1191 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1195 * Fetch the APIC ID of the BSP in case we have a
1196 * default configuration (or the MP table is broken).
1198 if (boot_cpu_physical_apicid == -1U)
1199 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1204 * This initializes the IO-APIC and APIC hardware if this is
1208 int apic_version[MAX_APICS];
1210 int __init APIC_init_uniprocessor(void)
1213 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1215 if (!smp_found_config && !cpu_has_apic)
1219 * Complain if the BIOS pretends there is one.
1221 if (!cpu_has_apic &&
1222 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1223 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1224 boot_cpu_physical_apicid);
1225 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1229 verify_local_APIC();
1234 * Hack: In case of kdump, after a crash, kernel might be booting
1235 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1236 * might be zero if read from MP tables. Get it from LAPIC.
1238 #ifdef CONFIG_CRASH_DUMP
1239 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
1241 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1245 #ifdef CONFIG_X86_IO_APIC
1246 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1248 localise_nmi_watchdog();
1249 end_local_APIC_setup();
1250 #ifdef CONFIG_X86_IO_APIC
1251 if (smp_found_config)
1252 if (!skip_ioapic_setup && nr_ioapics)
1261 * Local APIC interrupts
1265 * This interrupt should _never_ happen with our APIC/SMP architecture
1267 void smp_spurious_interrupt(struct pt_regs *regs)
1273 * Check if this really is a spurious interrupt and ACK it
1274 * if it is a vectored one. Just in case...
1275 * Spurious interrupts should not be ACKed.
1277 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1278 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1281 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1282 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1283 "should never happen.\n", smp_processor_id());
1284 __get_cpu_var(irq_stat).irq_spurious_count++;
1289 * This interrupt should never happen with our APIC/SMP architecture
1291 void smp_error_interrupt(struct pt_regs *regs)
1293 unsigned long v, v1;
1296 /* First tickle the hardware, only then report what went on. -- REW */
1297 v = apic_read(APIC_ESR);
1298 apic_write(APIC_ESR, 0);
1299 v1 = apic_read(APIC_ESR);
1301 atomic_inc(&irq_err_count);
1303 /* Here is what the APIC error bits mean:
1306 2: Send accept error
1307 3: Receive accept error
1309 5: Send illegal vector
1310 6: Received illegal vector
1311 7: Illegal register address
1313 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1314 smp_processor_id(), v , v1);
1319 void __init smp_intr_init(void)
1322 * IRQ0 must be given a fixed assignment and initialized,
1323 * because it's used before the IO-APIC is set up.
1325 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1328 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1329 * IPI, driven by wakeup.
1331 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1333 /* IPI for invalidation */
1334 alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1336 /* IPI for generic function call */
1337 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1342 * Initialize APIC interrupts
1344 void __init apic_intr_init(void)
1349 /* self generated IPI for local APIC timer */
1350 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1352 /* IPI vectors for APIC spurious and error interrupts */
1353 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1354 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1356 /* thermal monitor LVT interrupt */
1357 #ifdef CONFIG_X86_MCE_P4THERMAL
1358 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1363 * connect_bsp_APIC - attach the APIC to the interrupt system
1365 void __init connect_bsp_APIC(void)
1369 * Do not trust the local APIC being empty at bootup.
1373 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1374 * local APIC to INT and NMI lines.
1376 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1377 "enabling APIC mode.\n");
1385 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1386 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1388 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1391 void disconnect_bsp_APIC(int virt_wire_setup)
1395 * Put the board back into PIC mode (has an effect only on
1396 * certain older boards). Note that APIC interrupts, including
1397 * IPIs, won't work beyond this point! The only exception are
1400 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1401 "entering PIC mode.\n");
1405 /* Go back to Virtual Wire compatibility mode */
1406 unsigned long value;
1408 /* For the spurious interrupt use vector F, and enable it */
1409 value = apic_read(APIC_SPIV);
1410 value &= ~APIC_VECTOR_MASK;
1411 value |= APIC_SPIV_APIC_ENABLED;
1413 apic_write_around(APIC_SPIV, value);
1415 if (!virt_wire_setup) {
1417 * For LVT0 make it edge triggered, active high,
1418 * external and enabled
1420 value = apic_read(APIC_LVT0);
1421 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1422 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1423 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1424 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1425 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1426 apic_write_around(APIC_LVT0, value);
1429 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
1433 * For LVT1 make it edge triggered, active high, nmi and
1436 value = apic_read(APIC_LVT1);
1438 APIC_MODE_MASK | APIC_SEND_PENDING |
1439 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1440 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1441 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1442 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1443 apic_write_around(APIC_LVT1, value);
1447 unsigned int __cpuinitdata maxcpus = NR_CPUS;
1449 void __cpuinit generic_processor_info(int apicid, int version)
1453 physid_mask_t phys_cpu;
1458 if (version == 0x0) {
1459 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1460 "fixing up to 0x10. (tell your hw vendor)\n",
1464 apic_version[apicid] = version;
1466 phys_cpu = apicid_to_cpu_present(apicid);
1467 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1469 if (num_processors >= NR_CPUS) {
1470 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1471 " Processor ignored.\n", NR_CPUS);
1475 if (num_processors >= maxcpus) {
1476 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1477 " Processor ignored.\n", maxcpus);
1482 cpus_complement(tmp_map, cpu_present_map);
1483 cpu = first_cpu(tmp_map);
1485 if (apicid == boot_cpu_physical_apicid)
1487 * x86_bios_cpu_apicid is required to have processors listed
1488 * in same order as logical cpu numbers. Hence the first
1489 * entry is BSP, and so on.
1493 if (apicid > max_physical_apicid)
1494 max_physical_apicid = apicid;
1497 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1498 * but we need to work other dependencies like SMP_SUSPEND etc
1499 * before this can be done without some confusion.
1500 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1501 * - Ashok Raj <ashok.raj@intel.com>
1503 if (max_physical_apicid >= 8) {
1504 switch (boot_cpu_data.x86_vendor) {
1505 case X86_VENDOR_INTEL:
1506 if (!APIC_XAPIC(version)) {
1510 /* If P4 and above fall through */
1511 case X86_VENDOR_AMD:
1516 /* are we being called early in kernel startup? */
1517 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1518 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1519 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1521 cpu_to_apicid[cpu] = apicid;
1522 bios_cpu_apicid[cpu] = apicid;
1524 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1525 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1528 cpu_set(cpu, cpu_possible_map);
1529 cpu_set(cpu, cpu_present_map);
1539 /* r/w apic fields */
1540 unsigned int apic_id;
1541 unsigned int apic_taskpri;
1542 unsigned int apic_ldr;
1543 unsigned int apic_dfr;
1544 unsigned int apic_spiv;
1545 unsigned int apic_lvtt;
1546 unsigned int apic_lvtpc;
1547 unsigned int apic_lvt0;
1548 unsigned int apic_lvt1;
1549 unsigned int apic_lvterr;
1550 unsigned int apic_tmict;
1551 unsigned int apic_tdcr;
1552 unsigned int apic_thmr;
1555 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1557 unsigned long flags;
1560 if (!apic_pm_state.active)
1563 maxlvt = lapic_get_maxlvt();
1565 apic_pm_state.apic_id = apic_read(APIC_ID);
1566 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1567 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1568 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1569 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1570 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1572 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1573 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1574 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1575 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1576 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1577 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1578 #ifdef CONFIG_X86_MCE_P4THERMAL
1580 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1583 local_irq_save(flags);
1584 disable_local_APIC();
1585 local_irq_restore(flags);
1589 static int lapic_resume(struct sys_device *dev)
1592 unsigned long flags;
1595 if (!apic_pm_state.active)
1598 maxlvt = lapic_get_maxlvt();
1600 local_irq_save(flags);
1603 * Make sure the APICBASE points to the right address
1605 * FIXME! This will be wrong if we ever support suspend on
1606 * SMP! We'll need to do this as part of the CPU restore!
1608 rdmsr(MSR_IA32_APICBASE, l, h);
1609 l &= ~MSR_IA32_APICBASE_BASE;
1610 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1611 wrmsr(MSR_IA32_APICBASE, l, h);
1613 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1614 apic_write(APIC_ID, apic_pm_state.apic_id);
1615 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1616 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1617 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1618 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1619 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1620 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1621 #ifdef CONFIG_X86_MCE_P4THERMAL
1623 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1626 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1627 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1628 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1629 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1630 apic_write(APIC_ESR, 0);
1631 apic_read(APIC_ESR);
1632 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1633 apic_write(APIC_ESR, 0);
1634 apic_read(APIC_ESR);
1635 local_irq_restore(flags);
1640 * This device has no shutdown method - fully functioning local APICs
1641 * are needed on every CPU up until machine_halt/restart/poweroff.
1644 static struct sysdev_class lapic_sysclass = {
1646 .resume = lapic_resume,
1647 .suspend = lapic_suspend,
1650 static struct sys_device device_lapic = {
1652 .cls = &lapic_sysclass,
1655 static void __devinit apic_pm_activate(void)
1657 apic_pm_state.active = 1;
1660 static int __init init_lapic_sysfs(void)
1666 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1668 error = sysdev_class_register(&lapic_sysclass);
1670 error = sysdev_register(&device_lapic);
1673 device_initcall(init_lapic_sysfs);
1675 #else /* CONFIG_PM */
1677 static void apic_pm_activate(void) { }
1679 #endif /* CONFIG_PM */
1682 * APIC command line parameters
1684 static int __init parse_lapic(char *arg)
1686 force_enable_local_apic = 1;
1689 early_param("lapic", parse_lapic);
1691 static int __init parse_nolapic(char *arg)
1694 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1697 early_param("nolapic", parse_nolapic);
1699 static int __init parse_disable_lapic_timer(char *arg)
1701 local_apic_timer_disabled = 1;
1704 early_param("nolapic_timer", parse_disable_lapic_timer);
1706 static int __init parse_lapic_timer_c2_ok(char *arg)
1708 local_apic_timer_c2_ok = 1;
1711 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1713 static int __init apic_set_verbosity(char *str)
1715 if (strcmp("debug", str) == 0)
1716 apic_verbosity = APIC_DEBUG;
1717 else if (strcmp("verbose", str) == 0)
1718 apic_verbosity = APIC_VERBOSE;
1721 __setup("apic=", apic_set_verbosity);