2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
35 #include <asm/atomic.h>
38 #include <asm/mpspec.h>
40 #include <asm/arch_hooks.h>
42 #include <asm/pgalloc.h>
43 #include <asm/i8253.h>
46 #include <asm/proto.h>
47 #include <asm/timex.h>
49 #include <asm/i8259.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
58 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
59 # error SPURIOUS_APIC_VECTOR definition error
64 * Knob to control our willingness to enable the local APIC.
68 static int force_enable_local_apic;
70 * APIC command line parameters
72 static int __init parse_lapic(char *arg)
74 force_enable_local_apic = 1;
77 early_param("lapic", parse_lapic);
78 /* Local APIC was disabled by the BIOS and enabled by the kernel */
79 static int enabled_via_apicbase;
84 static int apic_calibrate_pmtmr __initdata;
85 static __init int setup_apicpmtimer(char *s)
87 apic_calibrate_pmtmr = 1;
91 __setup("apicpmtimer", setup_apicpmtimer);
100 /* x2apic enabled before OS handover */
101 int x2apic_preenabled;
103 static __init int setup_nox2apic(char *str)
106 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
109 early_param("nox2apic", setup_nox2apic);
112 unsigned long mp_lapic_addr;
114 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
115 static int disable_apic_timer __cpuinitdata;
116 /* Local APIC timer works in C2 */
117 int local_apic_timer_c2_ok;
118 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
120 int first_system_vector = 0xfe;
122 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
125 * Debug level, exported for io_apic.c
127 unsigned int apic_verbosity;
131 /* Have we found an MP table */
132 int smp_found_config;
134 static struct resource lapic_resource = {
135 .name = "Local APIC",
136 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
139 static unsigned int calibration_result;
141 static int lapic_next_event(unsigned long delta,
142 struct clock_event_device *evt);
143 static void lapic_timer_setup(enum clock_event_mode mode,
144 struct clock_event_device *evt);
145 static void lapic_timer_broadcast(cpumask_t mask);
146 static void apic_pm_activate(void);
149 * The local apic timer can be used for any function which is CPU local.
151 static struct clock_event_device lapic_clockevent = {
153 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
154 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
156 .set_mode = lapic_timer_setup,
157 .set_next_event = lapic_next_event,
158 .broadcast = lapic_timer_broadcast,
162 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
164 static unsigned long apic_phys;
167 * Get the LAPIC version
169 static inline int lapic_get_version(void)
171 return GET_APIC_VERSION(apic_read(APIC_LVR));
175 * Check, if the APIC is integrated or a separate chip
177 static inline int lapic_is_integrated(void)
182 return APIC_INTEGRATED(lapic_get_version());
187 * Check, whether this is a modern or a first generation APIC
189 static int modern_apic(void)
191 /* AMD systems use old APIC versions, so check the CPU */
192 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
193 boot_cpu_data.x86 >= 0xf)
195 return lapic_get_version() >= 0x14;
199 * Paravirt kernels also might be using these below ops. So we still
200 * use generic apic_read()/apic_write(), which might be pointing to different
201 * ops in PARAVIRT case.
203 void xapic_wait_icr_idle(void)
205 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
209 u32 safe_xapic_wait_icr_idle(void)
216 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
220 } while (timeout++ < 1000);
225 void xapic_icr_write(u32 low, u32 id)
227 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
228 apic_write(APIC_ICR, low);
231 u64 xapic_icr_read(void)
235 icr2 = apic_read(APIC_ICR2);
236 icr1 = apic_read(APIC_ICR);
238 return icr1 | ((u64)icr2 << 32);
241 static struct apic_ops xapic_ops = {
242 .read = native_apic_mem_read,
243 .write = native_apic_mem_write,
244 .icr_read = xapic_icr_read,
245 .icr_write = xapic_icr_write,
246 .wait_icr_idle = xapic_wait_icr_idle,
247 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
250 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
251 EXPORT_SYMBOL_GPL(apic_ops);
254 static void x2apic_wait_icr_idle(void)
256 /* no need to wait for icr idle in x2apic */
260 static u32 safe_x2apic_wait_icr_idle(void)
262 /* no need to wait for icr idle in x2apic */
266 void x2apic_icr_write(u32 low, u32 id)
268 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
271 u64 x2apic_icr_read(void)
275 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
279 static struct apic_ops x2apic_ops = {
280 .read = native_apic_msr_read,
281 .write = native_apic_msr_write,
282 .icr_read = x2apic_icr_read,
283 .icr_write = x2apic_icr_write,
284 .wait_icr_idle = x2apic_wait_icr_idle,
285 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
290 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
292 void __cpuinit enable_NMI_through_LVT0(void)
296 /* unmask and set to NMI */
299 /* Level triggered for 82489DX (32bit mode) */
300 if (!lapic_is_integrated())
301 v |= APIC_LVT_LEVEL_TRIGGER;
303 apic_write(APIC_LVT0, v);
308 * get_physical_broadcast - Get number of physical broadcast IDs
310 int get_physical_broadcast(void)
312 return modern_apic() ? 0xff : 0xf;
317 * lapic_get_maxlvt - get the maximum number of local vector table entries
319 int lapic_get_maxlvt(void)
323 v = apic_read(APIC_LVR);
325 * - we always have APIC integrated on 64bit mode
326 * - 82489DXs do not report # of LVT entries
328 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
336 #define APIC_DIVISOR 16
339 * This function sets up the local APIC timer, with a timeout of
340 * 'clocks' APIC bus clock. During calibration we actually call
341 * this function twice on the boot CPU, once with a bogus timeout
342 * value, second time for real. The other (noncalibrating) CPUs
343 * call this function only once, with the real, calibrated value.
345 * We do reads before writes even if unnecessary, to get around the
346 * P5 APIC double write bug.
348 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
350 unsigned int lvtt_value, tmp_value;
352 lvtt_value = LOCAL_TIMER_VECTOR;
354 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
355 if (!lapic_is_integrated())
356 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
359 lvtt_value |= APIC_LVT_MASKED;
361 apic_write(APIC_LVTT, lvtt_value);
366 tmp_value = apic_read(APIC_TDCR);
367 apic_write(APIC_TDCR,
368 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
372 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
376 * Setup extended LVT, AMD specific (K8, family 10h)
378 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
379 * MCE interrupts are supported. Thus MCE offset must be set to 0.
381 * If mask=1, the LVT entry does not generate interrupts while mask=0
382 * enables the vector. See also the BKDGs.
385 #define APIC_EILVT_LVTOFF_MCE 0
386 #define APIC_EILVT_LVTOFF_IBS 1
388 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
390 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
391 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
396 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
398 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
399 return APIC_EILVT_LVTOFF_MCE;
402 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
404 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
405 return APIC_EILVT_LVTOFF_IBS;
407 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
410 * Program the next event, relative to now
412 static int lapic_next_event(unsigned long delta,
413 struct clock_event_device *evt)
415 apic_write(APIC_TMICT, delta);
420 * Setup the lapic timer in periodic or oneshot mode
422 static void lapic_timer_setup(enum clock_event_mode mode,
423 struct clock_event_device *evt)
428 /* Lapic used as dummy for broadcast ? */
429 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
432 local_irq_save(flags);
435 case CLOCK_EVT_MODE_PERIODIC:
436 case CLOCK_EVT_MODE_ONESHOT:
437 __setup_APIC_LVTT(calibration_result,
438 mode != CLOCK_EVT_MODE_PERIODIC, 1);
440 case CLOCK_EVT_MODE_UNUSED:
441 case CLOCK_EVT_MODE_SHUTDOWN:
442 v = apic_read(APIC_LVTT);
443 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
444 apic_write(APIC_LVTT, v);
446 case CLOCK_EVT_MODE_RESUME:
447 /* Nothing to do here */
451 local_irq_restore(flags);
455 * Local APIC timer broadcast function
457 static void lapic_timer_broadcast(cpumask_t mask)
460 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
465 * Setup the local APIC timer for this CPU. Copy the initilized values
466 * of the boot CPU and register the clock event in the framework.
468 static void __cpuinit setup_APIC_timer(void)
470 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
472 memcpy(levt, &lapic_clockevent, sizeof(*levt));
473 levt->cpumask = cpumask_of_cpu(smp_processor_id());
475 clockevents_register_device(levt);
479 * In this functions we calibrate APIC bus clocks to the external timer.
481 * We want to do the calibration only once since we want to have local timer
482 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
485 * This was previously done by reading the PIT/HPET and waiting for a wrap
486 * around to find out, that a tick has elapsed. I have a box, where the PIT
487 * readout is broken, so it never gets out of the wait loop again. This was
488 * also reported by others.
490 * Monitoring the jiffies value is inaccurate and the clockevents
491 * infrastructure allows us to do a simple substitution of the interrupt
494 * The calibration routine also uses the pm_timer when possible, as the PIT
495 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
496 * back to normal later in the boot process).
499 #define LAPIC_CAL_LOOPS (HZ/10)
501 static __initdata int lapic_cal_loops = -1;
502 static __initdata long lapic_cal_t1, lapic_cal_t2;
503 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
504 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
505 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
508 * Temporary interrupt handler.
510 static void __init lapic_cal_handler(struct clock_event_device *dev)
512 unsigned long long tsc = 0;
513 long tapic = apic_read(APIC_TMCCT);
514 unsigned long pm = acpi_pm_read_early();
519 switch (lapic_cal_loops++) {
521 lapic_cal_t1 = tapic;
522 lapic_cal_tsc1 = tsc;
524 lapic_cal_j1 = jiffies;
527 case LAPIC_CAL_LOOPS:
528 lapic_cal_t2 = tapic;
529 lapic_cal_tsc2 = tsc;
530 if (pm < lapic_cal_pm1)
531 pm += ACPI_PM_OVRRUN;
533 lapic_cal_j2 = jiffies;
538 static int __init calibrate_by_pmtimer(long deltapm, long *delta)
540 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
541 const long pm_thresh = pm_100ms / 100;
545 #ifndef CONFIG_X86_PM_TIMER
549 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
551 /* Check, if the PM timer is available */
555 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
557 if (deltapm > (pm_100ms - pm_thresh) &&
558 deltapm < (pm_100ms + pm_thresh)) {
559 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
561 res = (((u64)deltapm) * mult) >> 22;
562 do_div(res, 1000000);
563 printk(KERN_WARNING "APIC calibration not consistent "
564 "with PM Timer: %ldms instead of 100ms\n",
566 /* Correct the lapic counter value */
567 res = (((u64)(*delta)) * pm_100ms);
568 do_div(res, deltapm);
569 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
570 "%lu (%ld)\n", (unsigned long)res, *delta);
577 static int __init calibrate_APIC_clock(void)
579 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
580 void (*real_handler)(struct clock_event_device *dev);
581 unsigned long deltaj;
583 int pm_referenced = 0;
587 /* Replace the global interrupt handler */
588 real_handler = global_clock_event->event_handler;
589 global_clock_event->event_handler = lapic_cal_handler;
592 * Setup the APIC counter to maximum. There is no way the lapic
593 * can underflow in the 100ms detection time frame
595 __setup_APIC_LVTT(0xffffffff, 0, 0);
597 /* Let the interrupts run */
600 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
605 /* Restore the real event handler */
606 global_clock_event->event_handler = real_handler;
608 /* Build delta t1-t2 as apic timer counts down */
609 delta = lapic_cal_t1 - lapic_cal_t2;
610 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
612 /* we trust the PM based calibration if possible */
613 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
616 /* Calculate the scaled math multiplication factor */
617 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
618 lapic_clockevent.shift);
619 lapic_clockevent.max_delta_ns =
620 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
621 lapic_clockevent.min_delta_ns =
622 clockevent_delta2ns(0xF, &lapic_clockevent);
624 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
626 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
627 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
628 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
632 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
633 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
635 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
636 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
639 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
641 calibration_result / (1000000 / HZ),
642 calibration_result % (1000000 / HZ));
645 * Do a sanity check on the APIC calibration result
647 if (calibration_result < (1000000 / HZ)) {
650 "APIC frequency too slow, disabling apic timer\n");
654 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
657 * PM timer calibration failed or not turned on
658 * so lets try APIC timer based calibration
660 if (!pm_referenced) {
661 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
664 * Setup the apic timer manually
666 levt->event_handler = lapic_cal_handler;
667 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
668 lapic_cal_loops = -1;
670 /* Let the interrupts run */
673 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
678 /* Stop the lapic timer */
679 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
684 deltaj = lapic_cal_j2 - lapic_cal_j1;
685 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
687 /* Check, if the jiffies result is consistent */
688 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
689 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
691 levt->features |= CLOCK_EVT_FEAT_DUMMY;
695 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
697 "APIC timer disabled due to verification failure.\n");
705 * Setup the boot APIC
707 * Calibrate and verify the result.
709 void __init setup_boot_APIC_clock(void)
712 * The local apic timer can be disabled via the kernel
713 * commandline or from the CPU detection code. Register the lapic
714 * timer as a dummy clock event source on SMP systems, so the
715 * broadcast mechanism is used. On UP systems simply ignore it.
717 if (disable_apic_timer) {
718 printk(KERN_INFO "Disabling APIC timer\n");
719 /* No broadcast on UP ! */
720 if (num_possible_cpus() > 1) {
721 lapic_clockevent.mult = 1;
727 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
728 "calibrating APIC timer ...\n");
730 if (calibrate_APIC_clock()) {
731 /* No broadcast on UP ! */
732 if (num_possible_cpus() > 1)
738 * If nmi_watchdog is set to IO_APIC, we need the
739 * PIT/HPET going. Otherwise register lapic as a dummy
742 if (nmi_watchdog != NMI_IO_APIC)
743 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
745 printk(KERN_WARNING "APIC timer registered as dummy,"
746 " due to nmi_watchdog=%d!\n", nmi_watchdog);
748 /* Setup the lapic or request the broadcast */
752 void __cpuinit setup_secondary_APIC_clock(void)
758 * The guts of the apic timer interrupt
760 static void local_apic_timer_interrupt(void)
762 int cpu = smp_processor_id();
763 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
766 * Normally we should not be here till LAPIC has been initialized but
767 * in some cases like kdump, its possible that there is a pending LAPIC
768 * timer interrupt from previous kernel's context and is delivered in
769 * new kernel the moment interrupts are enabled.
771 * Interrupts are enabled early and LAPIC is setup much later, hence
772 * its possible that when we get here evt->event_handler is NULL.
773 * Check for event_handler being NULL and discard the interrupt as
776 if (!evt->event_handler) {
778 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
780 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
785 * the NMI deadlock-detector uses this.
788 add_pda(apic_timer_irqs, 1);
790 per_cpu(irq_stat, cpu).apic_timer_irqs++;
793 evt->event_handler(evt);
797 * Local APIC timer interrupt. This is the most natural way for doing
798 * local interrupts, but local timer interrupts can be emulated by
799 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
801 * [ if a single-CPU system runs an SMP kernel then we call the local
802 * interrupt as well. Thus we cannot inline the local irq ... ]
804 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
806 struct pt_regs *old_regs = set_irq_regs(regs);
809 * NOTE! We'd better ACK the irq immediately,
810 * because timer handling can be slow.
814 * update_process_times() expects us to have done irq_enter().
815 * Besides, if we don't timer interrupts ignore the global
816 * interrupt lock, which is the WrongThing (tm) to do.
822 local_apic_timer_interrupt();
825 set_irq_regs(old_regs);
828 int setup_profiling_timer(unsigned int multiplier)
834 * Local APIC start and shutdown
838 * clear_local_APIC - shutdown the local APIC
840 * This is called, when a CPU is disabled and before rebooting, so the state of
841 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
842 * leftovers during boot.
844 void clear_local_APIC(void)
849 /* APIC hasn't been mapped yet */
853 maxlvt = lapic_get_maxlvt();
855 * Masking an LVT entry can trigger a local APIC error
856 * if the vector is zero. Mask LVTERR first to prevent this.
859 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
860 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
863 * Careful: we have to set masks only first to deassert
864 * any level-triggered sources.
866 v = apic_read(APIC_LVTT);
867 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
868 v = apic_read(APIC_LVT0);
869 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
870 v = apic_read(APIC_LVT1);
871 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
873 v = apic_read(APIC_LVTPC);
874 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
877 /* lets not touch this if we didn't frob it */
878 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
880 v = apic_read(APIC_LVTTHMR);
881 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
885 * Clean APIC state for other OSs:
887 apic_write(APIC_LVTT, APIC_LVT_MASKED);
888 apic_write(APIC_LVT0, APIC_LVT_MASKED);
889 apic_write(APIC_LVT1, APIC_LVT_MASKED);
891 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
893 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
895 /* Integrated APIC (!82489DX) ? */
896 if (lapic_is_integrated()) {
898 /* Clear ESR due to Pentium errata 3AP and 11AP */
899 apic_write(APIC_ESR, 0);
905 * disable_local_APIC - clear and disable the local APIC
907 void disable_local_APIC(void)
914 * Disable APIC (implies clearing of registers
917 value = apic_read(APIC_SPIV);
918 value &= ~APIC_SPIV_APIC_ENABLED;
919 apic_write(APIC_SPIV, value);
923 * When LAPIC was disabled by the BIOS and enabled by the kernel,
924 * restore the disabled state.
926 if (enabled_via_apicbase) {
929 rdmsr(MSR_IA32_APICBASE, l, h);
930 l &= ~MSR_IA32_APICBASE_ENABLE;
931 wrmsr(MSR_IA32_APICBASE, l, h);
937 * If Linux enabled the LAPIC against the BIOS default disable it down before
938 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
939 * not power-off. Additionally clear all LVT entries before disable_local_APIC
940 * for the case where Linux didn't enable the LAPIC.
942 void lapic_shutdown(void)
949 local_irq_save(flags);
952 if (!enabled_via_apicbase)
956 disable_local_APIC();
959 local_irq_restore(flags);
963 * This is to verify that we're looking at a real local APIC.
964 * Check these against your board if the CPUs aren't getting
965 * started for no apparent reason.
967 int __init verify_local_APIC(void)
969 unsigned int reg0, reg1;
972 * The version register is read-only in a real APIC.
974 reg0 = apic_read(APIC_LVR);
975 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
976 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
977 reg1 = apic_read(APIC_LVR);
978 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
981 * The two version reads above should print the same
982 * numbers. If the second one is different, then we
983 * poke at a non-APIC.
989 * Check if the version looks reasonably.
991 reg1 = GET_APIC_VERSION(reg0);
992 if (reg1 == 0x00 || reg1 == 0xff)
994 reg1 = lapic_get_maxlvt();
995 if (reg1 < 0x02 || reg1 == 0xff)
999 * The ID register is read/write in a real APIC.
1001 reg0 = apic_read(APIC_ID);
1002 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1003 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
1004 reg1 = apic_read(APIC_ID);
1005 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1006 apic_write(APIC_ID, reg0);
1007 if (reg1 != (reg0 ^ APIC_ID_MASK))
1011 * The next two are just to see if we have sane values.
1012 * They're only really relevant if we're in Virtual Wire
1013 * compatibility mode, but most boxes are anymore.
1015 reg0 = apic_read(APIC_LVT0);
1016 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1017 reg1 = apic_read(APIC_LVT1);
1018 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1024 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1026 void __init sync_Arb_IDs(void)
1029 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1032 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1038 apic_wait_icr_idle();
1040 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1041 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1042 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1046 * An initial setup of the virtual wire mode.
1048 void __init init_bsp_APIC(void)
1053 * Don't do the setup now if we have a SMP BIOS as the
1054 * through-I/O-APIC virtual wire mode might be active.
1056 if (smp_found_config || !cpu_has_apic)
1060 * Do not trust the local APIC being empty at bootup.
1067 value = apic_read(APIC_SPIV);
1068 value &= ~APIC_VECTOR_MASK;
1069 value |= APIC_SPIV_APIC_ENABLED;
1071 #ifdef CONFIG_X86_32
1072 /* This bit is reserved on P4/Xeon and should be cleared */
1073 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1074 (boot_cpu_data.x86 == 15))
1075 value &= ~APIC_SPIV_FOCUS_DISABLED;
1078 value |= APIC_SPIV_FOCUS_DISABLED;
1079 value |= SPURIOUS_APIC_VECTOR;
1080 apic_write(APIC_SPIV, value);
1083 * Set up the virtual wire mode.
1085 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1086 value = APIC_DM_NMI;
1087 if (!lapic_is_integrated()) /* 82489DX */
1088 value |= APIC_LVT_LEVEL_TRIGGER;
1089 apic_write(APIC_LVT1, value);
1092 static void __cpuinit lapic_setup_esr(void)
1094 unsigned int oldvalue, value, maxlvt;
1096 if (!lapic_is_integrated()) {
1097 printk(KERN_INFO "No ESR for 82489DX.\n");
1103 * Something untraceable is creating bad interrupts on
1104 * secondary quads ... for the moment, just leave the
1105 * ESR disabled - we can't do anything useful with the
1106 * errors anyway - mbligh
1108 printk(KERN_INFO "Leaving ESR disabled.\n");
1112 maxlvt = lapic_get_maxlvt();
1113 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1114 apic_write(APIC_ESR, 0);
1115 oldvalue = apic_read(APIC_ESR);
1117 /* enables sending errors */
1118 value = ERROR_APIC_VECTOR;
1119 apic_write(APIC_LVTERR, value);
1122 * spec says clear errors after enabling vector.
1125 apic_write(APIC_ESR, 0);
1126 value = apic_read(APIC_ESR);
1127 if (value != oldvalue)
1128 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1129 "vector: 0x%08x after: 0x%08x\n",
1135 * setup_local_APIC - setup the local APIC
1137 void __cpuinit setup_local_APIC(void)
1142 #ifdef CONFIG_X86_32
1143 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1144 if (lapic_is_integrated() && esr_disable) {
1145 apic_write(APIC_ESR, 0);
1146 apic_write(APIC_ESR, 0);
1147 apic_write(APIC_ESR, 0);
1148 apic_write(APIC_ESR, 0);
1155 * Double-check whether this APIC is really registered.
1156 * This is meaningless in clustered apic mode, so we skip it.
1158 if (!apic_id_registered())
1162 * Intel recommends to set DFR, LDR and TPR before enabling
1163 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1164 * document number 292116). So here it goes...
1169 * Set Task Priority to 'accept all'. We never change this
1172 value = apic_read(APIC_TASKPRI);
1173 value &= ~APIC_TPRI_MASK;
1174 apic_write(APIC_TASKPRI, value);
1177 * After a crash, we no longer service the interrupts and a pending
1178 * interrupt from previous kernel might still have ISR bit set.
1180 * Most probably by now CPU has serviced that pending interrupt and
1181 * it might not have done the ack_APIC_irq() because it thought,
1182 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1183 * does not clear the ISR bit and cpu thinks it has already serivced
1184 * the interrupt. Hence a vector might get locked. It was noticed
1185 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1187 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1188 value = apic_read(APIC_ISR + i*0x10);
1189 for (j = 31; j >= 0; j--) {
1196 * Now that we are all set up, enable the APIC
1198 value = apic_read(APIC_SPIV);
1199 value &= ~APIC_VECTOR_MASK;
1203 value |= APIC_SPIV_APIC_ENABLED;
1205 #ifdef CONFIG_X86_32
1207 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1208 * certain networking cards. If high frequency interrupts are
1209 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1210 * entry is masked/unmasked at a high rate as well then sooner or
1211 * later IOAPIC line gets 'stuck', no more interrupts are received
1212 * from the device. If focus CPU is disabled then the hang goes
1215 * [ This bug can be reproduced easily with a level-triggered
1216 * PCI Ne2000 networking cards and PII/PIII processors, dual
1220 * Actually disabling the focus CPU check just makes the hang less
1221 * frequent as it makes the interrupt distributon model be more
1222 * like LRU than MRU (the short-term load is more even across CPUs).
1223 * See also the comment in end_level_ioapic_irq(). --macro
1227 * - enable focus processor (bit==0)
1228 * - 64bit mode always use processor focus
1229 * so no need to set it
1231 value &= ~APIC_SPIV_FOCUS_DISABLED;
1235 * Set spurious IRQ vector
1237 value |= SPURIOUS_APIC_VECTOR;
1238 apic_write(APIC_SPIV, value);
1241 * Set up LVT0, LVT1:
1243 * set up through-local-APIC on the BP's LINT0. This is not
1244 * strictly necessary in pure symmetric-IO mode, but sometimes
1245 * we delegate interrupts to the 8259A.
1248 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1250 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1251 if (!smp_processor_id() && (pic_mode || !value)) {
1252 value = APIC_DM_EXTINT;
1253 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1254 smp_processor_id());
1256 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1257 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1258 smp_processor_id());
1260 apic_write(APIC_LVT0, value);
1263 * only the BP should see the LINT1 NMI signal, obviously.
1265 if (!smp_processor_id())
1266 value = APIC_DM_NMI;
1268 value = APIC_DM_NMI | APIC_LVT_MASKED;
1269 if (!lapic_is_integrated()) /* 82489DX */
1270 value |= APIC_LVT_LEVEL_TRIGGER;
1271 apic_write(APIC_LVT1, value);
1276 void __cpuinit end_local_APIC_setup(void)
1280 #ifdef CONFIG_X86_32
1283 /* Disable the local apic timer */
1284 value = apic_read(APIC_LVTT);
1285 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1286 apic_write(APIC_LVTT, value);
1290 setup_apic_nmi_watchdog(NULL);
1295 void check_x2apic(void)
1299 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1301 if (msr & X2APIC_ENABLE) {
1302 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1303 x2apic_preenabled = x2apic = 1;
1304 apic_ops = &x2apic_ops;
1308 void enable_x2apic(void)
1312 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1313 if (!(msr & X2APIC_ENABLE)) {
1314 printk("Enabling x2apic\n");
1315 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1319 void __init enable_IR_x2apic(void)
1321 #ifdef CONFIG_INTR_REMAP
1323 unsigned long flags;
1325 if (!cpu_has_x2apic)
1328 if (!x2apic_preenabled && disable_x2apic) {
1330 "Skipped enabling x2apic and Interrupt-remapping "
1331 "because of nox2apic\n");
1335 if (x2apic_preenabled && disable_x2apic)
1336 panic("Bios already enabled x2apic, can't enforce nox2apic");
1338 if (!x2apic_preenabled && skip_ioapic_setup) {
1340 "Skipped enabling x2apic and Interrupt-remapping "
1341 "because of skipping io-apic setup\n");
1345 ret = dmar_table_init();
1348 "dmar_table_init() failed with %d:\n", ret);
1350 if (x2apic_preenabled)
1351 panic("x2apic enabled by bios. But IR enabling failed");
1354 "Not enabling x2apic,Intr-remapping\n");
1358 local_irq_save(flags);
1361 ret = save_mask_IO_APIC_setup();
1363 printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret);
1367 ret = enable_intr_remapping(1);
1369 if (ret && x2apic_preenabled) {
1370 local_irq_restore(flags);
1371 panic("x2apic enabled by bios. But IR enabling failed");
1379 apic_ops = &x2apic_ops;
1386 * IR enabling failed
1388 restore_IO_APIC_setup();
1390 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1394 local_irq_restore(flags);
1397 if (!x2apic_preenabled)
1399 "Enabled x2apic and interrupt-remapping\n");
1402 "Enabled Interrupt-remapping\n");
1405 "Failed to enable Interrupt-remapping and x2apic\n");
1407 if (!cpu_has_x2apic)
1410 if (x2apic_preenabled)
1411 panic("x2apic enabled prior OS handover,"
1412 " enable CONFIG_INTR_REMAP");
1414 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1420 #endif /* HAVE_X2APIC */
1422 #ifdef CONFIG_X86_64
1424 * Detect and enable local APICs on non-SMP boards.
1425 * Original code written by Keir Fraser.
1426 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1427 * not correctly set up (usually the APIC timer won't work etc.)
1429 static int __init detect_init_APIC(void)
1431 if (!cpu_has_apic) {
1432 printk(KERN_INFO "No local APIC present\n");
1436 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1437 boot_cpu_physical_apicid = 0;
1442 * Detect and initialize APIC
1444 static int __init detect_init_APIC(void)
1448 /* Disabled by kernel option? */
1452 switch (boot_cpu_data.x86_vendor) {
1453 case X86_VENDOR_AMD:
1454 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1455 (boot_cpu_data.x86 == 15))
1458 case X86_VENDOR_INTEL:
1459 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1460 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1467 if (!cpu_has_apic) {
1469 * Over-ride BIOS and try to enable the local APIC only if
1470 * "lapic" specified.
1472 if (!force_enable_local_apic) {
1473 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1474 "you can enable it with \"lapic\"\n");
1478 * Some BIOSes disable the local APIC in the APIC_BASE
1479 * MSR. This can only be done in software for Intel P6 or later
1480 * and AMD K7 (Model > 1) or later.
1482 rdmsr(MSR_IA32_APICBASE, l, h);
1483 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1485 "Local APIC disabled by BIOS -- reenabling.\n");
1486 l &= ~MSR_IA32_APICBASE_BASE;
1487 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1488 wrmsr(MSR_IA32_APICBASE, l, h);
1489 enabled_via_apicbase = 1;
1493 * The APIC feature bit should now be enabled
1496 features = cpuid_edx(1);
1497 if (!(features & (1 << X86_FEATURE_APIC))) {
1498 printk(KERN_WARNING "Could not enable APIC!\n");
1501 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1502 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1504 /* The BIOS may have set up the APIC at some other address */
1505 rdmsr(MSR_IA32_APICBASE, l, h);
1506 if (l & MSR_IA32_APICBASE_ENABLE)
1507 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1509 printk(KERN_INFO "Found and enabled local APIC!\n");
1516 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1521 #ifdef CONFIG_X86_64
1522 void __init early_init_lapic_mapping(void)
1524 unsigned long phys_addr;
1527 * If no local APIC can be found then go out
1528 * : it means there is no mpatable and MADT
1530 if (!smp_found_config)
1533 phys_addr = mp_lapic_addr;
1535 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1536 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1537 APIC_BASE, phys_addr);
1540 * Fetch the APIC ID of the BSP in case we have a
1541 * default configuration (or the MP table is broken).
1543 boot_cpu_physical_apicid = read_apic_id();
1548 * init_apic_mappings - initialize APIC mappings
1550 void __init init_apic_mappings(void)
1554 boot_cpu_physical_apicid = read_apic_id();
1560 * If no local APIC can be found then set up a fake all
1561 * zeroes page to simulate the local APIC and another
1562 * one for the IO-APIC.
1564 if (!smp_found_config && detect_init_APIC()) {
1565 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1566 apic_phys = __pa(apic_phys);
1568 apic_phys = mp_lapic_addr;
1570 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1571 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1572 APIC_BASE, apic_phys);
1575 * Fetch the APIC ID of the BSP in case we have a
1576 * default configuration (or the MP table is broken).
1578 if (boot_cpu_physical_apicid == -1U)
1579 boot_cpu_physical_apicid = read_apic_id();
1583 * This initializes the IO-APIC and APIC hardware if this is
1586 int apic_version[MAX_APICS];
1588 int __init APIC_init_uniprocessor(void)
1590 #ifdef CONFIG_X86_64
1592 printk(KERN_INFO "Apic disabled\n");
1595 if (!cpu_has_apic) {
1597 printk(KERN_INFO "Apic disabled by BIOS\n");
1601 if (!smp_found_config && !cpu_has_apic)
1605 * Complain if the BIOS pretends there is one.
1607 if (!cpu_has_apic &&
1608 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1609 printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n",
1610 boot_cpu_physical_apicid);
1611 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1619 #ifdef CONFIG_X86_64
1620 setup_apic_routing();
1623 verify_local_APIC();
1626 #ifdef CONFIG_X86_64
1627 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1630 * Hack: In case of kdump, after a crash, kernel might be booting
1631 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1632 * might be zero if read from MP tables. Get it from LAPIC.
1634 # ifdef CONFIG_CRASH_DUMP
1635 boot_cpu_physical_apicid = read_apic_id();
1638 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1641 #ifdef CONFIG_X86_64
1643 * Now enable IO-APICs, actually call clear_IO_APIC
1644 * We need clear_IO_APIC before enabling vector on BP
1646 if (!skip_ioapic_setup && nr_ioapics)
1650 #ifdef CONFIG_X86_IO_APIC
1651 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1653 localise_nmi_watchdog();
1654 end_local_APIC_setup();
1656 #ifdef CONFIG_X86_IO_APIC
1657 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1659 # ifdef CONFIG_X86_64
1665 #ifdef CONFIG_X86_64
1666 setup_boot_APIC_clock();
1667 check_nmi_watchdog();
1676 * Local APIC interrupts
1680 * This interrupt should _never_ happen with our APIC/SMP architecture
1682 void smp_spurious_interrupt(struct pt_regs *regs)
1686 #ifdef CONFIG_X86_64
1691 * Check if this really is a spurious interrupt and ACK it
1692 * if it is a vectored one. Just in case...
1693 * Spurious interrupts should not be ACKed.
1695 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1696 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1699 #ifdef CONFIG_X86_64
1700 add_pda(irq_spurious_count, 1);
1702 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1703 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1704 "should never happen.\n", smp_processor_id());
1705 __get_cpu_var(irq_stat).irq_spurious_count++;
1711 * This interrupt should never happen with our APIC/SMP architecture
1713 void smp_error_interrupt(struct pt_regs *regs)
1717 #ifdef CONFIG_X86_64
1721 /* First tickle the hardware, only then report what went on. -- REW */
1722 v = apic_read(APIC_ESR);
1723 apic_write(APIC_ESR, 0);
1724 v1 = apic_read(APIC_ESR);
1726 atomic_inc(&irq_err_count);
1728 /* Here is what the APIC error bits mean:
1731 2: Send accept error
1732 3: Receive accept error
1734 5: Send illegal vector
1735 6: Received illegal vector
1736 7: Illegal register address
1738 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1739 smp_processor_id(), v , v1);
1744 * connect_bsp_APIC - attach the APIC to the interrupt system
1746 void __init connect_bsp_APIC(void)
1748 #ifdef CONFIG_X86_32
1751 * Do not trust the local APIC being empty at bootup.
1755 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1756 * local APIC to INT and NMI lines.
1758 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1759 "enabling APIC mode.\n");
1768 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1769 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1771 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1774 void disconnect_bsp_APIC(int virt_wire_setup)
1778 #ifdef CONFIG_X86_32
1781 * Put the board back into PIC mode (has an effect only on
1782 * certain older boards). Note that APIC interrupts, including
1783 * IPIs, won't work beyond this point! The only exception are
1786 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1787 "entering PIC mode.\n");
1794 /* Go back to Virtual Wire compatibility mode */
1796 /* For the spurious interrupt use vector F, and enable it */
1797 value = apic_read(APIC_SPIV);
1798 value &= ~APIC_VECTOR_MASK;
1799 value |= APIC_SPIV_APIC_ENABLED;
1801 apic_write(APIC_SPIV, value);
1803 if (!virt_wire_setup) {
1805 * For LVT0 make it edge triggered, active high,
1806 * external and enabled
1808 value = apic_read(APIC_LVT0);
1809 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1810 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1811 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1812 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1813 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1814 apic_write(APIC_LVT0, value);
1817 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1821 * For LVT1 make it edge triggered, active high,
1824 value = apic_read(APIC_LVT1);
1825 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1826 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1827 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1828 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1829 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1830 apic_write(APIC_LVT1, value);
1833 void __cpuinit generic_processor_info(int apicid, int version)
1841 if (version == 0x0) {
1842 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1843 "fixing up to 0x10. (tell your hw vendor)\n",
1847 apic_version[apicid] = version;
1849 if (num_processors >= NR_CPUS) {
1850 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1851 " Processor ignored.\n", NR_CPUS);
1856 cpus_complement(tmp_map, cpu_present_map);
1857 cpu = first_cpu(tmp_map);
1859 physid_set(apicid, phys_cpu_present_map);
1860 if (apicid == boot_cpu_physical_apicid) {
1862 * x86_bios_cpu_apicid is required to have processors listed
1863 * in same order as logical cpu numbers. Hence the first
1864 * entry is BSP, and so on.
1868 if (apicid > max_physical_apicid)
1869 max_physical_apicid = apicid;
1871 #ifdef CONFIG_X86_32
1873 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1874 * but we need to work other dependencies like SMP_SUSPEND etc
1875 * before this can be done without some confusion.
1876 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1877 * - Ashok Raj <ashok.raj@intel.com>
1879 if (max_physical_apicid >= 8) {
1880 switch (boot_cpu_data.x86_vendor) {
1881 case X86_VENDOR_INTEL:
1882 if (!APIC_XAPIC(version)) {
1886 /* If P4 and above fall through */
1887 case X86_VENDOR_AMD:
1893 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1894 /* are we being called early in kernel startup? */
1895 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1896 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1897 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1899 cpu_to_apicid[cpu] = apicid;
1900 bios_cpu_apicid[cpu] = apicid;
1902 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1903 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1907 cpu_set(cpu, cpu_possible_map);
1908 cpu_set(cpu, cpu_present_map);
1911 #ifdef CONFIG_X86_64
1912 int hard_smp_processor_id(void)
1914 return read_apic_id();
1925 * 'active' is true if the local APIC was enabled by us and
1926 * not the BIOS; this signifies that we are also responsible
1927 * for disabling it before entering apm/acpi suspend
1930 /* r/w apic fields */
1931 unsigned int apic_id;
1932 unsigned int apic_taskpri;
1933 unsigned int apic_ldr;
1934 unsigned int apic_dfr;
1935 unsigned int apic_spiv;
1936 unsigned int apic_lvtt;
1937 unsigned int apic_lvtpc;
1938 unsigned int apic_lvt0;
1939 unsigned int apic_lvt1;
1940 unsigned int apic_lvterr;
1941 unsigned int apic_tmict;
1942 unsigned int apic_tdcr;
1943 unsigned int apic_thmr;
1946 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1948 unsigned long flags;
1951 if (!apic_pm_state.active)
1954 maxlvt = lapic_get_maxlvt();
1956 apic_pm_state.apic_id = apic_read(APIC_ID);
1957 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1958 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1959 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1960 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1961 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1963 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1964 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1965 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1966 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1967 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1968 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1969 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1971 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1974 local_irq_save(flags);
1975 disable_local_APIC();
1976 local_irq_restore(flags);
1980 static int lapic_resume(struct sys_device *dev)
1983 unsigned long flags;
1986 if (!apic_pm_state.active)
1989 maxlvt = lapic_get_maxlvt();
1991 local_irq_save(flags);
2000 * Make sure the APICBASE points to the right address
2002 * FIXME! This will be wrong if we ever support suspend on
2003 * SMP! We'll need to do this as part of the CPU restore!
2005 rdmsr(MSR_IA32_APICBASE, l, h);
2006 l &= ~MSR_IA32_APICBASE_BASE;
2007 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2008 wrmsr(MSR_IA32_APICBASE, l, h);
2011 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2012 apic_write(APIC_ID, apic_pm_state.apic_id);
2013 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2014 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2015 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2016 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2017 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2018 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2019 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2021 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2024 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2025 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2026 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2027 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2028 apic_write(APIC_ESR, 0);
2029 apic_read(APIC_ESR);
2030 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2031 apic_write(APIC_ESR, 0);
2032 apic_read(APIC_ESR);
2034 local_irq_restore(flags);
2040 * This device has no shutdown method - fully functioning local APICs
2041 * are needed on every CPU up until machine_halt/restart/poweroff.
2044 static struct sysdev_class lapic_sysclass = {
2046 .resume = lapic_resume,
2047 .suspend = lapic_suspend,
2050 static struct sys_device device_lapic = {
2052 .cls = &lapic_sysclass,
2055 static void __cpuinit apic_pm_activate(void)
2057 apic_pm_state.active = 1;
2060 static int __init init_lapic_sysfs(void)
2066 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2068 error = sysdev_class_register(&lapic_sysclass);
2070 error = sysdev_register(&device_lapic);
2073 device_initcall(init_lapic_sysfs);
2075 #else /* CONFIG_PM */
2077 static void apic_pm_activate(void) { }
2079 #endif /* CONFIG_PM */
2081 #ifdef CONFIG_X86_64
2083 * apic_is_clustered_box() -- Check if we can expect good TSC
2085 * Thus far, the major user of this is IBM's Summit2 series:
2087 * Clustered boxes may have unsynced TSC problems if they are
2088 * multi-chassis. Use available data to take a good guess.
2089 * If in doubt, go HPET.
2091 __cpuinit int apic_is_clustered_box(void)
2093 int i, clusters, zeros;
2095 u16 *bios_cpu_apicid;
2096 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2099 * there is not this kind of box with AMD CPU yet.
2100 * Some AMD box with quadcore cpu and 8 sockets apicid
2101 * will be [4, 0x23] or [8, 0x27] could be thought to
2102 * vsmp box still need checking...
2104 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2107 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2108 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2110 for (i = 0; i < NR_CPUS; i++) {
2111 /* are we being called early in kernel startup? */
2112 if (bios_cpu_apicid) {
2113 id = bios_cpu_apicid[i];
2115 else if (i < nr_cpu_ids) {
2117 id = per_cpu(x86_bios_cpu_apicid, i);
2124 if (id != BAD_APICID)
2125 __set_bit(APIC_CLUSTERID(id), clustermap);
2128 /* Problem: Partially populated chassis may not have CPUs in some of
2129 * the APIC clusters they have been allocated. Only present CPUs have
2130 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2131 * Since clusters are allocated sequentially, count zeros only if
2132 * they are bounded by ones.
2136 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2137 if (test_bit(i, clustermap)) {
2138 clusters += 1 + zeros;
2144 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2145 * not guaranteed to be synced between boards
2147 if (is_vsmp_box() && clusters > 1)
2151 * If clusters > 2, then should be multi-chassis.
2152 * May have to revisit this when multi-core + hyperthreaded CPUs come
2153 * out, but AFAIK this will work even for them.
2155 return (clusters > 2);
2160 * APIC command line parameters
2162 static int __init setup_disableapic(char *arg)
2165 setup_clear_cpu_cap(X86_FEATURE_APIC);
2168 early_param("disableapic", setup_disableapic);
2170 /* same as disableapic, for compatibility */
2171 static int __init setup_nolapic(char *arg)
2173 return setup_disableapic(arg);
2175 early_param("nolapic", setup_nolapic);
2177 static int __init parse_lapic_timer_c2_ok(char *arg)
2179 local_apic_timer_c2_ok = 1;
2182 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2184 static int __init parse_disable_apic_timer(char *arg)
2186 disable_apic_timer = 1;
2189 early_param("noapictimer", parse_disable_apic_timer);
2191 static int __init parse_nolapic_timer(char *arg)
2193 disable_apic_timer = 1;
2196 early_param("nolapic_timer", parse_nolapic_timer);
2198 static int __init apic_set_verbosity(char *arg)
2201 #ifdef CONFIG_X86_64
2202 skip_ioapic_setup = 0;
2208 if (strcmp("debug", arg) == 0)
2209 apic_verbosity = APIC_DEBUG;
2210 else if (strcmp("verbose", arg) == 0)
2211 apic_verbosity = APIC_VERBOSE;
2213 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
2214 " use apic=verbose or apic=debug\n", arg);
2220 early_param("apic", apic_set_verbosity);
2222 static int __init lapic_insert_resource(void)
2227 /* Put local APIC into the resource map. */
2228 lapic_resource.start = apic_phys;
2229 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2230 insert_resource(&iomem_resource, &lapic_resource);
2236 * need call insert after e820_reserve_resources()
2237 * that is using request_resource
2239 late_initcall(lapic_insert_resource);