arch/x86/kernel/apic/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/apic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 void arch_disable_smp_support(void)
 102 {
 103 #ifdef CONFIG_PCI
 104         noioapicquirk = 1;
 105         noioapicreroute = -1;
 106 #endif
 107         skip_ioapic_setup = 1;
 108 }
 109
 110 static int __init parse_noapic(char *str)
 111 {
 112         /* disable IO-APIC */
 113         arch_disable_smp_support();
 114         return 0;
 115 }
 116 early_param("noapic", parse_noapic);
 117
 118 struct irq_pin_list;
 119
 120 /*
 121  * This is performance-critical, we want to do it O(1)
 122  *
 123  * the indexing order of this array favors 1:1 mappings
 124  * between pins and IRQs.
 125  */
 126
 127 struct irq_pin_list {
 128         int apic, pin;
 129         struct irq_pin_list *next;
 130 };
 131
 132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 133 {
 134         struct irq_pin_list *pin;
 135         int node;
 136
 137         node = cpu_to_node(cpu);
 138
 139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 140
 141         return pin;
 142 }
 143
 144 struct irq_cfg {
 145         struct irq_pin_list *irq_2_pin;
 146         cpumask_var_t domain;
 147         cpumask_var_t old_domain;
 148         unsigned move_cleanup_count;
 149         u8 vector;
 150         u8 move_in_progress : 1;
 151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 152         u8 move_desc_pending : 1;
 153 #endif
 154 };
 155
 156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 157 #ifdef CONFIG_SPARSE_IRQ
 158 static struct irq_cfg irq_cfgx[] = {
 159 #else
 160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 161 #endif
 162         [0]  = { .vector = IRQ0_VECTOR,  },
 163         [1]  = { .vector = IRQ1_VECTOR,  },
 164         [2]  = { .vector = IRQ2_VECTOR,  },
 165         [3]  = { .vector = IRQ3_VECTOR,  },
 166         [4]  = { .vector = IRQ4_VECTOR,  },
 167         [5]  = { .vector = IRQ5_VECTOR,  },
 168         [6]  = { .vector = IRQ6_VECTOR,  },
 169         [7]  = { .vector = IRQ7_VECTOR,  },
 170         [8]  = { .vector = IRQ8_VECTOR,  },
 171         [9]  = { .vector = IRQ9_VECTOR,  },
 172         [10] = { .vector = IRQ10_VECTOR, },
 173         [11] = { .vector = IRQ11_VECTOR, },
 174         [12] = { .vector = IRQ12_VECTOR, },
 175         [13] = { .vector = IRQ13_VECTOR, },
 176         [14] = { .vector = IRQ14_VECTOR, },
 177         [15] = { .vector = IRQ15_VECTOR, },
 178 };
 179
 180 int __init arch_early_irq_init(void)
 181 {
 182         struct irq_cfg *cfg;
 183         struct irq_desc *desc;
 184         int count;
 185         int i;
 186
 187         cfg = irq_cfgx;
 188         count = ARRAY_SIZE(irq_cfgx);
 189
 190         for (i = 0; i < count; i++) {
 191                 desc = irq_to_desc(i);
 192                 desc->chip_data = &cfg[i];
 193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 195                 if (i < NR_IRQS_LEGACY)
 196                         cpumask_setall(cfg[i].domain);
 197         }
 198
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPARSE_IRQ
 203 static struct irq_cfg *irq_cfg(unsigned int irq)
 204 {
 205         struct irq_cfg *cfg = NULL;
 206         struct irq_desc *desc;
 207
 208         desc = irq_to_desc(irq);
 209         if (desc)
 210                 cfg = desc->chip_data;
 211
 212         return cfg;
 213 }
 214
 215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 216 {
 217         struct irq_cfg *cfg;
 218         int node;
 219
 220         node = cpu_to_node(cpu);
 221
 222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 223         if (cfg) {
 224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 225                         kfree(cfg);
 226                         cfg = NULL;
 227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 228                                                           GFP_ATOMIC, node)) {
 229                         free_cpumask_var(cfg->domain);
 230                         kfree(cfg);
 231                         cfg = NULL;
 232                 } else {
 233                         cpumask_clear(cfg->domain);
 234                         cpumask_clear(cfg->old_domain);
 235                 }
 236         }
 237
 238         return cfg;
 239 }
 240
 241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 242 {
 243         struct irq_cfg *cfg;
 244
 245         cfg = desc->chip_data;
 246         if (!cfg) {
 247                 desc->chip_data = get_one_free_irq_cfg(cpu);
 248                 if (!desc->chip_data) {
 249                         printk(KERN_ERR "can not alloc irq_cfg\n");
 250                         BUG_ON(1);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 258
 259 static void
 260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 261 {
 262         struct irq_pin_list *old_entry, *head, *tail, *entry;
 263
 264         cfg->irq_2_pin = NULL;
 265         old_entry = old_cfg->irq_2_pin;
 266         if (!old_entry)
 267                 return;
 268
 269         entry = get_one_free_irq_2_pin(cpu);
 270         if (!entry)
 271                 return;
 272
 273         entry->apic     = old_entry->apic;
 274         entry->pin      = old_entry->pin;
 275         head            = entry;
 276         tail            = entry;
 277         old_entry       = old_entry->next;
 278         while (old_entry) {
 279                 entry = get_one_free_irq_2_pin(cpu);
 280                 if (!entry) {
 281                         entry = head;
 282                         while (entry) {
 283                                 head = entry->next;
 284                                 kfree(entry);
 285                                 entry = head;
 286                         }
 287                         /* still use the old one */
 288                         return;
 289                 }
 290                 entry->apic     = old_entry->apic;
 291                 entry->pin      = old_entry->pin;
 292                 tail->next      = entry;
 293                 tail            = entry;
 294                 old_entry       = old_entry->next;
 295         }
 296
 297         tail->next = NULL;
 298         cfg->irq_2_pin = head;
 299 }
 300
 301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 302 {
 303         struct irq_pin_list *entry, *next;
 304
 305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 306                 return;
 307
 308         entry = old_cfg->irq_2_pin;
 309
 310         while (entry) {
 311                 next = entry->next;
 312                 kfree(entry);
 313                 entry = next;
 314         }
 315         old_cfg->irq_2_pin = NULL;
 316 }
 317
 318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 319                                  struct irq_desc *desc, int cpu)
 320 {
 321         struct irq_cfg *cfg;
 322         struct irq_cfg *old_cfg;
 323
 324         cfg = get_one_free_irq_cfg(cpu);
 325
 326         if (!cfg)
 327                 return;
 328
 329         desc->chip_data = cfg;
 330
 331         old_cfg = old_desc->chip_data;
 332
 333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 334
 335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 336 }
 337
 338 static void free_irq_cfg(struct irq_cfg *old_cfg)
 339 {
 340         kfree(old_cfg);
 341 }
 342
 343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 344 {
 345         struct irq_cfg *old_cfg, *cfg;
 346
 347         old_cfg = old_desc->chip_data;
 348         cfg = desc->chip_data;
 349
 350         if (old_cfg == cfg)
 351                 return;
 352
 353         if (old_cfg) {
 354                 free_irq_2_pin(old_cfg, cfg);
 355                 free_irq_cfg(old_cfg);
 356                 old_desc->chip_data = NULL;
 357         }
 358 }
 359
 360 static void
 361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 362 {
 363         struct irq_cfg *cfg = desc->chip_data;
 364
 365         if (!cfg->move_in_progress) {
 366                 /* it means that domain is not changed */
 367                 if (!cpumask_intersects(desc->affinity, mask))
 368                         cfg->move_desc_pending = 1;
 369         }
 370 }
 371 #endif
 372
 373 #else
 374 static struct irq_cfg *irq_cfg(unsigned int irq)
 375 {
 376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 377 }
 378
 379 #endif
 380
 381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 382 static inline void
 383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 384 {
 385 }
 386 #endif
 387
 388 struct io_apic {
 389         unsigned int index;
 390         unsigned int unused[3];
 391         unsigned int data;
 392         unsigned int unused2[11];
 393         unsigned int eoi;
 394 };
 395
 396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 397 {
 398         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 399                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 400 }
 401
 402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 403 {
 404         struct io_apic __iomem *io_apic = io_apic_base(apic);
 405         writel(vector, &io_apic->eoi);
 406 }
 407
 408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 409 {
 410         struct io_apic __iomem *io_apic = io_apic_base(apic);
 411         writel(reg, &io_apic->index);
 412         return readl(&io_apic->data);
 413 }
 414
 415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 416 {
 417         struct io_apic __iomem *io_apic = io_apic_base(apic);
 418         writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 /*
 423  * Re-write a value: to be used for read-modify-write
 424  * cycles where the read already set up the index register.
 425  *
 426  * Older SiS APIC requires we rewrite the index register
 427  */
 428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 429 {
 430         struct io_apic __iomem *io_apic = io_apic_base(apic);
 431
 432         if (sis_apic_bug)
 433                 writel(reg, &io_apic->index);
 434         writel(value, &io_apic->data);
 435 }
 436
 437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 438 {
 439         struct irq_pin_list *entry;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&ioapic_lock, flags);
 443         entry = cfg->irq_2_pin;
 444         for (;;) {
 445                 unsigned int reg;
 446                 int pin;
 447
 448                 if (!entry)
 449                         break;
 450                 pin = entry->pin;
 451                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 452                 /* Is the remote IRR bit set? */
 453                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 454                         spin_unlock_irqrestore(&ioapic_lock, flags);
 455                         return true;
 456                 }
 457                 if (!entry->next)
 458                         break;
 459                 entry = entry->next;
 460         }
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462
 463         return false;
 464 }
 465
 466 union entry_union {
 467         struct { u32 w1, w2; };
 468         struct IO_APIC_route_entry entry;
 469 };
 470
 471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 472 {
 473         union entry_union eu;
 474         unsigned long flags;
 475         spin_lock_irqsave(&ioapic_lock, flags);
 476         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 477         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 478         spin_unlock_irqrestore(&ioapic_lock, flags);
 479         return eu.entry;
 480 }
 481
 482 /*
 483  * When we write a new IO APIC routing entry, we need to write the high
 484  * word first! If the mask bit in the low word is clear, we will enable
 485  * the interrupt, and we need to make sure the entry is fully populated
 486  * before that happens.
 487  */
 488 static void
 489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 490 {
 491         union entry_union eu;
 492         eu.entry = e;
 493         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 494         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 495 }
 496
 497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 498 {
 499         unsigned long flags;
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         __ioapic_write_entry(apic, pin, e);
 502         spin_unlock_irqrestore(&ioapic_lock, flags);
 503 }
 504
 505 /*
 506  * When we mask an IO APIC routing entry, we need to write the low
 507  * word first, in order to set the mask bit before we change the
 508  * high bits!
 509  */
 510 static void ioapic_mask_entry(int apic, int pin)
 511 {
 512         unsigned long flags;
 513         union entry_union eu = { .entry.mask = 1 };
 514
 515         spin_lock_irqsave(&ioapic_lock, flags);
 516         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 517         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 518         spin_unlock_irqrestore(&ioapic_lock, flags);
 519 }
 520
 521 #ifdef CONFIG_SMP
 522 static void send_cleanup_vector(struct irq_cfg *cfg)
 523 {
 524         cpumask_var_t cleanup_mask;
 525
 526         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 527                 unsigned int i;
 528                 cfg->move_cleanup_count = 0;
 529                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 530                         cfg->move_cleanup_count++;
 531                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 532                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 533         } else {
 534                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 535                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 536                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 537                 free_cpumask_var(cleanup_mask);
 538         }
 539         cfg->move_in_progress = 0;
 540 }
 541
 542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 543 {
 544         int apic, pin;
 545         struct irq_pin_list *entry;
 546         u8 vector = cfg->vector;
 547
 548         entry = cfg->irq_2_pin;
 549         for (;;) {
 550                 unsigned int reg;
 551
 552                 if (!entry)
 553                         break;
 554
 555                 apic = entry->apic;
 556                 pin = entry->pin;
 557                 /*
 558                  * With interrupt-remapping, destination information comes
 559                  * from interrupt-remapping table entry.
 560                  */
 561                 if (!irq_remapped(irq))
 562                         io_apic_write(apic, 0x11 + pin*2, dest);
 563                 reg = io_apic_read(apic, 0x10 + pin*2);
 564                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 565                 reg |= vector;
 566                 io_apic_modify(apic, 0x10 + pin*2, reg);
 567                 if (!entry->next)
 568                         break;
 569                 entry = entry->next;
 570         }
 571 }
 572
 573 static int
 574 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 575
 576 /*
 577  * Either sets desc->affinity to a valid value, and returns
 578  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 579  * leaves desc->affinity untouched.
 580  */
 581 static unsigned int
 582 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 583 {
 584         struct irq_cfg *cfg;
 585         unsigned int irq;
 586
 587         if (!cpumask_intersects(mask, cpu_online_mask))
 588                 return BAD_APICID;
 589
 590         irq = desc->irq;
 591         cfg = desc->chip_data;
 592         if (assign_irq_vector(irq, cfg, mask))
 593                 return BAD_APICID;
 594
 595         cpumask_and(desc->affinity, cfg->domain, mask);
 596         set_extra_move_desc(desc, mask);
 597
 598         return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
 599 }
 600
 601 static void
 602 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 603 {
 604         struct irq_cfg *cfg;
 605         unsigned long flags;
 606         unsigned int dest;
 607         unsigned int irq;
 608
 609         irq = desc->irq;
 610         cfg = desc->chip_data;
 611
 612         spin_lock_irqsave(&ioapic_lock, flags);
 613         dest = set_desc_affinity(desc, mask);
 614         if (dest != BAD_APICID) {
 615                 /* Only the high 8 bits are valid. */
 616                 dest = SET_APIC_LOGICAL_ID(dest);
 617                 __target_IO_APIC_irq(irq, dest, cfg);
 618         }
 619         spin_unlock_irqrestore(&ioapic_lock, flags);
 620 }
 621
 622 static void
 623 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 624 {
 625         struct irq_desc *desc;
 626
 627         desc = irq_to_desc(irq);
 628
 629         set_ioapic_affinity_irq_desc(desc, mask);
 630 }
 631 #endif /* CONFIG_SMP */
 632
 633 /*
 634  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 635  * shared ISA-space IRQs, so we have to support them. We are super
 636  * fast in the common case, and fast for shared ISA-space IRQs.
 637  */
 638 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 639 {
 640         struct irq_pin_list *entry;
 641
 642         entry = cfg->irq_2_pin;
 643         if (!entry) {
 644                 entry = get_one_free_irq_2_pin(cpu);
 645                 if (!entry) {
 646                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 647                                         apic, pin);
 648                         return;
 649                 }
 650                 cfg->irq_2_pin = entry;
 651                 entry->apic = apic;
 652                 entry->pin = pin;
 653                 return;
 654         }
 655
 656         while (entry->next) {
 657                 /* not again, please */
 658                 if (entry->apic == apic && entry->pin == pin)
 659                         return;
 660
 661                 entry = entry->next;
 662         }
 663
 664         entry->next = get_one_free_irq_2_pin(cpu);
 665         entry = entry->next;
 666         entry->apic = apic;
 667         entry->pin = pin;
 668 }
 669
 670 /*
 671  * Reroute an IRQ to a different pin.
 672  */
 673 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 674                                       int oldapic, int oldpin,
 675                                       int newapic, int newpin)
 676 {
 677         struct irq_pin_list *entry = cfg->irq_2_pin;
 678         int replaced = 0;
 679
 680         while (entry) {
 681                 if (entry->apic == oldapic && entry->pin == oldpin) {
 682                         entry->apic = newapic;
 683                         entry->pin = newpin;
 684                         replaced = 1;
 685                         /* every one is different, right? */
 686                         break;
 687                 }
 688                 entry = entry->next;
 689         }
 690
 691         /* why? call replace before add? */
 692         if (!replaced)
 693                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 694 }
 695
 696 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 697                                 int mask_and, int mask_or,
 698                                 void (*final)(struct irq_pin_list *entry))
 699 {
 700         int pin;
 701         struct irq_pin_list *entry;
 702
 703         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 704                 unsigned int reg;
 705                 pin = entry->pin;
 706                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 707                 reg &= mask_and;
 708                 reg |= mask_or;
 709                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 710                 if (final)
 711                         final(entry);
 712         }
 713 }
 714
 715 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 716 {
 717         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 718 }
 719
 720 #ifdef CONFIG_X86_64
 721 static void io_apic_sync(struct irq_pin_list *entry)
 722 {
 723         /*
 724          * Synchronize the IO-APIC and the CPU by doing
 725          * a dummy read from the IO-APIC
 726          */
 727         struct io_apic __iomem *io_apic;
 728         io_apic = io_apic_base(entry->apic);
 729         readl(&io_apic->data);
 730 }
 731
 732 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 733 {
 734         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 735 }
 736 #else /* CONFIG_X86_32 */
 737 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 738 {
 739         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 740 }
 741
 742 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 743 {
 744         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 745                         IO_APIC_REDIR_MASKED, NULL);
 746 }
 747
 748 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 749 {
 750         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 751                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 752 }
 753 #endif /* CONFIG_X86_32 */
 754
 755 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 756 {
 757         struct irq_cfg *cfg = desc->chip_data;
 758         unsigned long flags;
 759
 760         BUG_ON(!cfg);
 761
 762         spin_lock_irqsave(&ioapic_lock, flags);
 763         __mask_IO_APIC_irq(cfg);
 764         spin_unlock_irqrestore(&ioapic_lock, flags);
 765 }
 766
 767 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 768 {
 769         struct irq_cfg *cfg = desc->chip_data;
 770         unsigned long flags;
 771
 772         spin_lock_irqsave(&ioapic_lock, flags);
 773         __unmask_IO_APIC_irq(cfg);
 774         spin_unlock_irqrestore(&ioapic_lock, flags);
 775 }
 776
 777 static void mask_IO_APIC_irq(unsigned int irq)
 778 {
 779         struct irq_desc *desc = irq_to_desc(irq);
 780
 781         mask_IO_APIC_irq_desc(desc);
 782 }
 783 static void unmask_IO_APIC_irq(unsigned int irq)
 784 {
 785         struct irq_desc *desc = irq_to_desc(irq);
 786
 787         unmask_IO_APIC_irq_desc(desc);
 788 }
 789
 790 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 791 {
 792         struct IO_APIC_route_entry entry;
 793
 794         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 795         entry = ioapic_read_entry(apic, pin);
 796         if (entry.delivery_mode == dest_SMI)
 797                 return;
 798         /*
 799          * Disable it in the IO-APIC irq-routing table:
 800          */
 801         ioapic_mask_entry(apic, pin);
 802 }
 803
 804 static void clear_IO_APIC (void)
 805 {
 806         int apic, pin;
 807
 808         for (apic = 0; apic < nr_ioapics; apic++)
 809                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 810                         clear_IO_APIC_pin(apic, pin);
 811 }
 812
 813 #ifdef CONFIG_X86_32
 814 /*
 815  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 816  * specific CPU-side IRQs.
 817  */
 818
 819 #define MAX_PIRQS 8
 820 static int pirq_entries[MAX_PIRQS] = {
 821         [0 ... MAX_PIRQS - 1] = -1
 822 };
 823
 824 static int __init ioapic_pirq_setup(char *str)
 825 {
 826         int i, max;
 827         int ints[MAX_PIRQS+1];
 828
 829         get_options(str, ARRAY_SIZE(ints), ints);
 830
 831         apic_printk(APIC_VERBOSE, KERN_INFO
 832                         "PIRQ redirection, working around broken MP-BIOS.\n");
 833         max = MAX_PIRQS;
 834         if (ints[0] < MAX_PIRQS)
 835                 max = ints[0];
 836
 837         for (i = 0; i < max; i++) {
 838                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 839                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 840                 /*
 841                  * PIRQs are mapped upside down, usually.
 842                  */
 843                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 844         }
 845         return 1;
 846 }
 847
 848 __setup("pirq=", ioapic_pirq_setup);
 849 #endif /* CONFIG_X86_32 */
 850
 851 #ifdef CONFIG_INTR_REMAP
 852 /* I/O APIC RTE contents at the OS boot up */
 853 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 854
 855 /*
 856  * Saves all the IO-APIC RTE's
 857  */
 858 int save_IO_APIC_setup(void)
 859 {
 860         union IO_APIC_reg_01 reg_01;
 861         unsigned long flags;
 862         int apic, pin;
 863
 864         /*
 865          * The number of IO-APIC IRQ registers (== #pins):
 866          */
 867         for (apic = 0; apic < nr_ioapics; apic++) {
 868                 spin_lock_irqsave(&ioapic_lock, flags);
 869                 reg_01.raw = io_apic_read(apic, 1);
 870                 spin_unlock_irqrestore(&ioapic_lock, flags);
 871                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 872         }
 873
 874         for (apic = 0; apic < nr_ioapics; apic++) {
 875                 early_ioapic_entries[apic] =
 876                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 877                                 nr_ioapic_registers[apic], GFP_KERNEL);
 878                 if (!early_ioapic_entries[apic])
 879                         goto nomem;
 880         }
 881
 882         for (apic = 0; apic < nr_ioapics; apic++)
 883                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 884                         early_ioapic_entries[apic][pin] =
 885                                 ioapic_read_entry(apic, pin);
 886
 887         return 0;
 888
 889 nomem:
 890         while (apic >= 0)
 891                 kfree(early_ioapic_entries[apic--]);
 892         memset(early_ioapic_entries, 0,
 893                 ARRAY_SIZE(early_ioapic_entries));
 894
 895         return -ENOMEM;
 896 }
 897
 898 void mask_IO_APIC_setup(void)
 899 {
 900         int apic, pin;
 901
 902         for (apic = 0; apic < nr_ioapics; apic++) {
 903                 if (!early_ioapic_entries[apic])
 904                         break;
 905                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 906                         struct IO_APIC_route_entry entry;
 907
 908                         entry = early_ioapic_entries[apic][pin];
 909                         if (!entry.mask) {
 910                                 entry.mask = 1;
 911                                 ioapic_write_entry(apic, pin, entry);
 912                         }
 913                 }
 914         }
 915 }
 916
 917 void restore_IO_APIC_setup(void)
 918 {
 919         int apic, pin;
 920
 921         for (apic = 0; apic < nr_ioapics; apic++) {
 922                 if (!early_ioapic_entries[apic])
 923                         break;
 924                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 925                         ioapic_write_entry(apic, pin,
 926                                            early_ioapic_entries[apic][pin]);
 927                 kfree(early_ioapic_entries[apic]);
 928                 early_ioapic_entries[apic] = NULL;
 929         }
 930 }
 931
 932 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 933 {
 934         /*
 935          * for now plain restore of previous settings.
 936          * TBD: In the case of OS enabling interrupt-remapping,
 937          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 938          * table entries. for now, do a plain restore, and wait for
 939          * the setup_IO_APIC_irqs() to do proper initialization.
 940          */
 941         restore_IO_APIC_setup();
 942 }
 943 #endif
 944
 945 /*
 946  * Find the IRQ entry number of a certain pin.
 947  */
 948 static int find_irq_entry(int apic, int pin, int type)
 949 {
 950         int i;
 951
 952         for (i = 0; i < mp_irq_entries; i++)
 953                 if (mp_irqs[i].irqtype == type &&
 954                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 955                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 956                     mp_irqs[i].dstirq == pin)
 957                         return i;
 958
 959         return -1;
 960 }
 961
 962 /*
 963  * Find the pin to which IRQ[irq] (ISA) is connected
 964  */
 965 static int __init find_isa_irq_pin(int irq, int type)
 966 {
 967         int i;
 968
 969         for (i = 0; i < mp_irq_entries; i++) {
 970                 int lbus = mp_irqs[i].srcbus;
 971
 972                 if (test_bit(lbus, mp_bus_not_pci) &&
 973                     (mp_irqs[i].irqtype == type) &&
 974                     (mp_irqs[i].srcbusirq == irq))
 975
 976                         return mp_irqs[i].dstirq;
 977         }
 978         return -1;
 979 }
 980
 981 static int __init find_isa_irq_apic(int irq, int type)
 982 {
 983         int i;
 984
 985         for (i = 0; i < mp_irq_entries; i++) {
 986                 int lbus = mp_irqs[i].srcbus;
 987
 988                 if (test_bit(lbus, mp_bus_not_pci) &&
 989                     (mp_irqs[i].irqtype == type) &&
 990                     (mp_irqs[i].srcbusirq == irq))
 991                         break;
 992         }
 993         if (i < mp_irq_entries) {
 994                 int apic;
 995                 for(apic = 0; apic < nr_ioapics; apic++) {
 996                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 997                                 return apic;
 998                 }
 999         }
1000
1001         return -1;
1002 }
1003
1004 /*
1005  * Find a specific PCI IRQ entry.
1006  * Not an __init, possibly needed by modules
1007  */
1008 static int pin_2_irq(int idx, int apic, int pin);
1009
1010 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1011 {
1012         int apic, i, best_guess = -1;
1013
1014         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1015                 bus, slot, pin);
1016         if (test_bit(bus, mp_bus_not_pci)) {
1017                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1018                 return -1;
1019         }
1020         for (i = 0; i < mp_irq_entries; i++) {
1021                 int lbus = mp_irqs[i].srcbus;
1022
1023                 for (apic = 0; apic < nr_ioapics; apic++)
1024                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1025                             mp_irqs[i].dstapic == MP_APIC_ALL)
1026                                 break;
1027
1028                 if (!test_bit(lbus, mp_bus_not_pci) &&
1029                     !mp_irqs[i].irqtype &&
1030                     (bus == lbus) &&
1031                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1032                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1033
1034                         if (!(apic || IO_APIC_IRQ(irq)))
1035                                 continue;
1036
1037                         if (pin == (mp_irqs[i].srcbusirq & 3))
1038                                 return irq;
1039                         /*
1040                          * Use the first all-but-pin matching entry as a
1041                          * best-guess fuzzy result for broken mptables.
1042                          */
1043                         if (best_guess < 0)
1044                                 best_guess = irq;
1045                 }
1046         }
1047         return best_guess;
1048 }
1049
1050 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1051
1052 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1053 /*
1054  * EISA Edge/Level control register, ELCR
1055  */
1056 static int EISA_ELCR(unsigned int irq)
1057 {
1058         if (irq < NR_IRQS_LEGACY) {
1059                 unsigned int port = 0x4d0 + (irq >> 3);
1060                 return (inb(port) >> (irq & 7)) & 1;
1061         }
1062         apic_printk(APIC_VERBOSE, KERN_INFO
1063                         "Broken MPtable reports ISA irq %d\n", irq);
1064         return 0;
1065 }
1066
1067 #endif
1068
1069 /* ISA interrupts are always polarity zero edge triggered,
1070  * when listed as conforming in the MP table. */
1071
1072 #define default_ISA_trigger(idx)        (0)
1073 #define default_ISA_polarity(idx)       (0)
1074
1075 /* EISA interrupts are always polarity zero and can be edge or level
1076  * trigger depending on the ELCR value.  If an interrupt is listed as
1077  * EISA conforming in the MP table, that means its trigger type must
1078  * be read in from the ELCR */
1079
1080 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1081 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1082
1083 /* PCI interrupts are always polarity one level triggered,
1084  * when listed as conforming in the MP table. */
1085
1086 #define default_PCI_trigger(idx)        (1)
1087 #define default_PCI_polarity(idx)       (1)
1088
1089 /* MCA interrupts are always polarity zero level triggered,
1090  * when listed as conforming in the MP table. */
1091
1092 #define default_MCA_trigger(idx)        (1)
1093 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1094
1095 static int MPBIOS_polarity(int idx)
1096 {
1097         int bus = mp_irqs[idx].srcbus;
1098         int polarity;
1099
1100         /*
1101          * Determine IRQ line polarity (high active or low active):
1102          */
1103         switch (mp_irqs[idx].irqflag & 3)
1104         {
1105                 case 0: /* conforms, ie. bus-type dependent polarity */
1106                         if (test_bit(bus, mp_bus_not_pci))
1107                                 polarity = default_ISA_polarity(idx);
1108                         else
1109                                 polarity = default_PCI_polarity(idx);
1110                         break;
1111                 case 1: /* high active */
1112                 {
1113                         polarity = 0;
1114                         break;
1115                 }
1116                 case 2: /* reserved */
1117                 {
1118                         printk(KERN_WARNING "broken BIOS!!\n");
1119                         polarity = 1;
1120                         break;
1121                 }
1122                 case 3: /* low active */
1123                 {
1124                         polarity = 1;
1125                         break;
1126                 }
1127                 default: /* invalid */
1128                 {
1129                         printk(KERN_WARNING "broken BIOS!!\n");
1130                         polarity = 1;
1131                         break;
1132                 }
1133         }
1134         return polarity;
1135 }
1136
1137 static int MPBIOS_trigger(int idx)
1138 {
1139         int bus = mp_irqs[idx].srcbus;
1140         int trigger;
1141
1142         /*
1143          * Determine IRQ trigger mode (edge or level sensitive):
1144          */
1145         switch ((mp_irqs[idx].irqflag>>2) & 3)
1146         {
1147                 case 0: /* conforms, ie. bus-type dependent */
1148                         if (test_bit(bus, mp_bus_not_pci))
1149                                 trigger = default_ISA_trigger(idx);
1150                         else
1151                                 trigger = default_PCI_trigger(idx);
1152 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1153                         switch (mp_bus_id_to_type[bus]) {
1154                                 case MP_BUS_ISA: /* ISA pin */
1155                                 {
1156                                         /* set before the switch */
1157                                         break;
1158                                 }
1159                                 case MP_BUS_EISA: /* EISA pin */
1160                                 {
1161                                         trigger = default_EISA_trigger(idx);
1162                                         break;
1163                                 }
1164                                 case MP_BUS_PCI: /* PCI pin */
1165                                 {
1166                                         /* set before the switch */
1167                                         break;
1168                                 }
1169                                 case MP_BUS_MCA: /* MCA pin */
1170                                 {
1171                                         trigger = default_MCA_trigger(idx);
1172                                         break;
1173                                 }
1174                                 default:
1175                                 {
1176                                         printk(KERN_WARNING "broken BIOS!!\n");
1177                                         trigger = 1;
1178                                         break;
1179                                 }
1180                         }
1181 #endif
1182                         break;
1183                 case 1: /* edge */
1184                 {
1185                         trigger = 0;
1186                         break;
1187                 }
1188                 case 2: /* reserved */
1189                 {
1190                         printk(KERN_WARNING "broken BIOS!!\n");
1191                         trigger = 1;
1192                         break;
1193                 }
1194                 case 3: /* level */
1195                 {
1196                         trigger = 1;
1197                         break;
1198                 }
1199                 default: /* invalid */
1200                 {
1201                         printk(KERN_WARNING "broken BIOS!!\n");
1202                         trigger = 0;
1203                         break;
1204                 }
1205         }
1206         return trigger;
1207 }
1208
1209 static inline int irq_polarity(int idx)
1210 {
1211         return MPBIOS_polarity(idx);
1212 }
1213
1214 static inline int irq_trigger(int idx)
1215 {
1216         return MPBIOS_trigger(idx);
1217 }
1218
1219 int (*ioapic_renumber_irq)(int ioapic, int irq);
1220 static int pin_2_irq(int idx, int apic, int pin)
1221 {
1222         int irq, i;
1223         int bus = mp_irqs[idx].srcbus;
1224
1225         /*
1226          * Debugging check, we are in big trouble if this message pops up!
1227          */
1228         if (mp_irqs[idx].dstirq != pin)
1229                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1230
1231         if (test_bit(bus, mp_bus_not_pci)) {
1232                 irq = mp_irqs[idx].srcbusirq;
1233         } else {
1234                 /*
1235                  * PCI IRQs are mapped in order
1236                  */
1237                 i = irq = 0;
1238                 while (i < apic)
1239                         irq += nr_ioapic_registers[i++];
1240                 irq += pin;
1241                 /*
1242                  * For MPS mode, so far only needed by ES7000 platform
1243                  */
1244                 if (ioapic_renumber_irq)
1245                         irq = ioapic_renumber_irq(apic, irq);
1246         }
1247
1248 #ifdef CONFIG_X86_32
1249         /*
1250          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1251          */
1252         if ((pin >= 16) && (pin <= 23)) {
1253                 if (pirq_entries[pin-16] != -1) {
1254                         if (!pirq_entries[pin-16]) {
1255                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256                                                 "disabling PIRQ%d\n", pin-16);
1257                         } else {
1258                                 irq = pirq_entries[pin-16];
1259                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1260                                                 "using PIRQ%d -> IRQ %d\n",
1261                                                 pin-16, irq);
1262                         }
1263                 }
1264         }
1265 #endif
1266
1267         return irq;
1268 }
1269
1270 void lock_vector_lock(void)
1271 {
1272         /* Used to the online set of cpus does not change
1273          * during assign_irq_vector.
1274          */
1275         spin_lock(&vector_lock);
1276 }
1277
1278 void unlock_vector_lock(void)
1279 {
1280         spin_unlock(&vector_lock);
1281 }
1282
1283 static int
1284 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1285 {
1286         /*
1287          * NOTE! The local APIC isn't very good at handling
1288          * multiple interrupts at the same interrupt level.
1289          * As the interrupt level is determined by taking the
1290          * vector number and shifting that right by 4, we
1291          * want to spread these out a bit so that they don't
1292          * all fall in the same interrupt level.
1293          *
1294          * Also, we've got to be careful not to trash gate
1295          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1296          */
1297         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1298         unsigned int old_vector;
1299         int cpu, err;
1300         cpumask_var_t tmp_mask;
1301
1302         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1303                 return -EBUSY;
1304
1305         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1306                 return -ENOMEM;
1307
1308         old_vector = cfg->vector;
1309         if (old_vector) {
1310                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1311                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1312                 if (!cpumask_empty(tmp_mask)) {
1313                         free_cpumask_var(tmp_mask);
1314                         return 0;
1315                 }
1316         }
1317
1318         /* Only try and allocate irqs on cpus that are present */
1319         err = -ENOSPC;
1320         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1321                 int new_cpu;
1322                 int vector, offset;
1323
1324                 apic->vector_allocation_domain(cpu, tmp_mask);
1325
1326                 vector = current_vector;
1327                 offset = current_offset;
1328 next:
1329                 vector += 8;
1330                 if (vector >= first_system_vector) {
1331                         /* If out of vectors on large boxen, must share them. */
1332                         offset = (offset + 1) % 8;
1333                         vector = FIRST_DEVICE_VECTOR + offset;
1334                 }
1335                 if (unlikely(current_vector == vector))
1336                         continue;
1337
1338                 if (test_bit(vector, used_vectors))
1339                         goto next;
1340
1341                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1342                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1343                                 goto next;
1344                 /* Found one! */
1345                 current_vector = vector;
1346                 current_offset = offset;
1347                 if (old_vector) {
1348                         cfg->move_in_progress = 1;
1349                         cpumask_copy(cfg->old_domain, cfg->domain);
1350                 }
1351                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1352                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1353                 cfg->vector = vector;
1354                 cpumask_copy(cfg->domain, tmp_mask);
1355                 err = 0;
1356                 break;
1357         }
1358         free_cpumask_var(tmp_mask);
1359         return err;
1360 }
1361
1362 static int
1363 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1364 {
1365         int err;
1366         unsigned long flags;
1367
1368         spin_lock_irqsave(&vector_lock, flags);
1369         err = __assign_irq_vector(irq, cfg, mask);
1370         spin_unlock_irqrestore(&vector_lock, flags);
1371         return err;
1372 }
1373
1374 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1375 {
1376         int cpu, vector;
1377
1378         BUG_ON(!cfg->vector);
1379
1380         vector = cfg->vector;
1381         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1382                 per_cpu(vector_irq, cpu)[vector] = -1;
1383
1384         cfg->vector = 0;
1385         cpumask_clear(cfg->domain);
1386
1387         if (likely(!cfg->move_in_progress))
1388                 return;
1389         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1390                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1391                                                                 vector++) {
1392                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1393                                 continue;
1394                         per_cpu(vector_irq, cpu)[vector] = -1;
1395                         break;
1396                 }
1397         }
1398         cfg->move_in_progress = 0;
1399 }
1400
1401 void __setup_vector_irq(int cpu)
1402 {
1403         /* Initialize vector_irq on a new cpu */
1404         /* This function must be called with vector_lock held */
1405         int irq, vector;
1406         struct irq_cfg *cfg;
1407         struct irq_desc *desc;
1408
1409         /* Mark the inuse vectors */
1410         for_each_irq_desc(irq, desc) {
1411                 cfg = desc->chip_data;
1412                 if (!cpumask_test_cpu(cpu, cfg->domain))
1413                         continue;
1414                 vector = cfg->vector;
1415                 per_cpu(vector_irq, cpu)[vector] = irq;
1416         }
1417         /* Mark the free vectors */
1418         for (vector = 0; vector < NR_VECTORS; ++vector) {
1419                 irq = per_cpu(vector_irq, cpu)[vector];
1420                 if (irq < 0)
1421                         continue;
1422
1423                 cfg = irq_cfg(irq);
1424                 if (!cpumask_test_cpu(cpu, cfg->domain))
1425                         per_cpu(vector_irq, cpu)[vector] = -1;
1426         }
1427 }
1428
1429 static struct irq_chip ioapic_chip;
1430 static struct irq_chip ir_ioapic_chip;
1431
1432 #define IOAPIC_AUTO     -1
1433 #define IOAPIC_EDGE     0
1434 #define IOAPIC_LEVEL    1
1435
1436 #ifdef CONFIG_X86_32
1437 static inline int IO_APIC_irq_trigger(int irq)
1438 {
1439         int apic, idx, pin;
1440
1441         for (apic = 0; apic < nr_ioapics; apic++) {
1442                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1443                         idx = find_irq_entry(apic, pin, mp_INT);
1444                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1445                                 return irq_trigger(idx);
1446                 }
1447         }
1448         /*
1449          * nonexistent IRQs are edge default
1450          */
1451         return 0;
1452 }
1453 #else
1454 static inline int IO_APIC_irq_trigger(int irq)
1455 {
1456         return 1;
1457 }
1458 #endif
1459
1460 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1461 {
1462
1463         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1464             trigger == IOAPIC_LEVEL)
1465                 desc->status |= IRQ_LEVEL;
1466         else
1467                 desc->status &= ~IRQ_LEVEL;
1468
1469         if (irq_remapped(irq)) {
1470                 desc->status |= IRQ_MOVE_PCNTXT;
1471                 if (trigger)
1472                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1473                                                       handle_fasteoi_irq,
1474                                                      "fasteoi");
1475                 else
1476                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1477                                                       handle_edge_irq, "edge");
1478                 return;
1479         }
1480
1481         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1482             trigger == IOAPIC_LEVEL)
1483                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1484                                               handle_fasteoi_irq,
1485                                               "fasteoi");
1486         else
1487                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1488                                               handle_edge_irq, "edge");
1489 }
1490
1491 int setup_ioapic_entry(int apic_id, int irq,
1492                        struct IO_APIC_route_entry *entry,
1493                        unsigned int destination, int trigger,
1494                        int polarity, int vector, int pin)
1495 {
1496         /*
1497          * add it to the IO-APIC irq-routing table:
1498          */
1499         memset(entry,0,sizeof(*entry));
1500
1501         if (intr_remapping_enabled) {
1502                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1503                 struct irte irte;
1504                 struct IR_IO_APIC_route_entry *ir_entry =
1505                         (struct IR_IO_APIC_route_entry *) entry;
1506                 int index;
1507
1508                 if (!iommu)
1509                         panic("No mapping iommu for ioapic %d\n", apic_id);
1510
1511                 index = alloc_irte(iommu, irq, 1);
1512                 if (index < 0)
1513                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1514
1515                 memset(&irte, 0, sizeof(irte));
1516
1517                 irte.present = 1;
1518                 irte.dst_mode = apic->irq_dest_mode;
1519                 /*
1520                  * Trigger mode in the IRTE will always be edge, and the
1521                  * actual level or edge trigger will be setup in the IO-APIC
1522                  * RTE. This will help simplify level triggered irq migration.
1523                  * For more details, see the comments above explainig IO-APIC
1524                  * irq migration in the presence of interrupt-remapping.
1525                  */
1526                 irte.trigger_mode = 0;
1527                 irte.dlvry_mode = apic->irq_delivery_mode;
1528                 irte.vector = vector;
1529                 irte.dest_id = IRTE_DEST(destination);
1530
1531                 modify_irte(irq, &irte);
1532
1533                 ir_entry->index2 = (index >> 15) & 0x1;
1534                 ir_entry->zero = 0;
1535                 ir_entry->format = 1;
1536                 ir_entry->index = (index & 0x7fff);
1537                 /*
1538                  * IO-APIC RTE will be configured with virtual vector.
1539                  * irq handler will do the explicit EOI to the io-apic.
1540                  */
1541                 ir_entry->vector = pin;
1542         } else {
1543                 entry->delivery_mode = apic->irq_delivery_mode;
1544                 entry->dest_mode = apic->irq_dest_mode;
1545                 entry->dest = destination;
1546                 entry->vector = vector;
1547         }
1548
1549         entry->mask = 0;                                /* enable IRQ */
1550         entry->trigger = trigger;
1551         entry->polarity = polarity;
1552
1553         /* Mask level triggered irqs.
1554          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1555          */
1556         if (trigger)
1557                 entry->mask = 1;
1558         return 0;
1559 }
1560
1561 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1562                               int trigger, int polarity)
1563 {
1564         struct irq_cfg *cfg;
1565         struct IO_APIC_route_entry entry;
1566         unsigned int dest;
1567
1568         if (!IO_APIC_IRQ(irq))
1569                 return;
1570
1571         cfg = desc->chip_data;
1572
1573         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1574                 return;
1575
1576         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1577
1578         apic_printk(APIC_VERBOSE,KERN_DEBUG
1579                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1580                     "IRQ %d Mode:%i Active:%i)\n",
1581                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1582                     irq, trigger, polarity);
1583
1584
1585         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1586                                dest, trigger, polarity, cfg->vector, pin)) {
1587                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1588                        mp_ioapics[apic_id].apicid, pin);
1589                 __clear_irq_vector(irq, cfg);
1590                 return;
1591         }
1592
1593         ioapic_register_intr(irq, desc, trigger);
1594         if (irq < NR_IRQS_LEGACY)
1595                 disable_8259A_irq(irq);
1596
1597         ioapic_write_entry(apic_id, pin, entry);
1598 }
1599
1600 static void __init setup_IO_APIC_irqs(void)
1601 {
1602         int apic_id, pin, idx, irq;
1603         int notcon = 0;
1604         struct irq_desc *desc;
1605         struct irq_cfg *cfg;
1606         int cpu = boot_cpu_id;
1607
1608         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1609
1610         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1611                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1612
1613                         idx = find_irq_entry(apic_id, pin, mp_INT);
1614                         if (idx == -1) {
1615                                 if (!notcon) {
1616                                         notcon = 1;
1617                                         apic_printk(APIC_VERBOSE,
1618                                                 KERN_DEBUG " %d-%d",
1619                                                 mp_ioapics[apic_id].apicid, pin);
1620                                 } else
1621                                         apic_printk(APIC_VERBOSE, " %d-%d",
1622                                                 mp_ioapics[apic_id].apicid, pin);
1623                                 continue;
1624                         }
1625                         if (notcon) {
1626                                 apic_printk(APIC_VERBOSE,
1627                                         " (apicid-pin) not connected\n");
1628                                 notcon = 0;
1629                         }
1630
1631                         irq = pin_2_irq(idx, apic_id, pin);
1632
1633                         /*
1634                          * Skip the timer IRQ if there's a quirk handler
1635                          * installed and if it returns 1:
1636                          */
1637                         if (apic->multi_timer_check &&
1638                                         apic->multi_timer_check(apic_id, irq))
1639                                 continue;
1640
1641                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1642                         if (!desc) {
1643                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1644                                 continue;
1645                         }
1646                         cfg = desc->chip_data;
1647                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1648
1649                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1650                                         irq_trigger(idx), irq_polarity(idx));
1651                 }
1652         }
1653
1654         if (notcon)
1655                 apic_printk(APIC_VERBOSE,
1656                         " (apicid-pin) not connected\n");
1657 }
1658
1659 /*
1660  * Set up the timer pin, possibly with the 8259A-master behind.
1661  */
1662 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1663                                         int vector)
1664 {
1665         struct IO_APIC_route_entry entry;
1666
1667         if (intr_remapping_enabled)
1668                 return;
1669
1670         memset(&entry, 0, sizeof(entry));
1671
1672         /*
1673          * We use logical delivery to get the timer IRQ
1674          * to the first CPU.
1675          */
1676         entry.dest_mode = apic->irq_dest_mode;
1677         entry.mask = 0;                 /* don't mask IRQ for edge */
1678         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1679         entry.delivery_mode = apic->irq_delivery_mode;
1680         entry.polarity = 0;
1681         entry.trigger = 0;
1682         entry.vector = vector;
1683
1684         /*
1685          * The timer IRQ doesn't have to know that behind the
1686          * scene we may have a 8259A-master in AEOI mode ...
1687          */
1688         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1689
1690         /*
1691          * Add it to the IO-APIC irq-routing table:
1692          */
1693         ioapic_write_entry(apic_id, pin, entry);
1694 }
1695
1696
1697 __apicdebuginit(void) print_IO_APIC(void)
1698 {
1699         int apic, i;
1700         union IO_APIC_reg_00 reg_00;
1701         union IO_APIC_reg_01 reg_01;
1702         union IO_APIC_reg_02 reg_02;
1703         union IO_APIC_reg_03 reg_03;
1704         unsigned long flags;
1705         struct irq_cfg *cfg;
1706         struct irq_desc *desc;
1707         unsigned int irq;
1708
1709         if (apic_verbosity == APIC_QUIET)
1710                 return;
1711
1712         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1713         for (i = 0; i < nr_ioapics; i++)
1714                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1715                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1716
1717         /*
1718          * We are a bit conservative about what we expect.  We have to
1719          * know about every hardware change ASAP.
1720          */
1721         printk(KERN_INFO "testing the IO APIC.......................\n");
1722
1723         for (apic = 0; apic < nr_ioapics; apic++) {
1724
1725         spin_lock_irqsave(&ioapic_lock, flags);
1726         reg_00.raw = io_apic_read(apic, 0);
1727         reg_01.raw = io_apic_read(apic, 1);
1728         if (reg_01.bits.version >= 0x10)
1729                 reg_02.raw = io_apic_read(apic, 2);
1730         if (reg_01.bits.version >= 0x20)
1731                 reg_03.raw = io_apic_read(apic, 3);
1732         spin_unlock_irqrestore(&ioapic_lock, flags);
1733
1734         printk("\n");
1735         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1736         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1737         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1738         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1739         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1740
1741         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1742         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1743
1744         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1745         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1746
1747         /*
1748          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1749          * but the value of reg_02 is read as the previous read register
1750          * value, so ignore it if reg_02 == reg_01.
1751          */
1752         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1753                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1754                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1755         }
1756
1757         /*
1758          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1759          * or reg_03, but the value of reg_0[23] is read as the previous read
1760          * register value, so ignore it if reg_03 == reg_0[12].
1761          */
1762         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1763             reg_03.raw != reg_01.raw) {
1764                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1765                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1766         }
1767
1768         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1769
1770         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1771                           " Stat Dmod Deli Vect:   \n");
1772
1773         for (i = 0; i <= reg_01.bits.entries; i++) {
1774                 struct IO_APIC_route_entry entry;
1775
1776                 entry = ioapic_read_entry(apic, i);
1777
1778                 printk(KERN_DEBUG " %02x %03X ",
1779                         i,
1780                         entry.dest
1781                 );
1782
1783                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1784                         entry.mask,
1785                         entry.trigger,
1786                         entry.irr,
1787                         entry.polarity,
1788                         entry.delivery_status,
1789                         entry.dest_mode,
1790                         entry.delivery_mode,
1791                         entry.vector
1792                 );
1793         }
1794         }
1795         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1796         for_each_irq_desc(irq, desc) {
1797                 struct irq_pin_list *entry;
1798
1799                 cfg = desc->chip_data;
1800                 entry = cfg->irq_2_pin;
1801                 if (!entry)
1802                         continue;
1803                 printk(KERN_DEBUG "IRQ%d ", irq);
1804                 for (;;) {
1805                         printk("-> %d:%d", entry->apic, entry->pin);
1806                         if (!entry->next)
1807                                 break;
1808                         entry = entry->next;
1809                 }
1810                 printk("\n");
1811         }
1812
1813         printk(KERN_INFO ".................................... done.\n");
1814
1815         return;
1816 }
1817
1818 __apicdebuginit(void) print_APIC_bitfield(int base)
1819 {
1820         unsigned int v;
1821         int i, j;
1822
1823         if (apic_verbosity == APIC_QUIET)
1824                 return;
1825
1826         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1827         for (i = 0; i < 8; i++) {
1828                 v = apic_read(base + i*0x10);
1829                 for (j = 0; j < 32; j++) {
1830                         if (v & (1<<j))
1831                                 printk("1");
1832                         else
1833                                 printk("0");
1834                 }
1835                 printk("\n");
1836         }
1837 }
1838
1839 __apicdebuginit(void) print_local_APIC(void *dummy)
1840 {
1841         unsigned int v, ver, maxlvt;
1842         u64 icr;
1843
1844         if (apic_verbosity == APIC_QUIET)
1845                 return;
1846
1847         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1848                 smp_processor_id(), hard_smp_processor_id());
1849         v = apic_read(APIC_ID);
1850         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1851         v = apic_read(APIC_LVR);
1852         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1853         ver = GET_APIC_VERSION(v);
1854         maxlvt = lapic_get_maxlvt();
1855
1856         v = apic_read(APIC_TASKPRI);
1857         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1858
1859         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1860                 if (!APIC_XAPIC(ver)) {
1861                         v = apic_read(APIC_ARBPRI);
1862                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1863                                v & APIC_ARBPRI_MASK);
1864                 }
1865                 v = apic_read(APIC_PROCPRI);
1866                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1867         }
1868
1869         /*
1870          * Remote read supported only in the 82489DX and local APIC for
1871          * Pentium processors.
1872          */
1873         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1874                 v = apic_read(APIC_RRR);
1875                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1876         }
1877
1878         v = apic_read(APIC_LDR);
1879         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1880         if (!x2apic_enabled()) {
1881                 v = apic_read(APIC_DFR);
1882                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1883         }
1884         v = apic_read(APIC_SPIV);
1885         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1886
1887         printk(KERN_DEBUG "... APIC ISR field:\n");
1888         print_APIC_bitfield(APIC_ISR);
1889         printk(KERN_DEBUG "... APIC TMR field:\n");
1890         print_APIC_bitfield(APIC_TMR);
1891         printk(KERN_DEBUG "... APIC IRR field:\n");
1892         print_APIC_bitfield(APIC_IRR);
1893
1894         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1895                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1896                         apic_write(APIC_ESR, 0);
1897
1898                 v = apic_read(APIC_ESR);
1899                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1900         }
1901
1902         icr = apic_icr_read();
1903         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1904         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1905
1906         v = apic_read(APIC_LVTT);
1907         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1908
1909         if (maxlvt > 3) {                       /* PC is LVT#4. */
1910                 v = apic_read(APIC_LVTPC);
1911                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1912         }
1913         v = apic_read(APIC_LVT0);
1914         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1915         v = apic_read(APIC_LVT1);
1916         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1917
1918         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1919                 v = apic_read(APIC_LVTERR);
1920                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1921         }
1922
1923         v = apic_read(APIC_TMICT);
1924         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1925         v = apic_read(APIC_TMCCT);
1926         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1927         v = apic_read(APIC_TDCR);
1928         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1929         printk("\n");
1930 }
1931
1932 __apicdebuginit(void) print_all_local_APICs(void)
1933 {
1934         int cpu;
1935
1936         preempt_disable();
1937         for_each_online_cpu(cpu)
1938                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1939         preempt_enable();
1940 }
1941
1942 __apicdebuginit(void) print_PIC(void)
1943 {
1944         unsigned int v;
1945         unsigned long flags;
1946
1947         if (apic_verbosity == APIC_QUIET)
1948                 return;
1949
1950         printk(KERN_DEBUG "\nprinting PIC contents\n");
1951
1952         spin_lock_irqsave(&i8259A_lock, flags);
1953
1954         v = inb(0xa1) << 8 | inb(0x21);
1955         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1956
1957         v = inb(0xa0) << 8 | inb(0x20);
1958         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1959
1960         outb(0x0b,0xa0);
1961         outb(0x0b,0x20);
1962         v = inb(0xa0) << 8 | inb(0x20);
1963         outb(0x0a,0xa0);
1964         outb(0x0a,0x20);
1965
1966         spin_unlock_irqrestore(&i8259A_lock, flags);
1967
1968         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1969
1970         v = inb(0x4d1) << 8 | inb(0x4d0);
1971         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1972 }
1973
1974 __apicdebuginit(int) print_all_ICs(void)
1975 {
1976         print_PIC();
1977         print_all_local_APICs();
1978         print_IO_APIC();
1979
1980         return 0;
1981 }
1982
1983 fs_initcall(print_all_ICs);
1984
1985
1986 /* Where if anywhere is the i8259 connect in external int mode */
1987 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1988
1989 void __init enable_IO_APIC(void)
1990 {
1991         union IO_APIC_reg_01 reg_01;
1992         int i8259_apic, i8259_pin;
1993         int apic;
1994         unsigned long flags;
1995
1996         /*
1997          * The number of IO-APIC IRQ registers (== #pins):
1998          */
1999         for (apic = 0; apic < nr_ioapics; apic++) {
2000                 spin_lock_irqsave(&ioapic_lock, flags);
2001                 reg_01.raw = io_apic_read(apic, 1);
2002                 spin_unlock_irqrestore(&ioapic_lock, flags);
2003                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2004         }
2005         for(apic = 0; apic < nr_ioapics; apic++) {
2006                 int pin;
2007                 /* See if any of the pins is in ExtINT mode */
2008                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2009                         struct IO_APIC_route_entry entry;
2010                         entry = ioapic_read_entry(apic, pin);
2011
2012                         /* If the interrupt line is enabled and in ExtInt mode
2013                          * I have found the pin where the i8259 is connected.
2014                          */
2015                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2016                                 ioapic_i8259.apic = apic;
2017                                 ioapic_i8259.pin  = pin;
2018                                 goto found_i8259;
2019                         }
2020                 }
2021         }
2022  found_i8259:
2023         /* Look to see what if the MP table has reported the ExtINT */
2024         /* If we could not find the appropriate pin by looking at the ioapic
2025          * the i8259 probably is not connected the ioapic but give the
2026          * mptable a chance anyway.
2027          */
2028         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2029         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2030         /* Trust the MP table if nothing is setup in the hardware */
2031         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2032                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2033                 ioapic_i8259.pin  = i8259_pin;
2034                 ioapic_i8259.apic = i8259_apic;
2035         }
2036         /* Complain if the MP table and the hardware disagree */
2037         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2038                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2039         {
2040                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2041         }
2042
2043         /*
2044          * Do not trust the IO-APIC being empty at bootup
2045          */
2046         clear_IO_APIC();
2047 }
2048
2049 /*
2050  * Not an __init, needed by the reboot code
2051  */
2052 void disable_IO_APIC(void)
2053 {
2054         /*
2055          * Clear the IO-APIC before rebooting:
2056          */
2057         clear_IO_APIC();
2058
2059         /*
2060          * If the i8259 is routed through an IOAPIC
2061          * Put that IOAPIC in virtual wire mode
2062          * so legacy interrupts can be delivered.
2063          *
2064          * With interrupt-remapping, for now we will use virtual wire A mode,
2065          * as virtual wire B is little complex (need to configure both
2066          * IOAPIC RTE aswell as interrupt-remapping table entry).
2067          * As this gets called during crash dump, keep this simple for now.
2068          */
2069         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2070                 struct IO_APIC_route_entry entry;
2071
2072                 memset(&entry, 0, sizeof(entry));
2073                 entry.mask            = 0; /* Enabled */
2074                 entry.trigger         = 0; /* Edge */
2075                 entry.irr             = 0;
2076                 entry.polarity        = 0; /* High */
2077                 entry.delivery_status = 0;
2078                 entry.dest_mode       = 0; /* Physical */
2079                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2080                 entry.vector          = 0;
2081                 entry.dest            = read_apic_id();
2082
2083                 /*
2084                  * Add it to the IO-APIC irq-routing table:
2085                  */
2086                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2087         }
2088
2089         /*
2090          * Use virtual wire A mode when interrupt remapping is enabled.
2091          */
2092         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2093 }
2094
2095 #ifdef CONFIG_X86_32
2096 /*
2097  * function to set the IO-APIC physical IDs based on the
2098  * values stored in the MPC table.
2099  *
2100  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2101  */
2102
2103 static void __init setup_ioapic_ids_from_mpc(void)
2104 {
2105         union IO_APIC_reg_00 reg_00;
2106         physid_mask_t phys_id_present_map;
2107         int apic_id;
2108         int i;
2109         unsigned char old_id;
2110         unsigned long flags;
2111
2112         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2113                 return;
2114
2115         /*
2116          * Don't check I/O APIC IDs for xAPIC systems.  They have
2117          * no meaning without the serial APIC bus.
2118          */
2119         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2120                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2121                 return;
2122         /*
2123          * This is broken; anything with a real cpu count has to
2124          * circumvent this idiocy regardless.
2125          */
2126         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2127
2128         /*
2129          * Set the IOAPIC ID to the value stored in the MPC table.
2130          */
2131         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2132
2133                 /* Read the register 0 value */
2134                 spin_lock_irqsave(&ioapic_lock, flags);
2135                 reg_00.raw = io_apic_read(apic_id, 0);
2136                 spin_unlock_irqrestore(&ioapic_lock, flags);
2137
2138                 old_id = mp_ioapics[apic_id].apicid;
2139
2140                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2141                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2142                                 apic_id, mp_ioapics[apic_id].apicid);
2143                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2144                                 reg_00.bits.ID);
2145                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2146                 }
2147
2148                 /*
2149                  * Sanity check, is the ID really free? Every APIC in a
2150                  * system must have a unique ID or we get lots of nice
2151                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2152                  */
2153                 if (apic->check_apicid_used(phys_id_present_map,
2154                                         mp_ioapics[apic_id].apicid)) {
2155                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2156                                 apic_id, mp_ioapics[apic_id].apicid);
2157                         for (i = 0; i < get_physical_broadcast(); i++)
2158                                 if (!physid_isset(i, phys_id_present_map))
2159                                         break;
2160                         if (i >= get_physical_broadcast())
2161                                 panic("Max APIC ID exceeded!\n");
2162                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2163                                 i);
2164                         physid_set(i, phys_id_present_map);
2165                         mp_ioapics[apic_id].apicid = i;
2166                 } else {
2167                         physid_mask_t tmp;
2168                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2169                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2170                                         "phys_id_present_map\n",
2171                                         mp_ioapics[apic_id].apicid);
2172                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2173                 }
2174
2175
2176                 /*
2177                  * We need to adjust the IRQ routing table
2178                  * if the ID changed.
2179                  */
2180                 if (old_id != mp_ioapics[apic_id].apicid)
2181                         for (i = 0; i < mp_irq_entries; i++)
2182                                 if (mp_irqs[i].dstapic == old_id)
2183                                         mp_irqs[i].dstapic
2184                                                 = mp_ioapics[apic_id].apicid;
2185
2186                 /*
2187                  * Read the right value from the MPC table and
2188                  * write it into the ID register.
2189                  */
2190                 apic_printk(APIC_VERBOSE, KERN_INFO
2191                         "...changing IO-APIC physical APIC ID to %d ...",
2192                         mp_ioapics[apic_id].apicid);
2193
2194                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2195                 spin_lock_irqsave(&ioapic_lock, flags);
2196                 io_apic_write(apic_id, 0, reg_00.raw);
2197                 spin_unlock_irqrestore(&ioapic_lock, flags);
2198
2199                 /*
2200                  * Sanity check
2201                  */
2202                 spin_lock_irqsave(&ioapic_lock, flags);
2203                 reg_00.raw = io_apic_read(apic_id, 0);
2204                 spin_unlock_irqrestore(&ioapic_lock, flags);
2205                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2206                         printk("could not set ID!\n");
2207                 else
2208                         apic_printk(APIC_VERBOSE, " ok.\n");
2209         }
2210 }
2211 #endif
2212
2213 int no_timer_check __initdata;
2214
2215 static int __init notimercheck(char *s)
2216 {
2217         no_timer_check = 1;
2218         return 1;
2219 }
2220 __setup("no_timer_check", notimercheck);
2221
2222 /*
2223  * There is a nasty bug in some older SMP boards, their mptable lies
2224  * about the timer IRQ. We do the following to work around the situation:
2225  *
2226  *      - timer IRQ defaults to IO-APIC IRQ
2227  *      - if this function detects that timer IRQs are defunct, then we fall
2228  *        back to ISA timer IRQs
2229  */
2230 static int __init timer_irq_works(void)
2231 {
2232         unsigned long t1 = jiffies;
2233         unsigned long flags;
2234
2235         if (no_timer_check)
2236                 return 1;
2237
2238         local_save_flags(flags);
2239         local_irq_enable();
2240         /* Let ten ticks pass... */
2241         mdelay((10 * 1000) / HZ);
2242         local_irq_restore(flags);
2243
2244         /*
2245          * Expect a few ticks at least, to be sure some possible
2246          * glue logic does not lock up after one or two first
2247          * ticks in a non-ExtINT mode.  Also the local APIC
2248          * might have cached one ExtINT interrupt.  Finally, at
2249          * least one tick may be lost due to delays.
2250          */
2251
2252         /* jiffies wrap? */
2253         if (time_after(jiffies, t1 + 4))
2254                 return 1;
2255         return 0;
2256 }
2257
2258 /*
2259  * In the SMP+IOAPIC case it might happen that there are an unspecified
2260  * number of pending IRQ events unhandled. These cases are very rare,
2261  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2262  * better to do it this way as thus we do not have to be aware of
2263  * 'pending' interrupts in the IRQ path, except at this point.
2264  */
2265 /*
2266  * Edge triggered needs to resend any interrupt
2267  * that was delayed but this is now handled in the device
2268  * independent code.
2269  */
2270
2271 /*
2272  * Starting up a edge-triggered IO-APIC interrupt is
2273  * nasty - we need to make sure that we get the edge.
2274  * If it is already asserted for some reason, we need
2275  * return 1 to indicate that is was pending.
2276  *
2277  * This is not complete - we should be able to fake
2278  * an edge even if it isn't on the 8259A...
2279  */
2280
2281 static unsigned int startup_ioapic_irq(unsigned int irq)
2282 {
2283         int was_pending = 0;
2284         unsigned long flags;
2285         struct irq_cfg *cfg;
2286
2287         spin_lock_irqsave(&ioapic_lock, flags);
2288         if (irq < NR_IRQS_LEGACY) {
2289                 disable_8259A_irq(irq);
2290                 if (i8259A_irq_pending(irq))
2291                         was_pending = 1;
2292         }
2293         cfg = irq_cfg(irq);
2294         __unmask_IO_APIC_irq(cfg);
2295         spin_unlock_irqrestore(&ioapic_lock, flags);
2296
2297         return was_pending;
2298 }
2299
2300 #ifdef CONFIG_X86_64
2301 static int ioapic_retrigger_irq(unsigned int irq)
2302 {
2303
2304         struct irq_cfg *cfg = irq_cfg(irq);
2305         unsigned long flags;
2306
2307         spin_lock_irqsave(&vector_lock, flags);
2308         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2309         spin_unlock_irqrestore(&vector_lock, flags);
2310
2311         return 1;
2312 }
2313 #else
2314 static int ioapic_retrigger_irq(unsigned int irq)
2315 {
2316         apic->send_IPI_self(irq_cfg(irq)->vector);
2317
2318         return 1;
2319 }
2320 #endif
2321
2322 /*
2323  * Level and edge triggered IO-APIC interrupts need different handling,
2324  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2325  * handled with the level-triggered descriptor, but that one has slightly
2326  * more overhead. Level-triggered interrupts cannot be handled with the
2327  * edge-triggered handler, without risking IRQ storms and other ugly
2328  * races.
2329  */
2330
2331 #ifdef CONFIG_SMP
2332
2333 #ifdef CONFIG_INTR_REMAP
2334
2335 /*
2336  * Migrate the IO-APIC irq in the presence of intr-remapping.
2337  *
2338  * For both level and edge triggered, irq migration is a simple atomic
2339  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2340  *
2341  * For level triggered, we eliminate the io-apic RTE modification (with the
2342  * updated vector information), by using a virtual vector (io-apic pin number).
2343  * Real vector that is used for interrupting cpu will be coming from
2344  * the interrupt-remapping table entry.
2345  */
2346 static void
2347 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2348 {
2349         struct irq_cfg *cfg;
2350         struct irte irte;
2351         unsigned int dest;
2352         unsigned int irq;
2353
2354         if (!cpumask_intersects(mask, cpu_online_mask))
2355                 return;
2356
2357         irq = desc->irq;
2358         if (get_irte(irq, &irte))
2359                 return;
2360
2361         cfg = desc->chip_data;
2362         if (assign_irq_vector(irq, cfg, mask))
2363                 return;
2364
2365         set_extra_move_desc(desc, mask);
2366
2367         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2368
2369         irte.vector = cfg->vector;
2370         irte.dest_id = IRTE_DEST(dest);
2371
2372         /*
2373          * Modified the IRTE and flushes the Interrupt entry cache.
2374          */
2375         modify_irte(irq, &irte);
2376
2377         if (cfg->move_in_progress)
2378                 send_cleanup_vector(cfg);
2379
2380         cpumask_copy(desc->affinity, mask);
2381 }
2382
2383 /*
2384  * Migrates the IRQ destination in the process context.
2385  */
2386 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2387                                             const struct cpumask *mask)
2388 {
2389         migrate_ioapic_irq_desc(desc, mask);
2390 }
2391 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2392                                        const struct cpumask *mask)
2393 {
2394         struct irq_desc *desc = irq_to_desc(irq);
2395
2396         set_ir_ioapic_affinity_irq_desc(desc, mask);
2397 }
2398 #else
2399 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2400                                                    const struct cpumask *mask)
2401 {
2402 }
2403 #endif
2404
2405 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2406 {
2407         unsigned vector, me;
2408
2409         ack_APIC_irq();
2410         exit_idle();
2411         irq_enter();
2412
2413         me = smp_processor_id();
2414         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2415                 unsigned int irq;
2416                 unsigned int irr;
2417                 struct irq_desc *desc;
2418                 struct irq_cfg *cfg;
2419                 irq = __get_cpu_var(vector_irq)[vector];
2420
2421                 if (irq == -1)
2422                         continue;
2423
2424                 desc = irq_to_desc(irq);
2425                 if (!desc)
2426                         continue;
2427
2428                 cfg = irq_cfg(irq);
2429                 spin_lock(&desc->lock);
2430                 if (!cfg->move_cleanup_count)
2431                         goto unlock;
2432
2433                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2434                         goto unlock;
2435
2436                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2437                 /*
2438                  * Check if the vector that needs to be cleanedup is
2439                  * registered at the cpu's IRR. If so, then this is not
2440                  * the best time to clean it up. Lets clean it up in the
2441                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2442                  * to myself.
2443                  */
2444                 if (irr  & (1 << (vector % 32))) {
2445                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2446                         goto unlock;
2447                 }
2448                 __get_cpu_var(vector_irq)[vector] = -1;
2449                 cfg->move_cleanup_count--;
2450 unlock:
2451                 spin_unlock(&desc->lock);
2452         }
2453
2454         irq_exit();
2455 }
2456
2457 static void irq_complete_move(struct irq_desc **descp)
2458 {
2459         struct irq_desc *desc = *descp;
2460         struct irq_cfg *cfg = desc->chip_data;
2461         unsigned vector, me;
2462
2463         if (likely(!cfg->move_in_progress)) {
2464 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2465                 if (likely(!cfg->move_desc_pending))
2466                         return;
2467
2468                 /* domain has not changed, but affinity did */
2469                 me = smp_processor_id();
2470                 if (cpumask_test_cpu(me, desc->affinity)) {
2471                         *descp = desc = move_irq_desc(desc, me);
2472                         /* get the new one */
2473                         cfg = desc->chip_data;
2474                         cfg->move_desc_pending = 0;
2475                 }
2476 #endif
2477                 return;
2478         }
2479
2480         vector = ~get_irq_regs()->orig_ax;
2481         me = smp_processor_id();
2482
2483         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2484 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2485                 *descp = desc = move_irq_desc(desc, me);
2486                 /* get the new one */
2487                 cfg = desc->chip_data;
2488 #endif
2489                 send_cleanup_vector(cfg);
2490         }
2491 }
2492 #else
2493 static inline void irq_complete_move(struct irq_desc **descp) {}
2494 #endif
2495
2496 #ifdef CONFIG_INTR_REMAP
2497 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2498 {
2499         int apic, pin;
2500         struct irq_pin_list *entry;
2501
2502         entry = cfg->irq_2_pin;
2503         for (;;) {
2504
2505                 if (!entry)
2506                         break;
2507
2508                 apic = entry->apic;
2509                 pin = entry->pin;
2510                 io_apic_eoi(apic, pin);
2511                 entry = entry->next;
2512         }
2513 }
2514
2515 static void
2516 eoi_ioapic_irq(struct irq_desc *desc)
2517 {
2518         struct irq_cfg *cfg;
2519         unsigned long flags;
2520         unsigned int irq;
2521
2522         irq = desc->irq;
2523         cfg = desc->chip_data;
2524
2525         spin_lock_irqsave(&ioapic_lock, flags);
2526         __eoi_ioapic_irq(irq, cfg);
2527         spin_unlock_irqrestore(&ioapic_lock, flags);
2528 }
2529
2530 static void ack_x2apic_level(unsigned int irq)
2531 {
2532         struct irq_desc *desc = irq_to_desc(irq);
2533         ack_x2APIC_irq();
2534         eoi_ioapic_irq(desc);
2535 }
2536
2537 static void ack_x2apic_edge(unsigned int irq)
2538 {
2539         ack_x2APIC_irq();
2540 }
2541
2542 #endif
2543
2544 static void ack_apic_edge(unsigned int irq)
2545 {
2546         struct irq_desc *desc = irq_to_desc(irq);
2547
2548         irq_complete_move(&desc);
2549         move_native_irq(irq);
2550         ack_APIC_irq();
2551 }
2552
2553 atomic_t irq_mis_count;
2554
2555 static void ack_apic_level(unsigned int irq)
2556 {
2557         struct irq_desc *desc = irq_to_desc(irq);
2558
2559 #ifdef CONFIG_X86_32
2560         unsigned long v;
2561         int i;
2562 #endif
2563         struct irq_cfg *cfg;
2564         int do_unmask_irq = 0;
2565
2566         irq_complete_move(&desc);
2567 #ifdef CONFIG_GENERIC_PENDING_IRQ
2568         /* If we are moving the irq we need to mask it */
2569         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2570                 do_unmask_irq = 1;
2571                 mask_IO_APIC_irq_desc(desc);
2572         }
2573 #endif
2574
2575 #ifdef CONFIG_X86_32
2576         /*
2577         * It appears there is an erratum which affects at least version 0x11
2578         * of I/O APIC (that's the 82093AA and cores integrated into various
2579         * chipsets).  Under certain conditions a level-triggered interrupt is
2580         * erroneously delivered as edge-triggered one but the respective IRR
2581         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2582         * message but it will never arrive and further interrupts are blocked
2583         * from the source.  The exact reason is so far unknown, but the
2584         * phenomenon was observed when two consecutive interrupt requests
2585         * from a given source get delivered to the same CPU and the source is
2586         * temporarily disabled in between.
2587         *
2588         * A workaround is to simulate an EOI message manually.  We achieve it
2589         * by setting the trigger mode to edge and then to level when the edge
2590         * trigger mode gets detected in the TMR of a local APIC for a
2591         * level-triggered interrupt.  We mask the source for the time of the
2592         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2593         * The idea is from Manfred Spraul.  --macro
2594         */
2595         cfg = desc->chip_data;
2596         i = cfg->vector;
2597
2598         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2599 #endif
2600
2601         /*
2602          * We must acknowledge the irq before we move it or the acknowledge will
2603          * not propagate properly.
2604          */
2605         ack_APIC_irq();
2606
2607         /* Now we can move and renable the irq */
2608         if (unlikely(do_unmask_irq)) {
2609                 /* Only migrate the irq if the ack has been received.
2610                  *
2611                  * On rare occasions the broadcast level triggered ack gets
2612                  * delayed going to ioapics, and if we reprogram the
2613                  * vector while Remote IRR is still set the irq will never
2614                  * fire again.
2615                  *
2616                  * To prevent this scenario we read the Remote IRR bit
2617                  * of the ioapic.  This has two effects.
2618                  * - On any sane system the read of the ioapic will
2619                  *   flush writes (and acks) going to the ioapic from
2620                  *   this cpu.
2621                  * - We get to see if the ACK has actually been delivered.
2622                  *
2623                  * Based on failed experiments of reprogramming the
2624                  * ioapic entry from outside of irq context starting
2625                  * with masking the ioapic entry and then polling until
2626                  * Remote IRR was clear before reprogramming the
2627                  * ioapic I don't trust the Remote IRR bit to be
2628                  * completey accurate.
2629                  *
2630                  * However there appears to be no other way to plug
2631                  * this race, so if the Remote IRR bit is not
2632                  * accurate and is causing problems then it is a hardware bug
2633                  * and you can go talk to the chipset vendor about it.
2634                  */
2635                 cfg = desc->chip_data;
2636                 if (!io_apic_level_ack_pending(cfg))
2637                         move_masked_irq(irq);
2638                 unmask_IO_APIC_irq_desc(desc);
2639         }
2640
2641 #ifdef CONFIG_X86_32
2642         if (!(v & (1 << (i & 0x1f)))) {
2643                 atomic_inc(&irq_mis_count);
2644                 spin_lock(&ioapic_lock);
2645                 __mask_and_edge_IO_APIC_irq(cfg);
2646                 __unmask_and_level_IO_APIC_irq(cfg);
2647                 spin_unlock(&ioapic_lock);
2648         }
2649 #endif
2650 }
2651
2652 static struct irq_chip ioapic_chip __read_mostly = {
2653         .name           = "IO-APIC",
2654         .startup        = startup_ioapic_irq,
2655         .mask           = mask_IO_APIC_irq,
2656         .unmask         = unmask_IO_APIC_irq,
2657         .ack            = ack_apic_edge,
2658         .eoi            = ack_apic_level,
2659 #ifdef CONFIG_SMP
2660         .set_affinity   = set_ioapic_affinity_irq,
2661 #endif
2662         .retrigger      = ioapic_retrigger_irq,
2663 };
2664
2665 static struct irq_chip ir_ioapic_chip __read_mostly = {
2666         .name           = "IR-IO-APIC",
2667         .startup        = startup_ioapic_irq,
2668         .mask           = mask_IO_APIC_irq,
2669         .unmask         = unmask_IO_APIC_irq,
2670 #ifdef CONFIG_INTR_REMAP
2671         .ack            = ack_x2apic_edge,
2672         .eoi            = ack_x2apic_level,
2673 #ifdef CONFIG_SMP
2674         .set_affinity   = set_ir_ioapic_affinity_irq,
2675 #endif
2676 #endif
2677         .retrigger      = ioapic_retrigger_irq,
2678 };
2679
2680 static inline void init_IO_APIC_traps(void)
2681 {
2682         int irq;
2683         struct irq_desc *desc;
2684         struct irq_cfg *cfg;
2685
2686         /*
2687          * NOTE! The local APIC isn't very good at handling
2688          * multiple interrupts at the same interrupt level.
2689          * As the interrupt level is determined by taking the
2690          * vector number and shifting that right by 4, we
2691          * want to spread these out a bit so that they don't
2692          * all fall in the same interrupt level.
2693          *
2694          * Also, we've got to be careful not to trash gate
2695          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2696          */
2697         for_each_irq_desc(irq, desc) {
2698                 cfg = desc->chip_data;
2699                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2700                         /*
2701                          * Hmm.. We don't have an entry for this,
2702                          * so default to an old-fashioned 8259
2703                          * interrupt if we can..
2704                          */
2705                         if (irq < NR_IRQS_LEGACY)
2706                                 make_8259A_irq(irq);
2707                         else
2708                                 /* Strange. Oh, well.. */
2709                                 desc->chip = &no_irq_chip;
2710                 }
2711         }
2712 }
2713
2714 /*
2715  * The local APIC irq-chip implementation:
2716  */
2717
2718 static void mask_lapic_irq(unsigned int irq)
2719 {
2720         unsigned long v;
2721
2722         v = apic_read(APIC_LVT0);
2723         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2724 }
2725
2726 static void unmask_lapic_irq(unsigned int irq)
2727 {
2728         unsigned long v;
2729
2730         v = apic_read(APIC_LVT0);
2731         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2732 }
2733
2734 static void ack_lapic_irq(unsigned int irq)
2735 {
2736         ack_APIC_irq();
2737 }
2738
2739 static struct irq_chip lapic_chip __read_mostly = {
2740         .name           = "local-APIC",
2741         .mask           = mask_lapic_irq,
2742         .unmask         = unmask_lapic_irq,
2743         .ack            = ack_lapic_irq,
2744 };
2745
2746 static void lapic_register_intr(int irq, struct irq_desc *desc)
2747 {
2748         desc->status &= ~IRQ_LEVEL;
2749         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2750                                       "edge");
2751 }
2752
2753 static void __init setup_nmi(void)
2754 {
2755         /*
2756          * Dirty trick to enable the NMI watchdog ...
2757          * We put the 8259A master into AEOI mode and
2758          * unmask on all local APICs LVT0 as NMI.
2759          *
2760          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2761          * is from Maciej W. Rozycki - so we do not have to EOI from
2762          * the NMI handler or the timer interrupt.
2763          */
2764         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2765
2766         enable_NMI_through_LVT0();
2767
2768         apic_printk(APIC_VERBOSE, " done.\n");
2769 }
2770
2771 /*
2772  * This looks a bit hackish but it's about the only one way of sending
2773  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2774  * not support the ExtINT mode, unfortunately.  We need to send these
2775  * cycles as some i82489DX-based boards have glue logic that keeps the
2776  * 8259A interrupt line asserted until INTA.  --macro
2777  */
2778 static inline void __init unlock_ExtINT_logic(void)
2779 {
2780         int apic, pin, i;
2781         struct IO_APIC_route_entry entry0, entry1;
2782         unsigned char save_control, save_freq_select;
2783
2784         pin  = find_isa_irq_pin(8, mp_INT);
2785         if (pin == -1) {
2786                 WARN_ON_ONCE(1);
2787                 return;
2788         }
2789         apic = find_isa_irq_apic(8, mp_INT);
2790         if (apic == -1) {
2791                 WARN_ON_ONCE(1);
2792                 return;
2793         }
2794
2795         entry0 = ioapic_read_entry(apic, pin);
2796         clear_IO_APIC_pin(apic, pin);
2797
2798         memset(&entry1, 0, sizeof(entry1));
2799
2800         entry1.dest_mode = 0;                   /* physical delivery */
2801         entry1.mask = 0;                        /* unmask IRQ now */
2802         entry1.dest = hard_smp_processor_id();
2803         entry1.delivery_mode = dest_ExtINT;
2804         entry1.polarity = entry0.polarity;
2805         entry1.trigger = 0;
2806         entry1.vector = 0;
2807
2808         ioapic_write_entry(apic, pin, entry1);
2809
2810         save_control = CMOS_READ(RTC_CONTROL);
2811         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2812         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2813                    RTC_FREQ_SELECT);
2814         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2815
2816         i = 100;
2817         while (i-- > 0) {
2818                 mdelay(10);
2819                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2820                         i -= 10;
2821         }
2822
2823         CMOS_WRITE(save_control, RTC_CONTROL);
2824         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2825         clear_IO_APIC_pin(apic, pin);
2826
2827         ioapic_write_entry(apic, pin, entry0);
2828 }
2829
2830 static int disable_timer_pin_1 __initdata;
2831 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2832 static int __init disable_timer_pin_setup(char *arg)
2833 {
2834         disable_timer_pin_1 = 1;
2835         return 0;
2836 }
2837 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2838
2839 int timer_through_8259 __initdata;
2840
2841 /*
2842  * This code may look a bit paranoid, but it's supposed to cooperate with
2843  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2844  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2845  * fanatically on his truly buggy board.
2846  *
2847  * FIXME: really need to revamp this for all platforms.
2848  */
2849 static inline void __init check_timer(void)
2850 {
2851         struct irq_desc *desc = irq_to_desc(0);
2852         struct irq_cfg *cfg = desc->chip_data;
2853         int cpu = boot_cpu_id;
2854         int apic1, pin1, apic2, pin2;
2855         unsigned long flags;
2856         int no_pin1 = 0;
2857
2858         local_irq_save(flags);
2859
2860         /*
2861          * get/set the timer IRQ vector:
2862          */
2863         disable_8259A_irq(0);
2864         assign_irq_vector(0, cfg, apic->target_cpus());
2865
2866         /*
2867          * As IRQ0 is to be enabled in the 8259A, the virtual
2868          * wire has to be disabled in the local APIC.  Also
2869          * timer interrupts need to be acknowledged manually in
2870          * the 8259A for the i82489DX when using the NMI
2871          * watchdog as that APIC treats NMIs as level-triggered.
2872          * The AEOI mode will finish them in the 8259A
2873          * automatically.
2874          */
2875         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2876         init_8259A(1);
2877 #ifdef CONFIG_X86_32
2878         {
2879                 unsigned int ver;
2880
2881                 ver = apic_read(APIC_LVR);
2882                 ver = GET_APIC_VERSION(ver);
2883                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2884         }
2885 #endif
2886
2887         pin1  = find_isa_irq_pin(0, mp_INT);
2888         apic1 = find_isa_irq_apic(0, mp_INT);
2889         pin2  = ioapic_i8259.pin;
2890         apic2 = ioapic_i8259.apic;
2891
2892         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2893                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2894                     cfg->vector, apic1, pin1, apic2, pin2);
2895
2896         /*
2897          * Some BIOS writers are clueless and report the ExtINTA
2898          * I/O APIC input from the cascaded 8259A as the timer
2899          * interrupt input.  So just in case, if only one pin
2900          * was found above, try it both directly and through the
2901          * 8259A.
2902          */
2903         if (pin1 == -1) {
2904                 if (intr_remapping_enabled)
2905                         panic("BIOS bug: timer not connected to IO-APIC");
2906                 pin1 = pin2;
2907                 apic1 = apic2;
2908                 no_pin1 = 1;
2909         } else if (pin2 == -1) {
2910                 pin2 = pin1;
2911                 apic2 = apic1;
2912         }
2913
2914         if (pin1 != -1) {
2915                 /*
2916                  * Ok, does IRQ0 through the IOAPIC work?
2917                  */
2918                 if (no_pin1) {
2919                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2920                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2921                 } else {
2922                         /* for edge trigger, setup_IO_APIC_irq already
2923                          * leave it unmasked.
2924                          * so only need to unmask if it is level-trigger
2925                          * do we really have level trigger timer?
2926                          */
2927                         int idx;
2928                         idx = find_irq_entry(apic1, pin1, mp_INT);
2929                         if (idx != -1 && irq_trigger(idx))
2930                                 unmask_IO_APIC_irq_desc(desc);
2931                 }
2932                 if (timer_irq_works()) {
2933                         if (nmi_watchdog == NMI_IO_APIC) {
2934                                 setup_nmi();
2935                                 enable_8259A_irq(0);
2936                         }
2937                         if (disable_timer_pin_1 > 0)
2938                                 clear_IO_APIC_pin(0, pin1);
2939                         goto out;
2940                 }
2941                 if (intr_remapping_enabled)
2942                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2943                 local_irq_disable();
2944                 clear_IO_APIC_pin(apic1, pin1);
2945                 if (!no_pin1)
2946                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2947                                     "8254 timer not connected to IO-APIC\n");
2948
2949                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2950                             "(IRQ0) through the 8259A ...\n");
2951                 apic_printk(APIC_QUIET, KERN_INFO
2952                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2953                 /*
2954                  * legacy devices should be connected to IO APIC #0
2955                  */
2956                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2957                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2958                 enable_8259A_irq(0);
2959                 if (timer_irq_works()) {
2960                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2961                         timer_through_8259 = 1;
2962                         if (nmi_watchdog == NMI_IO_APIC) {
2963                                 disable_8259A_irq(0);
2964                                 setup_nmi();
2965                                 enable_8259A_irq(0);
2966                         }
2967                         goto out;
2968                 }
2969                 /*
2970                  * Cleanup, just in case ...
2971                  */
2972                 local_irq_disable();
2973                 disable_8259A_irq(0);
2974                 clear_IO_APIC_pin(apic2, pin2);
2975                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2976         }
2977
2978         if (nmi_watchdog == NMI_IO_APIC) {
2979                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2980                             "through the IO-APIC - disabling NMI Watchdog!\n");
2981                 nmi_watchdog = NMI_NONE;
2982         }
2983 #ifdef CONFIG_X86_32
2984         timer_ack = 0;
2985 #endif
2986
2987         apic_printk(APIC_QUIET, KERN_INFO
2988                     "...trying to set up timer as Virtual Wire IRQ...\n");
2989
2990         lapic_register_intr(0, desc);
2991         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2992         enable_8259A_irq(0);
2993
2994         if (timer_irq_works()) {
2995                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2996                 goto out;
2997         }
2998         local_irq_disable();
2999         disable_8259A_irq(0);
3000         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3001         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3002
3003         apic_printk(APIC_QUIET, KERN_INFO
3004                     "...trying to set up timer as ExtINT IRQ...\n");
3005
3006         init_8259A(0);
3007         make_8259A_irq(0);
3008         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3009
3010         unlock_ExtINT_logic();
3011
3012         if (timer_irq_works()) {
3013                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3014                 goto out;
3015         }
3016         local_irq_disable();
3017         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3018         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3019                 "report.  Then try booting with the 'noapic' option.\n");
3020 out:
3021         local_irq_restore(flags);
3022 }
3023
3024 /*
3025  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3026  * to devices.  However there may be an I/O APIC pin available for
3027  * this interrupt regardless.  The pin may be left unconnected, but
3028  * typically it will be reused as an ExtINT cascade interrupt for
3029  * the master 8259A.  In the MPS case such a pin will normally be
3030  * reported as an ExtINT interrupt in the MP table.  With ACPI
3031  * there is no provision for ExtINT interrupts, and in the absence
3032  * of an override it would be treated as an ordinary ISA I/O APIC
3033  * interrupt, that is edge-triggered and unmasked by default.  We
3034  * used to do this, but it caused problems on some systems because
3035  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3036  * the same ExtINT cascade interrupt to drive the local APIC of the
3037  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3038  * the I/O APIC in all cases now.  No actual device should request
3039  * it anyway.  --macro
3040  */
3041 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3042
3043 void __init setup_IO_APIC(void)
3044 {
3045
3046         /*
3047          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3048          */
3049
3050         io_apic_irqs = ~PIC_IRQS;
3051
3052         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3053         /*
3054          * Set up IO-APIC IRQ routing.
3055          */
3056 #ifdef CONFIG_X86_32
3057         if (!acpi_ioapic)
3058                 setup_ioapic_ids_from_mpc();
3059 #endif
3060         sync_Arb_IDs();
3061         setup_IO_APIC_irqs();
3062         init_IO_APIC_traps();
3063         check_timer();
3064 }
3065
3066 /*
3067  *      Called after all the initialization is done. If we didnt find any
3068  *      APIC bugs then we can allow the modify fast path
3069  */
3070
3071 static int __init io_apic_bug_finalize(void)
3072 {
3073         if (sis_apic_bug == -1)
3074                 sis_apic_bug = 0;
3075         return 0;
3076 }
3077
3078 late_initcall(io_apic_bug_finalize);
3079
3080 struct sysfs_ioapic_data {
3081         struct sys_device dev;
3082         struct IO_APIC_route_entry entry[0];
3083 };
3084 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3085
3086 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3087 {
3088         struct IO_APIC_route_entry *entry;
3089         struct sysfs_ioapic_data *data;
3090         int i;
3091
3092         data = container_of(dev, struct sysfs_ioapic_data, dev);
3093         entry = data->entry;
3094         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3095                 *entry = ioapic_read_entry(dev->id, i);
3096
3097         return 0;
3098 }
3099
3100 static int ioapic_resume(struct sys_device *dev)
3101 {
3102         struct IO_APIC_route_entry *entry;
3103         struct sysfs_ioapic_data *data;
3104         unsigned long flags;
3105         union IO_APIC_reg_00 reg_00;
3106         int i;
3107
3108         data = container_of(dev, struct sysfs_ioapic_data, dev);
3109         entry = data->entry;
3110
3111         spin_lock_irqsave(&ioapic_lock, flags);
3112         reg_00.raw = io_apic_read(dev->id, 0);
3113         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3114                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3115                 io_apic_write(dev->id, 0, reg_00.raw);
3116         }
3117         spin_unlock_irqrestore(&ioapic_lock, flags);
3118         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3119                 ioapic_write_entry(dev->id, i, entry[i]);
3120
3121         return 0;
3122 }
3123
3124 static struct sysdev_class ioapic_sysdev_class = {
3125         .name = "ioapic",
3126         .suspend = ioapic_suspend,
3127         .resume = ioapic_resume,
3128 };
3129
3130 static int __init ioapic_init_sysfs(void)
3131 {
3132         struct sys_device * dev;
3133         int i, size, error;
3134
3135         error = sysdev_class_register(&ioapic_sysdev_class);
3136         if (error)
3137                 return error;
3138
3139         for (i = 0; i < nr_ioapics; i++ ) {
3140                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3141                         * sizeof(struct IO_APIC_route_entry);
3142                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3143                 if (!mp_ioapic_data[i]) {
3144                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3145                         continue;
3146                 }
3147                 dev = &mp_ioapic_data[i]->dev;
3148                 dev->id = i;
3149                 dev->cls = &ioapic_sysdev_class;
3150                 error = sysdev_register(dev);
3151                 if (error) {
3152                         kfree(mp_ioapic_data[i]);
3153                         mp_ioapic_data[i] = NULL;
3154                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3155                         continue;
3156                 }
3157         }
3158
3159         return 0;
3160 }
3161
3162 device_initcall(ioapic_init_sysfs);
3163
3164 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3165 /*
3166  * Dynamic irq allocate and deallocation
3167  */
3168 unsigned int create_irq_nr(unsigned int irq_want)
3169 {
3170         /* Allocate an unused irq */
3171         unsigned int irq;
3172         unsigned int new;
3173         unsigned long flags;
3174         struct irq_cfg *cfg_new = NULL;
3175         int cpu = boot_cpu_id;
3176         struct irq_desc *desc_new = NULL;
3177
3178         irq = 0;
3179         if (irq_want < nr_irqs_gsi)
3180                 irq_want = nr_irqs_gsi;
3181
3182         spin_lock_irqsave(&vector_lock, flags);
3183         for (new = irq_want; new < nr_irqs; new++) {
3184                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3185                 if (!desc_new) {
3186                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3187                         continue;
3188                 }
3189                 cfg_new = desc_new->chip_data;
3190
3191                 if (cfg_new->vector != 0)
3192                         continue;
3193                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3194                         irq = new;
3195                 break;
3196         }
3197         spin_unlock_irqrestore(&vector_lock, flags);
3198
3199         if (irq > 0) {
3200                 dynamic_irq_init(irq);
3201                 /* restore it, in case dynamic_irq_init clear it */
3202                 if (desc_new)
3203                         desc_new->chip_data = cfg_new;
3204         }
3205         return irq;
3206 }
3207
3208 int create_irq(void)
3209 {
3210         unsigned int irq_want;
3211         int irq;
3212
3213         irq_want = nr_irqs_gsi;
3214         irq = create_irq_nr(irq_want);
3215
3216         if (irq == 0)
3217                 irq = -1;
3218
3219         return irq;
3220 }
3221
3222 void destroy_irq(unsigned int irq)
3223 {
3224         unsigned long flags;
3225         struct irq_cfg *cfg;
3226         struct irq_desc *desc;
3227
3228         /* store it, in case dynamic_irq_cleanup clear it */
3229         desc = irq_to_desc(irq);
3230         cfg = desc->chip_data;
3231         dynamic_irq_cleanup(irq);
3232         /* connect back irq_cfg */
3233         if (desc)
3234                 desc->chip_data = cfg;
3235
3236         free_irte(irq);
3237         spin_lock_irqsave(&vector_lock, flags);
3238         __clear_irq_vector(irq, cfg);
3239         spin_unlock_irqrestore(&vector_lock, flags);
3240 }
3241
3242 /*
3243  * MSI message composition
3244  */
3245 #ifdef CONFIG_PCI_MSI
3246 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3247 {
3248         struct irq_cfg *cfg;
3249         int err;
3250         unsigned dest;
3251
3252         if (disable_apic)
3253                 return -ENXIO;
3254
3255         cfg = irq_cfg(irq);
3256         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3257         if (err)
3258                 return err;
3259
3260         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3261
3262         if (irq_remapped(irq)) {
3263                 struct irte irte;
3264                 int ir_index;
3265                 u16 sub_handle;
3266
3267                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3268                 BUG_ON(ir_index == -1);
3269
3270                 memset (&irte, 0, sizeof(irte));
3271
3272                 irte.present = 1;
3273                 irte.dst_mode = apic->irq_dest_mode;
3274                 irte.trigger_mode = 0; /* edge */
3275                 irte.dlvry_mode = apic->irq_delivery_mode;
3276                 irte.vector = cfg->vector;
3277                 irte.dest_id = IRTE_DEST(dest);
3278
3279                 modify_irte(irq, &irte);
3280
3281                 msg->address_hi = MSI_ADDR_BASE_HI;
3282                 msg->data = sub_handle;
3283                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3284                                   MSI_ADDR_IR_SHV |
3285                                   MSI_ADDR_IR_INDEX1(ir_index) |
3286                                   MSI_ADDR_IR_INDEX2(ir_index);
3287         } else {
3288                 if (x2apic_enabled())
3289                         msg->address_hi = MSI_ADDR_BASE_HI |
3290                                           MSI_ADDR_EXT_DEST_ID(dest);
3291                 else
3292                         msg->address_hi = MSI_ADDR_BASE_HI;
3293
3294                 msg->address_lo =
3295                         MSI_ADDR_BASE_LO |
3296                         ((apic->irq_dest_mode == 0) ?
3297                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3298                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3299                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3300                                 MSI_ADDR_REDIRECTION_CPU:
3301                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3302                         MSI_ADDR_DEST_ID(dest);
3303
3304                 msg->data =
3305                         MSI_DATA_TRIGGER_EDGE |
3306                         MSI_DATA_LEVEL_ASSERT |
3307                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3308                                 MSI_DATA_DELIVERY_FIXED:
3309                                 MSI_DATA_DELIVERY_LOWPRI) |
3310                         MSI_DATA_VECTOR(cfg->vector);
3311         }
3312         return err;
3313 }
3314
3315 #ifdef CONFIG_SMP
3316 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3317 {
3318         struct irq_desc *desc = irq_to_desc(irq);
3319         struct irq_cfg *cfg;
3320         struct msi_msg msg;
3321         unsigned int dest;
3322
3323         dest = set_desc_affinity(desc, mask);
3324         if (dest == BAD_APICID)
3325                 return;
3326
3327         cfg = desc->chip_data;
3328
3329         read_msi_msg_desc(desc, &msg);
3330
3331         msg.data &= ~MSI_DATA_VECTOR_MASK;
3332         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3333         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3334         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3335
3336         write_msi_msg_desc(desc, &msg);
3337 }
3338 #ifdef CONFIG_INTR_REMAP
3339 /*
3340  * Migrate the MSI irq to another cpumask. This migration is
3341  * done in the process context using interrupt-remapping hardware.
3342  */
3343 static void
3344 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3345 {
3346         struct irq_desc *desc = irq_to_desc(irq);
3347         struct irq_cfg *cfg = desc->chip_data;
3348         unsigned int dest;
3349         struct irte irte;
3350
3351         if (get_irte(irq, &irte))
3352                 return;
3353
3354         dest = set_desc_affinity(desc, mask);
3355         if (dest == BAD_APICID)
3356                 return;
3357
3358         irte.vector = cfg->vector;
3359         irte.dest_id = IRTE_DEST(dest);
3360
3361         /*
3362          * atomically update the IRTE with the new destination and vector.
3363          */
3364         modify_irte(irq, &irte);
3365
3366         /*
3367          * After this point, all the interrupts will start arriving
3368          * at the new destination. So, time to cleanup the previous
3369          * vector allocation.
3370          */
3371         if (cfg->move_in_progress)
3372                 send_cleanup_vector(cfg);
3373 }
3374
3375 #endif
3376 #endif /* CONFIG_SMP */
3377
3378 /*
3379  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3380  * which implement the MSI or MSI-X Capability Structure.
3381  */
3382 static struct irq_chip msi_chip = {
3383         .name           = "PCI-MSI",
3384         .unmask         = unmask_msi_irq,
3385         .mask           = mask_msi_irq,
3386         .ack            = ack_apic_edge,
3387 #ifdef CONFIG_SMP
3388         .set_affinity   = set_msi_irq_affinity,
3389 #endif
3390         .retrigger      = ioapic_retrigger_irq,
3391 };
3392
3393 static struct irq_chip msi_ir_chip = {
3394         .name           = "IR-PCI-MSI",
3395         .unmask         = unmask_msi_irq,
3396         .mask           = mask_msi_irq,
3397 #ifdef CONFIG_INTR_REMAP
3398         .ack            = ack_x2apic_edge,
3399 #ifdef CONFIG_SMP
3400         .set_affinity   = ir_set_msi_irq_affinity,
3401 #endif
3402 #endif
3403         .retrigger      = ioapic_retrigger_irq,
3404 };
3405
3406 /*
3407  * Map the PCI dev to the corresponding remapping hardware unit
3408  * and allocate 'nvec' consecutive interrupt-remapping table entries
3409  * in it.
3410  */
3411 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3412 {
3413         struct intel_iommu *iommu;
3414         int index;
3415
3416         iommu = map_dev_to_ir(dev);
3417         if (!iommu) {
3418                 printk(KERN_ERR
3419                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3420                 return -ENOENT;
3421         }
3422
3423         index = alloc_irte(iommu, irq, nvec);
3424         if (index < 0) {
3425                 printk(KERN_ERR
3426                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3427                        pci_name(dev));
3428                 return -ENOSPC;
3429         }
3430         return index;
3431 }
3432
3433 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3434 {
3435         int ret;
3436         struct msi_msg msg;
3437
3438         ret = msi_compose_msg(dev, irq, &msg);
3439         if (ret < 0)
3440                 return ret;
3441
3442         set_irq_msi(irq, msidesc);
3443         write_msi_msg(irq, &msg);
3444
3445         if (irq_remapped(irq)) {
3446                 struct irq_desc *desc = irq_to_desc(irq);
3447                 /*
3448                  * irq migration in process context
3449                  */
3450                 desc->status |= IRQ_MOVE_PCNTXT;
3451                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3452         } else
3453                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3454
3455         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3456
3457         return 0;
3458 }
3459
3460 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3461 {
3462         unsigned int irq;
3463         int ret, sub_handle;
3464         struct msi_desc *msidesc;
3465         unsigned int irq_want;
3466         struct intel_iommu *iommu = NULL;
3467         int index = 0;
3468
3469         irq_want = nr_irqs_gsi;
3470         sub_handle = 0;
3471         list_for_each_entry(msidesc, &dev->msi_list, list) {
3472                 irq = create_irq_nr(irq_want);
3473                 if (irq == 0)
3474                         return -1;
3475                 irq_want = irq + 1;
3476                 if (!intr_remapping_enabled)
3477                         goto no_ir;
3478
3479                 if (!sub_handle) {
3480                         /*
3481                          * allocate the consecutive block of IRTE's
3482                          * for 'nvec'
3483                          */
3484                         index = msi_alloc_irte(dev, irq, nvec);
3485                         if (index < 0) {
3486                                 ret = index;
3487                                 goto error;
3488                         }
3489                 } else {
3490                         iommu = map_dev_to_ir(dev);
3491                         if (!iommu) {
3492                                 ret = -ENOENT;
3493                                 goto error;
3494                         }
3495                         /*
3496                          * setup the mapping between the irq and the IRTE
3497                          * base index, the sub_handle pointing to the
3498                          * appropriate interrupt remap table entry.
3499                          */
3500                         set_irte_irq(irq, iommu, index, sub_handle);
3501                 }
3502 no_ir:
3503                 ret = setup_msi_irq(dev, msidesc, irq);
3504                 if (ret < 0)
3505                         goto error;
3506                 sub_handle++;
3507         }
3508         return 0;
3509
3510 error:
3511         destroy_irq(irq);
3512         return ret;
3513 }
3514
3515 void arch_teardown_msi_irq(unsigned int irq)
3516 {
3517         destroy_irq(irq);
3518 }
3519
3520 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3521 #ifdef CONFIG_SMP
3522 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3523 {
3524         struct irq_desc *desc = irq_to_desc(irq);
3525         struct irq_cfg *cfg;
3526         struct msi_msg msg;
3527         unsigned int dest;
3528
3529         dest = set_desc_affinity(desc, mask);
3530         if (dest == BAD_APICID)
3531                 return;
3532
3533         cfg = desc->chip_data;
3534
3535         dmar_msi_read(irq, &msg);
3536
3537         msg.data &= ~MSI_DATA_VECTOR_MASK;
3538         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3539         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3540         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3541
3542         dmar_msi_write(irq, &msg);
3543 }
3544
3545 #endif /* CONFIG_SMP */
3546
3547 struct irq_chip dmar_msi_type = {
3548         .name = "DMAR_MSI",
3549         .unmask = dmar_msi_unmask,
3550         .mask = dmar_msi_mask,
3551         .ack = ack_apic_edge,
3552 #ifdef CONFIG_SMP
3553         .set_affinity = dmar_msi_set_affinity,
3554 #endif
3555         .retrigger = ioapic_retrigger_irq,
3556 };
3557
3558 int arch_setup_dmar_msi(unsigned int irq)
3559 {
3560         int ret;
3561         struct msi_msg msg;
3562
3563         ret = msi_compose_msg(NULL, irq, &msg);
3564         if (ret < 0)
3565                 return ret;
3566         dmar_msi_write(irq, &msg);
3567         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3568                 "edge");
3569         return 0;
3570 }
3571 #endif
3572
3573 #ifdef CONFIG_HPET_TIMER
3574
3575 #ifdef CONFIG_SMP
3576 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3577 {
3578         struct irq_desc *desc = irq_to_desc(irq);
3579         struct irq_cfg *cfg;
3580         struct msi_msg msg;
3581         unsigned int dest;
3582
3583         dest = set_desc_affinity(desc, mask);
3584         if (dest == BAD_APICID)
3585                 return;
3586
3587         cfg = desc->chip_data;
3588
3589         hpet_msi_read(irq, &msg);
3590
3591         msg.data &= ~MSI_DATA_VECTOR_MASK;
3592         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3593         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3594         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3595
3596         hpet_msi_write(irq, &msg);
3597 }
3598
3599 #endif /* CONFIG_SMP */
3600
3601 static struct irq_chip hpet_msi_type = {
3602         .name = "HPET_MSI",
3603         .unmask = hpet_msi_unmask,
3604         .mask = hpet_msi_mask,
3605         .ack = ack_apic_edge,
3606 #ifdef CONFIG_SMP
3607         .set_affinity = hpet_msi_set_affinity,
3608 #endif
3609         .retrigger = ioapic_retrigger_irq,
3610 };
3611
3612 int arch_setup_hpet_msi(unsigned int irq)
3613 {
3614         int ret;
3615         struct msi_msg msg;
3616
3617         ret = msi_compose_msg(NULL, irq, &msg);
3618         if (ret < 0)
3619                 return ret;
3620
3621         hpet_msi_write(irq, &msg);
3622         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3623                 "edge");
3624
3625         return 0;
3626 }
3627 #endif
3628
3629 #endif /* CONFIG_PCI_MSI */
3630 /*
3631  * Hypertransport interrupt support
3632  */
3633 #ifdef CONFIG_HT_IRQ
3634
3635 #ifdef CONFIG_SMP
3636
3637 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3638 {
3639         struct ht_irq_msg msg;
3640         fetch_ht_irq_msg(irq, &msg);
3641
3642         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3643         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3644
3645         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3646         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3647
3648         write_ht_irq_msg(irq, &msg);
3649 }
3650
3651 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3652 {
3653         struct irq_desc *desc = irq_to_desc(irq);
3654         struct irq_cfg *cfg;
3655         unsigned int dest;
3656
3657         dest = set_desc_affinity(desc, mask);
3658         if (dest == BAD_APICID)
3659                 return;
3660
3661         cfg = desc->chip_data;
3662
3663         target_ht_irq(irq, dest, cfg->vector);
3664 }
3665
3666 #endif
3667
3668 static struct irq_chip ht_irq_chip = {
3669         .name           = "PCI-HT",
3670         .mask           = mask_ht_irq,
3671         .unmask         = unmask_ht_irq,
3672         .ack            = ack_apic_edge,
3673 #ifdef CONFIG_SMP
3674         .set_affinity   = set_ht_irq_affinity,
3675 #endif
3676         .retrigger      = ioapic_retrigger_irq,
3677 };
3678
3679 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3680 {
3681         struct irq_cfg *cfg;
3682         int err;
3683
3684         if (disable_apic)
3685                 return -ENXIO;
3686
3687         cfg = irq_cfg(irq);
3688         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3689         if (!err) {
3690                 struct ht_irq_msg msg;
3691                 unsigned dest;
3692
3693                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3694                                                     apic->target_cpus());
3695
3696                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3697
3698                 msg.address_lo =
3699                         HT_IRQ_LOW_BASE |
3700                         HT_IRQ_LOW_DEST_ID(dest) |
3701                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3702                         ((apic->irq_dest_mode == 0) ?
3703                                 HT_IRQ_LOW_DM_PHYSICAL :
3704                                 HT_IRQ_LOW_DM_LOGICAL) |
3705                         HT_IRQ_LOW_RQEOI_EDGE |
3706                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3707                                 HT_IRQ_LOW_MT_FIXED :
3708                                 HT_IRQ_LOW_MT_ARBITRATED) |
3709                         HT_IRQ_LOW_IRQ_MASKED;
3710
3711                 write_ht_irq_msg(irq, &msg);
3712
3713                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3714                                               handle_edge_irq, "edge");
3715
3716                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3717         }
3718         return err;
3719 }
3720 #endif /* CONFIG_HT_IRQ */
3721
3722 #ifdef CONFIG_X86_UV
3723 /*
3724  * Re-target the irq to the specified CPU and enable the specified MMR located
3725  * on the specified blade to allow the sending of MSIs to the specified CPU.
3726  */
3727 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3728                        unsigned long mmr_offset)
3729 {
3730         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3731         struct irq_cfg *cfg;
3732         int mmr_pnode;
3733         unsigned long mmr_value;
3734         struct uv_IO_APIC_route_entry *entry;
3735         unsigned long flags;
3736         int err;
3737
3738         cfg = irq_cfg(irq);
3739
3740         err = assign_irq_vector(irq, cfg, eligible_cpu);
3741         if (err != 0)
3742                 return err;
3743
3744         spin_lock_irqsave(&vector_lock, flags);
3745         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3746                                       irq_name);
3747         spin_unlock_irqrestore(&vector_lock, flags);
3748
3749         mmr_value = 0;
3750         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3751         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3752
3753         entry->vector = cfg->vector;
3754         entry->delivery_mode = apic->irq_delivery_mode;
3755         entry->dest_mode = apic->irq_dest_mode;
3756         entry->polarity = 0;
3757         entry->trigger = 0;
3758         entry->mask = 0;
3759         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3760
3761         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3762         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3763
3764         return irq;
3765 }
3766
3767 /*
3768  * Disable the specified MMR located on the specified blade so that MSIs are
3769  * longer allowed to be sent.
3770  */
3771 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3772 {
3773         unsigned long mmr_value;
3774         struct uv_IO_APIC_route_entry *entry;
3775         int mmr_pnode;
3776
3777         mmr_value = 0;
3778         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3779         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3780
3781         entry->mask = 1;
3782
3783         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3784         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3785 }
3786 #endif /* CONFIG_X86_64 */
3787
3788 int __init io_apic_get_redir_entries (int ioapic)
3789 {
3790         union IO_APIC_reg_01    reg_01;
3791         unsigned long flags;
3792
3793         spin_lock_irqsave(&ioapic_lock, flags);
3794         reg_01.raw = io_apic_read(ioapic, 1);
3795         spin_unlock_irqrestore(&ioapic_lock, flags);
3796
3797         return reg_01.bits.entries;
3798 }
3799
3800 void __init probe_nr_irqs_gsi(void)
3801 {
3802         int nr = 0;
3803
3804         nr = acpi_probe_gsi();
3805         if (nr > nr_irqs_gsi) {
3806                 nr_irqs_gsi = nr;
3807         } else {
3808                 /* for acpi=off or acpi is not compiled in */
3809                 int idx;
3810
3811                 nr = 0;
3812                 for (idx = 0; idx < nr_ioapics; idx++)
3813                         nr += io_apic_get_redir_entries(idx) + 1;
3814
3815                 if (nr > nr_irqs_gsi)
3816                         nr_irqs_gsi = nr;
3817         }
3818
3819         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3820 }
3821
3822 #ifdef CONFIG_SPARSE_IRQ
3823 int __init arch_probe_nr_irqs(void)
3824 {
3825         int nr;
3826
3827         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3828                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3829
3830         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3831 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3832         /*
3833          * for MSI and HT dyn irq
3834          */
3835         nr += nr_irqs_gsi * 16;
3836 #endif
3837         if (nr < nr_irqs)
3838                 nr_irqs = nr;
3839
3840         return 0;
3841 }
3842 #endif
3843
3844 /* --------------------------------------------------------------------------
3845                           ACPI-based IOAPIC Configuration
3846    -------------------------------------------------------------------------- */
3847
3848 #ifdef CONFIG_ACPI
3849
3850 #ifdef CONFIG_X86_32
3851 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3852 {
3853         union IO_APIC_reg_00 reg_00;
3854         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3855         physid_mask_t tmp;
3856         unsigned long flags;
3857         int i = 0;
3858
3859         /*
3860          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3861          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3862          * supports up to 16 on one shared APIC bus.
3863          *
3864          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3865          *      advantage of new APIC bus architecture.
3866          */
3867
3868         if (physids_empty(apic_id_map))
3869                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3870
3871         spin_lock_irqsave(&ioapic_lock, flags);
3872         reg_00.raw = io_apic_read(ioapic, 0);
3873         spin_unlock_irqrestore(&ioapic_lock, flags);
3874
3875         if (apic_id >= get_physical_broadcast()) {
3876                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3877                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3878                 apic_id = reg_00.bits.ID;
3879         }
3880
3881         /*
3882          * Every APIC in a system must have a unique ID or we get lots of nice
3883          * 'stuck on smp_invalidate_needed IPI wait' messages.
3884          */
3885         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3886
3887                 for (i = 0; i < get_physical_broadcast(); i++) {
3888                         if (!apic->check_apicid_used(apic_id_map, i))
3889                                 break;
3890                 }
3891
3892                 if (i == get_physical_broadcast())
3893                         panic("Max apic_id exceeded!\n");
3894
3895                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3896                         "trying %d\n", ioapic, apic_id, i);
3897
3898                 apic_id = i;
3899         }
3900
3901         tmp = apic->apicid_to_cpu_present(apic_id);
3902         physids_or(apic_id_map, apic_id_map, tmp);
3903
3904         if (reg_00.bits.ID != apic_id) {
3905                 reg_00.bits.ID = apic_id;
3906
3907                 spin_lock_irqsave(&ioapic_lock, flags);
3908                 io_apic_write(ioapic, 0, reg_00.raw);
3909                 reg_00.raw = io_apic_read(ioapic, 0);
3910                 spin_unlock_irqrestore(&ioapic_lock, flags);
3911
3912                 /* Sanity check */
3913                 if (reg_00.bits.ID != apic_id) {
3914                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3915                         return -1;
3916                 }
3917         }
3918
3919         apic_printk(APIC_VERBOSE, KERN_INFO
3920                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3921
3922         return apic_id;
3923 }
3924
3925 int __init io_apic_get_version(int ioapic)
3926 {
3927         union IO_APIC_reg_01    reg_01;
3928         unsigned long flags;
3929
3930         spin_lock_irqsave(&ioapic_lock, flags);
3931         reg_01.raw = io_apic_read(ioapic, 1);
3932         spin_unlock_irqrestore(&ioapic_lock, flags);
3933
3934         return reg_01.bits.version;
3935 }
3936 #endif
3937
3938 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3939 {
3940         struct irq_desc *desc;
3941         struct irq_cfg *cfg;
3942         int cpu = boot_cpu_id;
3943
3944         if (!IO_APIC_IRQ(irq)) {
3945                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3946                         ioapic);
3947                 return -EINVAL;
3948         }
3949
3950         desc = irq_to_desc_alloc_cpu(irq, cpu);
3951         if (!desc) {
3952                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3953                 return 0;
3954         }
3955
3956         /*
3957          * IRQs < 16 are already in the irq_2_pin[] map
3958          */
3959         if (irq >= NR_IRQS_LEGACY) {
3960                 cfg = desc->chip_data;
3961                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3962         }
3963
3964         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3965
3966         return 0;
3967 }
3968
3969
3970 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3971 {
3972         int i;
3973
3974         if (skip_ioapic_setup)
3975                 return -1;
3976
3977         for (i = 0; i < mp_irq_entries; i++)
3978                 if (mp_irqs[i].irqtype == mp_INT &&
3979                     mp_irqs[i].srcbusirq == bus_irq)
3980                         break;
3981         if (i >= mp_irq_entries)
3982                 return -1;
3983
3984         *trigger = irq_trigger(i);
3985         *polarity = irq_polarity(i);
3986         return 0;
3987 }
3988
3989 #endif /* CONFIG_ACPI */
3990
3991 /*
3992  * This function currently is only a helper for the i386 smp boot process where
3993  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3994  * so mask in all cases should simply be apic->target_cpus()
3995  */
3996 #ifdef CONFIG_SMP
3997 void __init setup_ioapic_dest(void)
3998 {
3999         int pin, ioapic, irq, irq_entry;
4000         struct irq_desc *desc;
4001         struct irq_cfg *cfg;
4002         const struct cpumask *mask;
4003
4004         if (skip_ioapic_setup == 1)
4005                 return;
4006
4007         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4008                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4009                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4010                         if (irq_entry == -1)
4011                                 continue;
4012                         irq = pin_2_irq(irq_entry, ioapic, pin);
4013
4014                         /* setup_IO_APIC_irqs could fail to get vector for some device
4015                          * when you have too many devices, because at that time only boot
4016                          * cpu is online.
4017                          */
4018                         desc = irq_to_desc(irq);
4019                         cfg = desc->chip_data;
4020                         if (!cfg->vector) {
4021                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4022                                                   irq_trigger(irq_entry),
4023                                                   irq_polarity(irq_entry));
4024                                 continue;
4025
4026                         }
4027
4028                         /*
4029                          * Honour affinities which have been set in early boot
4030                          */
4031                         if (desc->status &
4032                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4033                                 mask = desc->affinity;
4034                         else
4035                                 mask = apic->target_cpus();
4036
4037                         if (intr_remapping_enabled)
4038                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4039                         else
4040                                 set_ioapic_affinity_irq_desc(desc, mask);
4041                 }
4042
4043         }
4044 }
4045 #endif
4046
4047 #define IOAPIC_RESOURCE_NAME_SIZE 11
4048
4049 static struct resource *ioapic_resources;
4050
4051 static struct resource * __init ioapic_setup_resources(void)
4052 {
4053         unsigned long n;
4054         struct resource *res;
4055         char *mem;
4056         int i;
4057
4058         if (nr_ioapics <= 0)
4059                 return NULL;
4060
4061         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4062         n *= nr_ioapics;
4063
4064         mem = alloc_bootmem(n);
4065         res = (void *)mem;
4066
4067         if (mem != NULL) {
4068                 mem += sizeof(struct resource) * nr_ioapics;
4069
4070                 for (i = 0; i < nr_ioapics; i++) {
4071                         res[i].name = mem;
4072                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4073                         sprintf(mem,  "IOAPIC %u", i);
4074                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4075                 }
4076         }
4077
4078         ioapic_resources = res;
4079
4080         return res;
4081 }
4082
4083 void __init ioapic_init_mappings(void)
4084 {
4085         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4086         struct resource *ioapic_res;
4087         int i;
4088
4089         ioapic_res = ioapic_setup_resources();
4090         for (i = 0; i < nr_ioapics; i++) {
4091                 if (smp_found_config) {
4092                         ioapic_phys = mp_ioapics[i].apicaddr;
4093 #ifdef CONFIG_X86_32
4094                         if (!ioapic_phys) {
4095                                 printk(KERN_ERR
4096                                        "WARNING: bogus zero IO-APIC "
4097                                        "address found in MPTABLE, "
4098                                        "disabling IO/APIC support!\n");
4099                                 smp_found_config = 0;
4100                                 skip_ioapic_setup = 1;
4101                                 goto fake_ioapic_page;
4102                         }
4103 #endif
4104                 } else {
4105 #ifdef CONFIG_X86_32
4106 fake_ioapic_page:
4107 #endif
4108                         ioapic_phys = (unsigned long)
4109                                 alloc_bootmem_pages(PAGE_SIZE);
4110                         ioapic_phys = __pa(ioapic_phys);
4111                 }
4112                 set_fixmap_nocache(idx, ioapic_phys);
4113                 apic_printk(APIC_VERBOSE,
4114                             "mapped IOAPIC to %08lx (%08lx)\n",
4115                             __fix_to_virt(idx), ioapic_phys);
4116                 idx++;
4117
4118                 if (ioapic_res != NULL) {
4119                         ioapic_res->start = ioapic_phys;
4120                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4121                         ioapic_res++;
4122                 }
4123         }
4124 }
4125
4126 static int __init ioapic_insert_resources(void)
4127 {
4128         int i;
4129         struct resource *r = ioapic_resources;
4130
4131         if (!r) {
4132                 if (nr_ioapics > 0) {
4133                         printk(KERN_ERR
4134                                 "IO APIC resources couldn't be allocated.\n");
4135                         return -1;
4136                 }
4137                 return 0;
4138         }
4139
4140         for (i = 0; i < nr_ioapics; i++) {
4141                 insert_resource(&iomem_resource, r);
4142                 r++;
4143         }
4144
4145         return 0;
4146 }
4147
4148 /* Insert the IO APIC resources after PCI initialization has occured to handle
4149  * IO APICS that are mapped in on a BAR in PCI space. */
4150 late_initcall(ioapic_insert_resources);