2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug = -1;
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
79 * # of IRQ routing registers
81 int nr_ioapic_registers[MAX_IO_APICS];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99 int skip_ioapic_setup;
101 void arch_disable_smp_support(void)
105 noioapicreroute = -1;
107 skip_ioapic_setup = 1;
110 static int __init parse_noapic(char *str)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
134 struct irq_pin_list *pin;
137 node = cpu_to_node(cpu);
139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
145 struct irq_pin_list *irq_2_pin;
146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
148 unsigned move_cleanup_count;
150 u8 move_in_progress : 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx[] = {
160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
180 int __init arch_early_irq_init(void)
183 struct irq_desc *desc;
188 count = ARRAY_SIZE(irq_cfgx);
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg *irq_cfg(unsigned int irq)
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
208 desc = irq_to_desc(irq);
210 cfg = desc->chip_data;
215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
220 node = cpu_to_node(cpu);
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
229 free_cpumask_var(cfg->domain);
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
245 cfg = desc->chip_data;
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
269 entry = get_one_free_irq_2_pin(cpu);
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
277 old_entry = old_entry->next;
279 entry = get_one_free_irq_2_pin(cpu);
287 /* still use the old one */
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
294 old_entry = old_entry->next;
298 cfg->irq_2_pin = head;
301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
303 struct irq_pin_list *entry, *next;
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
308 entry = old_cfg->irq_2_pin;
315 old_cfg->irq_2_pin = NULL;
318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
322 struct irq_cfg *old_cfg;
324 cfg = get_one_free_irq_cfg(cpu);
329 desc->chip_data = cfg;
331 old_cfg = old_desc->chip_data;
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
338 static void free_irq_cfg(struct irq_cfg *old_cfg)
343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
345 struct irq_cfg *old_cfg, *cfg;
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
363 struct irq_cfg *cfg = desc->chip_data;
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc->affinity, mask))
368 cfg->move_desc_pending = 1;
374 static struct irq_cfg *irq_cfg(unsigned int irq)
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
390 unsigned int unused[3];
392 unsigned int unused2[11];
396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
398 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
399 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(vector, &io_apic->eoi);
408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
410 struct io_apic __iomem *io_apic = io_apic_base(apic);
411 writel(reg, &io_apic->index);
412 return readl(&io_apic->data);
415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
417 struct io_apic __iomem *io_apic = io_apic_base(apic);
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
430 struct io_apic __iomem *io_apic = io_apic_base(apic);
433 writel(reg, &io_apic->index);
434 writel(value, &io_apic->data);
437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
439 struct irq_pin_list *entry;
442 spin_lock_irqsave(&ioapic_lock, flags);
443 entry = cfg->irq_2_pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin*2);
452 /* Is the remote IRR bit set? */
453 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
454 spin_unlock_irqrestore(&ioapic_lock, flags);
461 spin_unlock_irqrestore(&ioapic_lock, flags);
467 struct { u32 w1, w2; };
468 struct IO_APIC_route_entry entry;
471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
473 union entry_union eu;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
477 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
478 spin_unlock_irqrestore(&ioapic_lock, flags);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
491 union entry_union eu;
493 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
494 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
500 spin_lock_irqsave(&ioapic_lock, flags);
501 __ioapic_write_entry(apic, pin, e);
502 spin_unlock_irqrestore(&ioapic_lock, flags);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic, int pin)
513 union entry_union eu = { .entry.mask = 1 };
515 spin_lock_irqsave(&ioapic_lock, flags);
516 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
517 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
518 spin_unlock_irqrestore(&ioapic_lock, flags);
522 static void send_cleanup_vector(struct irq_cfg *cfg)
524 cpumask_var_t cleanup_mask;
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
528 cfg->move_cleanup_count = 0;
529 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
530 cfg->move_cleanup_count++;
531 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
532 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
534 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
535 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
536 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
537 free_cpumask_var(cleanup_mask);
539 cfg->move_in_progress = 0;
542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
545 struct irq_pin_list *entry;
546 u8 vector = cfg->vector;
548 entry = cfg->irq_2_pin;
557 #ifdef CONFIG_INTR_REMAP
559 * With interrupt-remapping, destination information comes
560 * from interrupt-remapping table entry.
562 if (!irq_remapped(irq))
563 io_apic_write(apic, 0x11 + pin*2, dest);
565 io_apic_write(apic, 0x11 + pin*2, dest);
567 reg = io_apic_read(apic, 0x10 + pin*2);
568 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
570 io_apic_modify(apic, 0x10 + pin*2, reg);
578 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
581 * Either sets desc->affinity to a valid value, and returns
582 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
583 * leaves desc->affinity untouched.
586 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
591 if (!cpumask_intersects(mask, cpu_online_mask))
595 cfg = desc->chip_data;
596 if (assign_irq_vector(irq, cfg, mask))
599 cpumask_and(desc->affinity, cfg->domain, mask);
600 set_extra_move_desc(desc, mask);
602 return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
606 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
614 cfg = desc->chip_data;
616 spin_lock_irqsave(&ioapic_lock, flags);
617 dest = set_desc_affinity(desc, mask);
618 if (dest != BAD_APICID) {
619 /* Only the high 8 bits are valid. */
620 dest = SET_APIC_LOGICAL_ID(dest);
621 __target_IO_APIC_irq(irq, dest, cfg);
623 spin_unlock_irqrestore(&ioapic_lock, flags);
627 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
629 struct irq_desc *desc;
631 desc = irq_to_desc(irq);
633 set_ioapic_affinity_irq_desc(desc, mask);
635 #endif /* CONFIG_SMP */
638 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
639 * shared ISA-space IRQs, so we have to support them. We are super
640 * fast in the common case, and fast for shared ISA-space IRQs.
642 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
644 struct irq_pin_list *entry;
646 entry = cfg->irq_2_pin;
648 entry = get_one_free_irq_2_pin(cpu);
650 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
654 cfg->irq_2_pin = entry;
660 while (entry->next) {
661 /* not again, please */
662 if (entry->apic == apic && entry->pin == pin)
668 entry->next = get_one_free_irq_2_pin(cpu);
675 * Reroute an IRQ to a different pin.
677 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
678 int oldapic, int oldpin,
679 int newapic, int newpin)
681 struct irq_pin_list *entry = cfg->irq_2_pin;
685 if (entry->apic == oldapic && entry->pin == oldpin) {
686 entry->apic = newapic;
689 /* every one is different, right? */
695 /* why? call replace before add? */
697 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
700 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
701 int mask_and, int mask_or,
702 void (*final)(struct irq_pin_list *entry))
705 struct irq_pin_list *entry;
707 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
710 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
713 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
719 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
721 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
725 static void io_apic_sync(struct irq_pin_list *entry)
728 * Synchronize the IO-APIC and the CPU by doing
729 * a dummy read from the IO-APIC
731 struct io_apic __iomem *io_apic;
732 io_apic = io_apic_base(entry->apic);
733 readl(&io_apic->data);
736 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
738 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
740 #else /* CONFIG_X86_32 */
741 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
743 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
746 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
748 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
749 IO_APIC_REDIR_MASKED, NULL);
752 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
754 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
755 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
757 #endif /* CONFIG_X86_32 */
759 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
761 struct irq_cfg *cfg = desc->chip_data;
766 spin_lock_irqsave(&ioapic_lock, flags);
767 __mask_IO_APIC_irq(cfg);
768 spin_unlock_irqrestore(&ioapic_lock, flags);
771 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
773 struct irq_cfg *cfg = desc->chip_data;
776 spin_lock_irqsave(&ioapic_lock, flags);
777 __unmask_IO_APIC_irq(cfg);
778 spin_unlock_irqrestore(&ioapic_lock, flags);
781 static void mask_IO_APIC_irq(unsigned int irq)
783 struct irq_desc *desc = irq_to_desc(irq);
785 mask_IO_APIC_irq_desc(desc);
787 static void unmask_IO_APIC_irq(unsigned int irq)
789 struct irq_desc *desc = irq_to_desc(irq);
791 unmask_IO_APIC_irq_desc(desc);
794 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
796 struct IO_APIC_route_entry entry;
798 /* Check delivery_mode to be sure we're not clearing an SMI pin */
799 entry = ioapic_read_entry(apic, pin);
800 if (entry.delivery_mode == dest_SMI)
803 * Disable it in the IO-APIC irq-routing table:
805 ioapic_mask_entry(apic, pin);
808 static void clear_IO_APIC (void)
812 for (apic = 0; apic < nr_ioapics; apic++)
813 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
814 clear_IO_APIC_pin(apic, pin);
819 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
820 * specific CPU-side IRQs.
824 static int pirq_entries[MAX_PIRQS] = {
825 [0 ... MAX_PIRQS - 1] = -1
828 static int __init ioapic_pirq_setup(char *str)
831 int ints[MAX_PIRQS+1];
833 get_options(str, ARRAY_SIZE(ints), ints);
835 apic_printk(APIC_VERBOSE, KERN_INFO
836 "PIRQ redirection, working around broken MP-BIOS.\n");
838 if (ints[0] < MAX_PIRQS)
841 for (i = 0; i < max; i++) {
842 apic_printk(APIC_VERBOSE, KERN_DEBUG
843 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
845 * PIRQs are mapped upside down, usually.
847 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
852 __setup("pirq=", ioapic_pirq_setup);
853 #endif /* CONFIG_X86_32 */
855 #ifdef CONFIG_INTR_REMAP
856 /* I/O APIC RTE contents at the OS boot up */
857 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
860 * Saves and masks all the unmasked IO-APIC RTE's
862 int save_mask_IO_APIC_setup(void)
864 union IO_APIC_reg_01 reg_01;
869 * The number of IO-APIC IRQ registers (== #pins):
871 for (apic = 0; apic < nr_ioapics; apic++) {
872 spin_lock_irqsave(&ioapic_lock, flags);
873 reg_01.raw = io_apic_read(apic, 1);
874 spin_unlock_irqrestore(&ioapic_lock, flags);
875 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
878 for (apic = 0; apic < nr_ioapics; apic++) {
879 early_ioapic_entries[apic] =
880 kzalloc(sizeof(struct IO_APIC_route_entry) *
881 nr_ioapic_registers[apic], GFP_KERNEL);
882 if (!early_ioapic_entries[apic])
886 for (apic = 0; apic < nr_ioapics; apic++)
887 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
888 struct IO_APIC_route_entry entry;
890 entry = early_ioapic_entries[apic][pin] =
891 ioapic_read_entry(apic, pin);
894 ioapic_write_entry(apic, pin, entry);
902 kfree(early_ioapic_entries[apic--]);
903 memset(early_ioapic_entries, 0,
904 ARRAY_SIZE(early_ioapic_entries));
909 void restore_IO_APIC_setup(void)
913 for (apic = 0; apic < nr_ioapics; apic++) {
914 if (!early_ioapic_entries[apic])
916 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
917 ioapic_write_entry(apic, pin,
918 early_ioapic_entries[apic][pin]);
919 kfree(early_ioapic_entries[apic]);
920 early_ioapic_entries[apic] = NULL;
924 void reinit_intr_remapped_IO_APIC(int intr_remapping)
927 * for now plain restore of previous settings.
928 * TBD: In the case of OS enabling interrupt-remapping,
929 * IO-APIC RTE's need to be setup to point to interrupt-remapping
930 * table entries. for now, do a plain restore, and wait for
931 * the setup_IO_APIC_irqs() to do proper initialization.
933 restore_IO_APIC_setup();
938 * Find the IRQ entry number of a certain pin.
940 static int find_irq_entry(int apic, int pin, int type)
944 for (i = 0; i < mp_irq_entries; i++)
945 if (mp_irqs[i].irqtype == type &&
946 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
947 mp_irqs[i].dstapic == MP_APIC_ALL) &&
948 mp_irqs[i].dstirq == pin)
955 * Find the pin to which IRQ[irq] (ISA) is connected
957 static int __init find_isa_irq_pin(int irq, int type)
961 for (i = 0; i < mp_irq_entries; i++) {
962 int lbus = mp_irqs[i].srcbus;
964 if (test_bit(lbus, mp_bus_not_pci) &&
965 (mp_irqs[i].irqtype == type) &&
966 (mp_irqs[i].srcbusirq == irq))
968 return mp_irqs[i].dstirq;
973 static int __init find_isa_irq_apic(int irq, int type)
977 for (i = 0; i < mp_irq_entries; i++) {
978 int lbus = mp_irqs[i].srcbus;
980 if (test_bit(lbus, mp_bus_not_pci) &&
981 (mp_irqs[i].irqtype == type) &&
982 (mp_irqs[i].srcbusirq == irq))
985 if (i < mp_irq_entries) {
987 for(apic = 0; apic < nr_ioapics; apic++) {
988 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
997 * Find a specific PCI IRQ entry.
998 * Not an __init, possibly needed by modules
1000 static int pin_2_irq(int idx, int apic, int pin);
1002 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1004 int apic, i, best_guess = -1;
1006 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1008 if (test_bit(bus, mp_bus_not_pci)) {
1009 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1012 for (i = 0; i < mp_irq_entries; i++) {
1013 int lbus = mp_irqs[i].srcbus;
1015 for (apic = 0; apic < nr_ioapics; apic++)
1016 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1017 mp_irqs[i].dstapic == MP_APIC_ALL)
1020 if (!test_bit(lbus, mp_bus_not_pci) &&
1021 !mp_irqs[i].irqtype &&
1023 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1024 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1026 if (!(apic || IO_APIC_IRQ(irq)))
1029 if (pin == (mp_irqs[i].srcbusirq & 3))
1032 * Use the first all-but-pin matching entry as a
1033 * best-guess fuzzy result for broken mptables.
1042 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1044 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1046 * EISA Edge/Level control register, ELCR
1048 static int EISA_ELCR(unsigned int irq)
1050 if (irq < NR_IRQS_LEGACY) {
1051 unsigned int port = 0x4d0 + (irq >> 3);
1052 return (inb(port) >> (irq & 7)) & 1;
1054 apic_printk(APIC_VERBOSE, KERN_INFO
1055 "Broken MPtable reports ISA irq %d\n", irq);
1061 /* ISA interrupts are always polarity zero edge triggered,
1062 * when listed as conforming in the MP table. */
1064 #define default_ISA_trigger(idx) (0)
1065 #define default_ISA_polarity(idx) (0)
1067 /* EISA interrupts are always polarity zero and can be edge or level
1068 * trigger depending on the ELCR value. If an interrupt is listed as
1069 * EISA conforming in the MP table, that means its trigger type must
1070 * be read in from the ELCR */
1072 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1073 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1075 /* PCI interrupts are always polarity one level triggered,
1076 * when listed as conforming in the MP table. */
1078 #define default_PCI_trigger(idx) (1)
1079 #define default_PCI_polarity(idx) (1)
1081 /* MCA interrupts are always polarity zero level triggered,
1082 * when listed as conforming in the MP table. */
1084 #define default_MCA_trigger(idx) (1)
1085 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1087 static int MPBIOS_polarity(int idx)
1089 int bus = mp_irqs[idx].srcbus;
1093 * Determine IRQ line polarity (high active or low active):
1095 switch (mp_irqs[idx].irqflag & 3)
1097 case 0: /* conforms, ie. bus-type dependent polarity */
1098 if (test_bit(bus, mp_bus_not_pci))
1099 polarity = default_ISA_polarity(idx);
1101 polarity = default_PCI_polarity(idx);
1103 case 1: /* high active */
1108 case 2: /* reserved */
1110 printk(KERN_WARNING "broken BIOS!!\n");
1114 case 3: /* low active */
1119 default: /* invalid */
1121 printk(KERN_WARNING "broken BIOS!!\n");
1129 static int MPBIOS_trigger(int idx)
1131 int bus = mp_irqs[idx].srcbus;
1135 * Determine IRQ trigger mode (edge or level sensitive):
1137 switch ((mp_irqs[idx].irqflag>>2) & 3)
1139 case 0: /* conforms, ie. bus-type dependent */
1140 if (test_bit(bus, mp_bus_not_pci))
1141 trigger = default_ISA_trigger(idx);
1143 trigger = default_PCI_trigger(idx);
1144 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1145 switch (mp_bus_id_to_type[bus]) {
1146 case MP_BUS_ISA: /* ISA pin */
1148 /* set before the switch */
1151 case MP_BUS_EISA: /* EISA pin */
1153 trigger = default_EISA_trigger(idx);
1156 case MP_BUS_PCI: /* PCI pin */
1158 /* set before the switch */
1161 case MP_BUS_MCA: /* MCA pin */
1163 trigger = default_MCA_trigger(idx);
1168 printk(KERN_WARNING "broken BIOS!!\n");
1180 case 2: /* reserved */
1182 printk(KERN_WARNING "broken BIOS!!\n");
1191 default: /* invalid */
1193 printk(KERN_WARNING "broken BIOS!!\n");
1201 static inline int irq_polarity(int idx)
1203 return MPBIOS_polarity(idx);
1206 static inline int irq_trigger(int idx)
1208 return MPBIOS_trigger(idx);
1211 int (*ioapic_renumber_irq)(int ioapic, int irq);
1212 static int pin_2_irq(int idx, int apic, int pin)
1215 int bus = mp_irqs[idx].srcbus;
1218 * Debugging check, we are in big trouble if this message pops up!
1220 if (mp_irqs[idx].dstirq != pin)
1221 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1223 if (test_bit(bus, mp_bus_not_pci)) {
1224 irq = mp_irqs[idx].srcbusirq;
1227 * PCI IRQs are mapped in order
1231 irq += nr_ioapic_registers[i++];
1234 * For MPS mode, so far only needed by ES7000 platform
1236 if (ioapic_renumber_irq)
1237 irq = ioapic_renumber_irq(apic, irq);
1240 #ifdef CONFIG_X86_32
1242 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1244 if ((pin >= 16) && (pin <= 23)) {
1245 if (pirq_entries[pin-16] != -1) {
1246 if (!pirq_entries[pin-16]) {
1247 apic_printk(APIC_VERBOSE, KERN_DEBUG
1248 "disabling PIRQ%d\n", pin-16);
1250 irq = pirq_entries[pin-16];
1251 apic_printk(APIC_VERBOSE, KERN_DEBUG
1252 "using PIRQ%d -> IRQ %d\n",
1262 void lock_vector_lock(void)
1264 /* Used to the online set of cpus does not change
1265 * during assign_irq_vector.
1267 spin_lock(&vector_lock);
1270 void unlock_vector_lock(void)
1272 spin_unlock(&vector_lock);
1276 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1279 * NOTE! The local APIC isn't very good at handling
1280 * multiple interrupts at the same interrupt level.
1281 * As the interrupt level is determined by taking the
1282 * vector number and shifting that right by 4, we
1283 * want to spread these out a bit so that they don't
1284 * all fall in the same interrupt level.
1286 * Also, we've got to be careful not to trash gate
1287 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1289 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1290 unsigned int old_vector;
1292 cpumask_var_t tmp_mask;
1294 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1297 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1300 old_vector = cfg->vector;
1302 cpumask_and(tmp_mask, mask, cpu_online_mask);
1303 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1304 if (!cpumask_empty(tmp_mask)) {
1305 free_cpumask_var(tmp_mask);
1310 /* Only try and allocate irqs on cpus that are present */
1312 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1316 apic->vector_allocation_domain(cpu, tmp_mask);
1318 vector = current_vector;
1319 offset = current_offset;
1322 if (vector >= first_system_vector) {
1323 /* If out of vectors on large boxen, must share them. */
1324 offset = (offset + 1) % 8;
1325 vector = FIRST_DEVICE_VECTOR + offset;
1327 if (unlikely(current_vector == vector))
1330 if (test_bit(vector, used_vectors))
1333 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1334 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1337 current_vector = vector;
1338 current_offset = offset;
1340 cfg->move_in_progress = 1;
1341 cpumask_copy(cfg->old_domain, cfg->domain);
1343 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1344 per_cpu(vector_irq, new_cpu)[vector] = irq;
1345 cfg->vector = vector;
1346 cpumask_copy(cfg->domain, tmp_mask);
1350 free_cpumask_var(tmp_mask);
1355 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1358 unsigned long flags;
1360 spin_lock_irqsave(&vector_lock, flags);
1361 err = __assign_irq_vector(irq, cfg, mask);
1362 spin_unlock_irqrestore(&vector_lock, flags);
1366 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1370 BUG_ON(!cfg->vector);
1372 vector = cfg->vector;
1373 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1374 per_cpu(vector_irq, cpu)[vector] = -1;
1377 cpumask_clear(cfg->domain);
1379 if (likely(!cfg->move_in_progress))
1381 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1382 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1384 if (per_cpu(vector_irq, cpu)[vector] != irq)
1386 per_cpu(vector_irq, cpu)[vector] = -1;
1390 cfg->move_in_progress = 0;
1393 void __setup_vector_irq(int cpu)
1395 /* Initialize vector_irq on a new cpu */
1396 /* This function must be called with vector_lock held */
1398 struct irq_cfg *cfg;
1399 struct irq_desc *desc;
1401 /* Mark the inuse vectors */
1402 for_each_irq_desc(irq, desc) {
1403 cfg = desc->chip_data;
1404 if (!cpumask_test_cpu(cpu, cfg->domain))
1406 vector = cfg->vector;
1407 per_cpu(vector_irq, cpu)[vector] = irq;
1409 /* Mark the free vectors */
1410 for (vector = 0; vector < NR_VECTORS; ++vector) {
1411 irq = per_cpu(vector_irq, cpu)[vector];
1416 if (!cpumask_test_cpu(cpu, cfg->domain))
1417 per_cpu(vector_irq, cpu)[vector] = -1;
1421 static struct irq_chip ioapic_chip;
1422 #ifdef CONFIG_INTR_REMAP
1423 static struct irq_chip ir_ioapic_chip;
1426 #define IOAPIC_AUTO -1
1427 #define IOAPIC_EDGE 0
1428 #define IOAPIC_LEVEL 1
1430 #ifdef CONFIG_X86_32
1431 static inline int IO_APIC_irq_trigger(int irq)
1435 for (apic = 0; apic < nr_ioapics; apic++) {
1436 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1437 idx = find_irq_entry(apic, pin, mp_INT);
1438 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1439 return irq_trigger(idx);
1443 * nonexistent IRQs are edge default
1448 static inline int IO_APIC_irq_trigger(int irq)
1454 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1457 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1458 trigger == IOAPIC_LEVEL)
1459 desc->status |= IRQ_LEVEL;
1461 desc->status &= ~IRQ_LEVEL;
1463 #ifdef CONFIG_INTR_REMAP
1464 if (irq_remapped(irq)) {
1465 desc->status |= IRQ_MOVE_PCNTXT;
1467 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1471 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1472 handle_edge_irq, "edge");
1476 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1477 trigger == IOAPIC_LEVEL)
1478 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1482 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1483 handle_edge_irq, "edge");
1486 int setup_ioapic_entry(int apic_id, int irq,
1487 struct IO_APIC_route_entry *entry,
1488 unsigned int destination, int trigger,
1489 int polarity, int vector, int pin)
1492 * add it to the IO-APIC irq-routing table:
1494 memset(entry,0,sizeof(*entry));
1496 #ifdef CONFIG_INTR_REMAP
1497 if (intr_remapping_enabled) {
1498 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1500 struct IR_IO_APIC_route_entry *ir_entry =
1501 (struct IR_IO_APIC_route_entry *) entry;
1505 panic("No mapping iommu for ioapic %d\n", apic_id);
1507 index = alloc_irte(iommu, irq, 1);
1509 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1511 memset(&irte, 0, sizeof(irte));
1514 irte.dst_mode = apic->irq_dest_mode;
1516 * Trigger mode in the IRTE will always be edge, and the
1517 * actual level or edge trigger will be setup in the IO-APIC
1518 * RTE. This will help simplify level triggered irq migration.
1519 * For more details, see the comments above explainig IO-APIC
1520 * irq migration in the presence of interrupt-remapping.
1522 irte.trigger_mode = 0;
1523 irte.dlvry_mode = apic->irq_delivery_mode;
1524 irte.vector = vector;
1525 irte.dest_id = IRTE_DEST(destination);
1527 modify_irte(irq, &irte);
1529 ir_entry->index2 = (index >> 15) & 0x1;
1531 ir_entry->format = 1;
1532 ir_entry->index = (index & 0x7fff);
1534 * IO-APIC RTE will be configured with virtual vector.
1535 * irq handler will do the explicit EOI to the io-apic.
1537 ir_entry->vector = pin;
1541 entry->delivery_mode = apic->irq_delivery_mode;
1542 entry->dest_mode = apic->irq_dest_mode;
1543 entry->dest = destination;
1544 entry->vector = vector;
1547 entry->mask = 0; /* enable IRQ */
1548 entry->trigger = trigger;
1549 entry->polarity = polarity;
1551 /* Mask level triggered irqs.
1552 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1559 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1560 int trigger, int polarity)
1562 struct irq_cfg *cfg;
1563 struct IO_APIC_route_entry entry;
1566 if (!IO_APIC_IRQ(irq))
1569 cfg = desc->chip_data;
1571 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1574 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1576 apic_printk(APIC_VERBOSE,KERN_DEBUG
1577 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1578 "IRQ %d Mode:%i Active:%i)\n",
1579 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1580 irq, trigger, polarity);
1583 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1584 dest, trigger, polarity, cfg->vector, pin)) {
1585 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1586 mp_ioapics[apic_id].apicid, pin);
1587 __clear_irq_vector(irq, cfg);
1591 ioapic_register_intr(irq, desc, trigger);
1592 if (irq < NR_IRQS_LEGACY)
1593 disable_8259A_irq(irq);
1595 ioapic_write_entry(apic_id, pin, entry);
1598 static void __init setup_IO_APIC_irqs(void)
1600 int apic_id, pin, idx, irq;
1602 struct irq_desc *desc;
1603 struct irq_cfg *cfg;
1604 int cpu = boot_cpu_id;
1606 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1608 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1609 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1611 idx = find_irq_entry(apic_id, pin, mp_INT);
1615 apic_printk(APIC_VERBOSE,
1616 KERN_DEBUG " %d-%d",
1617 mp_ioapics[apic_id].apicid, pin);
1619 apic_printk(APIC_VERBOSE, " %d-%d",
1620 mp_ioapics[apic_id].apicid, pin);
1624 apic_printk(APIC_VERBOSE,
1625 " (apicid-pin) not connected\n");
1629 irq = pin_2_irq(idx, apic_id, pin);
1632 * Skip the timer IRQ if there's a quirk handler
1633 * installed and if it returns 1:
1635 if (apic->multi_timer_check &&
1636 apic->multi_timer_check(apic_id, irq))
1639 desc = irq_to_desc_alloc_cpu(irq, cpu);
1641 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1644 cfg = desc->chip_data;
1645 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1647 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1648 irq_trigger(idx), irq_polarity(idx));
1653 apic_printk(APIC_VERBOSE,
1654 " (apicid-pin) not connected\n");
1658 * Set up the timer pin, possibly with the 8259A-master behind.
1660 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1663 struct IO_APIC_route_entry entry;
1665 #ifdef CONFIG_INTR_REMAP
1666 if (intr_remapping_enabled)
1670 memset(&entry, 0, sizeof(entry));
1673 * We use logical delivery to get the timer IRQ
1676 entry.dest_mode = apic->irq_dest_mode;
1677 entry.mask = 0; /* don't mask IRQ for edge */
1678 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1679 entry.delivery_mode = apic->irq_delivery_mode;
1682 entry.vector = vector;
1685 * The timer IRQ doesn't have to know that behind the
1686 * scene we may have a 8259A-master in AEOI mode ...
1688 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1691 * Add it to the IO-APIC irq-routing table:
1693 ioapic_write_entry(apic_id, pin, entry);
1697 __apicdebuginit(void) print_IO_APIC(void)
1700 union IO_APIC_reg_00 reg_00;
1701 union IO_APIC_reg_01 reg_01;
1702 union IO_APIC_reg_02 reg_02;
1703 union IO_APIC_reg_03 reg_03;
1704 unsigned long flags;
1705 struct irq_cfg *cfg;
1706 struct irq_desc *desc;
1709 if (apic_verbosity == APIC_QUIET)
1712 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1713 for (i = 0; i < nr_ioapics; i++)
1714 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1715 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1718 * We are a bit conservative about what we expect. We have to
1719 * know about every hardware change ASAP.
1721 printk(KERN_INFO "testing the IO APIC.......................\n");
1723 for (apic = 0; apic < nr_ioapics; apic++) {
1725 spin_lock_irqsave(&ioapic_lock, flags);
1726 reg_00.raw = io_apic_read(apic, 0);
1727 reg_01.raw = io_apic_read(apic, 1);
1728 if (reg_01.bits.version >= 0x10)
1729 reg_02.raw = io_apic_read(apic, 2);
1730 if (reg_01.bits.version >= 0x20)
1731 reg_03.raw = io_apic_read(apic, 3);
1732 spin_unlock_irqrestore(&ioapic_lock, flags);
1735 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1736 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1737 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1738 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1739 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1741 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1742 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1744 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1745 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1748 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1749 * but the value of reg_02 is read as the previous read register
1750 * value, so ignore it if reg_02 == reg_01.
1752 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1753 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1754 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1758 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1759 * or reg_03, but the value of reg_0[23] is read as the previous read
1760 * register value, so ignore it if reg_03 == reg_0[12].
1762 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1763 reg_03.raw != reg_01.raw) {
1764 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1765 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1768 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1770 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1771 " Stat Dmod Deli Vect: \n");
1773 for (i = 0; i <= reg_01.bits.entries; i++) {
1774 struct IO_APIC_route_entry entry;
1776 entry = ioapic_read_entry(apic, i);
1778 printk(KERN_DEBUG " %02x %03X ",
1783 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1788 entry.delivery_status,
1790 entry.delivery_mode,
1795 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1796 for_each_irq_desc(irq, desc) {
1797 struct irq_pin_list *entry;
1799 cfg = desc->chip_data;
1800 entry = cfg->irq_2_pin;
1803 printk(KERN_DEBUG "IRQ%d ", irq);
1805 printk("-> %d:%d", entry->apic, entry->pin);
1808 entry = entry->next;
1813 printk(KERN_INFO ".................................... done.\n");
1818 __apicdebuginit(void) print_APIC_bitfield(int base)
1823 if (apic_verbosity == APIC_QUIET)
1826 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1827 for (i = 0; i < 8; i++) {
1828 v = apic_read(base + i*0x10);
1829 for (j = 0; j < 32; j++) {
1839 __apicdebuginit(void) print_local_APIC(void *dummy)
1841 unsigned int v, ver, maxlvt;
1844 if (apic_verbosity == APIC_QUIET)
1847 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1848 smp_processor_id(), hard_smp_processor_id());
1849 v = apic_read(APIC_ID);
1850 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1851 v = apic_read(APIC_LVR);
1852 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1853 ver = GET_APIC_VERSION(v);
1854 maxlvt = lapic_get_maxlvt();
1856 v = apic_read(APIC_TASKPRI);
1857 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1859 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1860 if (!APIC_XAPIC(ver)) {
1861 v = apic_read(APIC_ARBPRI);
1862 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1863 v & APIC_ARBPRI_MASK);
1865 v = apic_read(APIC_PROCPRI);
1866 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1870 * Remote read supported only in the 82489DX and local APIC for
1871 * Pentium processors.
1873 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1874 v = apic_read(APIC_RRR);
1875 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1878 v = apic_read(APIC_LDR);
1879 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1880 if (!x2apic_enabled()) {
1881 v = apic_read(APIC_DFR);
1882 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1884 v = apic_read(APIC_SPIV);
1885 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1887 printk(KERN_DEBUG "... APIC ISR field:\n");
1888 print_APIC_bitfield(APIC_ISR);
1889 printk(KERN_DEBUG "... APIC TMR field:\n");
1890 print_APIC_bitfield(APIC_TMR);
1891 printk(KERN_DEBUG "... APIC IRR field:\n");
1892 print_APIC_bitfield(APIC_IRR);
1894 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1895 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1896 apic_write(APIC_ESR, 0);
1898 v = apic_read(APIC_ESR);
1899 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1902 icr = apic_icr_read();
1903 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1904 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1906 v = apic_read(APIC_LVTT);
1907 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1909 if (maxlvt > 3) { /* PC is LVT#4. */
1910 v = apic_read(APIC_LVTPC);
1911 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1913 v = apic_read(APIC_LVT0);
1914 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1915 v = apic_read(APIC_LVT1);
1916 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1918 if (maxlvt > 2) { /* ERR is LVT#3. */
1919 v = apic_read(APIC_LVTERR);
1920 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1923 v = apic_read(APIC_TMICT);
1924 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1925 v = apic_read(APIC_TMCCT);
1926 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1927 v = apic_read(APIC_TDCR);
1928 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1932 __apicdebuginit(void) print_all_local_APICs(void)
1937 for_each_online_cpu(cpu)
1938 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1942 __apicdebuginit(void) print_PIC(void)
1945 unsigned long flags;
1947 if (apic_verbosity == APIC_QUIET)
1950 printk(KERN_DEBUG "\nprinting PIC contents\n");
1952 spin_lock_irqsave(&i8259A_lock, flags);
1954 v = inb(0xa1) << 8 | inb(0x21);
1955 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1957 v = inb(0xa0) << 8 | inb(0x20);
1958 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1962 v = inb(0xa0) << 8 | inb(0x20);
1966 spin_unlock_irqrestore(&i8259A_lock, flags);
1968 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1970 v = inb(0x4d1) << 8 | inb(0x4d0);
1971 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1974 __apicdebuginit(int) print_all_ICs(void)
1977 print_all_local_APICs();
1983 fs_initcall(print_all_ICs);
1986 /* Where if anywhere is the i8259 connect in external int mode */
1987 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1989 void __init enable_IO_APIC(void)
1991 union IO_APIC_reg_01 reg_01;
1992 int i8259_apic, i8259_pin;
1994 unsigned long flags;
1997 * The number of IO-APIC IRQ registers (== #pins):
1999 for (apic = 0; apic < nr_ioapics; apic++) {
2000 spin_lock_irqsave(&ioapic_lock, flags);
2001 reg_01.raw = io_apic_read(apic, 1);
2002 spin_unlock_irqrestore(&ioapic_lock, flags);
2003 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2005 for(apic = 0; apic < nr_ioapics; apic++) {
2007 /* See if any of the pins is in ExtINT mode */
2008 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2009 struct IO_APIC_route_entry entry;
2010 entry = ioapic_read_entry(apic, pin);
2012 /* If the interrupt line is enabled and in ExtInt mode
2013 * I have found the pin where the i8259 is connected.
2015 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2016 ioapic_i8259.apic = apic;
2017 ioapic_i8259.pin = pin;
2023 /* Look to see what if the MP table has reported the ExtINT */
2024 /* If we could not find the appropriate pin by looking at the ioapic
2025 * the i8259 probably is not connected the ioapic but give the
2026 * mptable a chance anyway.
2028 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2029 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2030 /* Trust the MP table if nothing is setup in the hardware */
2031 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2032 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2033 ioapic_i8259.pin = i8259_pin;
2034 ioapic_i8259.apic = i8259_apic;
2036 /* Complain if the MP table and the hardware disagree */
2037 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2038 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2040 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2044 * Do not trust the IO-APIC being empty at bootup
2050 * Not an __init, needed by the reboot code
2052 void disable_IO_APIC(void)
2055 * Clear the IO-APIC before rebooting:
2060 * If the i8259 is routed through an IOAPIC
2061 * Put that IOAPIC in virtual wire mode
2062 * so legacy interrupts can be delivered.
2064 * With interrupt-remapping, for now we will use virtual wire A mode,
2065 * as virtual wire B is little complex (need to configure both
2066 * IOAPIC RTE aswell as interrupt-remapping table entry).
2067 * As this gets called during crash dump, keep this simple for now.
2069 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2070 struct IO_APIC_route_entry entry;
2072 memset(&entry, 0, sizeof(entry));
2073 entry.mask = 0; /* Enabled */
2074 entry.trigger = 0; /* Edge */
2076 entry.polarity = 0; /* High */
2077 entry.delivery_status = 0;
2078 entry.dest_mode = 0; /* Physical */
2079 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2081 entry.dest = read_apic_id();
2084 * Add it to the IO-APIC irq-routing table:
2086 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2090 * Use virtual wire A mode when interrupt remapping is enabled.
2092 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2095 #ifdef CONFIG_X86_32
2097 * function to set the IO-APIC physical IDs based on the
2098 * values stored in the MPC table.
2100 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2103 static void __init setup_ioapic_ids_from_mpc(void)
2105 union IO_APIC_reg_00 reg_00;
2106 physid_mask_t phys_id_present_map;
2109 unsigned char old_id;
2110 unsigned long flags;
2112 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2116 * Don't check I/O APIC IDs for xAPIC systems. They have
2117 * no meaning without the serial APIC bus.
2119 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2120 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2123 * This is broken; anything with a real cpu count has to
2124 * circumvent this idiocy regardless.
2126 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2129 * Set the IOAPIC ID to the value stored in the MPC table.
2131 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2133 /* Read the register 0 value */
2134 spin_lock_irqsave(&ioapic_lock, flags);
2135 reg_00.raw = io_apic_read(apic_id, 0);
2136 spin_unlock_irqrestore(&ioapic_lock, flags);
2138 old_id = mp_ioapics[apic_id].apicid;
2140 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2141 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2142 apic_id, mp_ioapics[apic_id].apicid);
2143 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2145 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2149 * Sanity check, is the ID really free? Every APIC in a
2150 * system must have a unique ID or we get lots of nice
2151 * 'stuck on smp_invalidate_needed IPI wait' messages.
2153 if (apic->check_apicid_used(phys_id_present_map,
2154 mp_ioapics[apic_id].apicid)) {
2155 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2156 apic_id, mp_ioapics[apic_id].apicid);
2157 for (i = 0; i < get_physical_broadcast(); i++)
2158 if (!physid_isset(i, phys_id_present_map))
2160 if (i >= get_physical_broadcast())
2161 panic("Max APIC ID exceeded!\n");
2162 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2164 physid_set(i, phys_id_present_map);
2165 mp_ioapics[apic_id].apicid = i;
2168 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2169 apic_printk(APIC_VERBOSE, "Setting %d in the "
2170 "phys_id_present_map\n",
2171 mp_ioapics[apic_id].apicid);
2172 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2177 * We need to adjust the IRQ routing table
2178 * if the ID changed.
2180 if (old_id != mp_ioapics[apic_id].apicid)
2181 for (i = 0; i < mp_irq_entries; i++)
2182 if (mp_irqs[i].dstapic == old_id)
2184 = mp_ioapics[apic_id].apicid;
2187 * Read the right value from the MPC table and
2188 * write it into the ID register.
2190 apic_printk(APIC_VERBOSE, KERN_INFO
2191 "...changing IO-APIC physical APIC ID to %d ...",
2192 mp_ioapics[apic_id].apicid);
2194 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2195 spin_lock_irqsave(&ioapic_lock, flags);
2196 io_apic_write(apic_id, 0, reg_00.raw);
2197 spin_unlock_irqrestore(&ioapic_lock, flags);
2202 spin_lock_irqsave(&ioapic_lock, flags);
2203 reg_00.raw = io_apic_read(apic_id, 0);
2204 spin_unlock_irqrestore(&ioapic_lock, flags);
2205 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2206 printk("could not set ID!\n");
2208 apic_printk(APIC_VERBOSE, " ok.\n");
2213 int no_timer_check __initdata;
2215 static int __init notimercheck(char *s)
2220 __setup("no_timer_check", notimercheck);
2223 * There is a nasty bug in some older SMP boards, their mptable lies
2224 * about the timer IRQ. We do the following to work around the situation:
2226 * - timer IRQ defaults to IO-APIC IRQ
2227 * - if this function detects that timer IRQs are defunct, then we fall
2228 * back to ISA timer IRQs
2230 static int __init timer_irq_works(void)
2232 unsigned long t1 = jiffies;
2233 unsigned long flags;
2238 local_save_flags(flags);
2240 /* Let ten ticks pass... */
2241 mdelay((10 * 1000) / HZ);
2242 local_irq_restore(flags);
2245 * Expect a few ticks at least, to be sure some possible
2246 * glue logic does not lock up after one or two first
2247 * ticks in a non-ExtINT mode. Also the local APIC
2248 * might have cached one ExtINT interrupt. Finally, at
2249 * least one tick may be lost due to delays.
2253 if (time_after(jiffies, t1 + 4))
2259 * In the SMP+IOAPIC case it might happen that there are an unspecified
2260 * number of pending IRQ events unhandled. These cases are very rare,
2261 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2262 * better to do it this way as thus we do not have to be aware of
2263 * 'pending' interrupts in the IRQ path, except at this point.
2266 * Edge triggered needs to resend any interrupt
2267 * that was delayed but this is now handled in the device
2272 * Starting up a edge-triggered IO-APIC interrupt is
2273 * nasty - we need to make sure that we get the edge.
2274 * If it is already asserted for some reason, we need
2275 * return 1 to indicate that is was pending.
2277 * This is not complete - we should be able to fake
2278 * an edge even if it isn't on the 8259A...
2281 static unsigned int startup_ioapic_irq(unsigned int irq)
2283 int was_pending = 0;
2284 unsigned long flags;
2285 struct irq_cfg *cfg;
2287 spin_lock_irqsave(&ioapic_lock, flags);
2288 if (irq < NR_IRQS_LEGACY) {
2289 disable_8259A_irq(irq);
2290 if (i8259A_irq_pending(irq))
2294 __unmask_IO_APIC_irq(cfg);
2295 spin_unlock_irqrestore(&ioapic_lock, flags);
2300 #ifdef CONFIG_X86_64
2301 static int ioapic_retrigger_irq(unsigned int irq)
2304 struct irq_cfg *cfg = irq_cfg(irq);
2305 unsigned long flags;
2307 spin_lock_irqsave(&vector_lock, flags);
2308 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2309 spin_unlock_irqrestore(&vector_lock, flags);
2314 static int ioapic_retrigger_irq(unsigned int irq)
2316 apic->send_IPI_self(irq_cfg(irq)->vector);
2323 * Level and edge triggered IO-APIC interrupts need different handling,
2324 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2325 * handled with the level-triggered descriptor, but that one has slightly
2326 * more overhead. Level-triggered interrupts cannot be handled with the
2327 * edge-triggered handler, without risking IRQ storms and other ugly
2333 #ifdef CONFIG_INTR_REMAP
2336 * Migrate the IO-APIC irq in the presence of intr-remapping.
2338 * For both level and edge triggered, irq migration is a simple atomic
2339 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2341 * For level triggered, we eliminate the io-apic RTE modification (with the
2342 * updated vector information), by using a virtual vector (io-apic pin number).
2343 * Real vector that is used for interrupting cpu will be coming from
2344 * the interrupt-remapping table entry.
2347 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2349 struct irq_cfg *cfg;
2354 if (!cpumask_intersects(mask, cpu_online_mask))
2358 if (get_irte(irq, &irte))
2361 cfg = desc->chip_data;
2362 if (assign_irq_vector(irq, cfg, mask))
2365 set_extra_move_desc(desc, mask);
2367 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2369 irte.vector = cfg->vector;
2370 irte.dest_id = IRTE_DEST(dest);
2373 * Modified the IRTE and flushes the Interrupt entry cache.
2375 modify_irte(irq, &irte);
2377 if (cfg->move_in_progress)
2378 send_cleanup_vector(cfg);
2380 cpumask_copy(desc->affinity, mask);
2384 * Migrates the IRQ destination in the process context.
2386 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2387 const struct cpumask *mask)
2389 migrate_ioapic_irq_desc(desc, mask);
2391 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2392 const struct cpumask *mask)
2394 struct irq_desc *desc = irq_to_desc(irq);
2396 set_ir_ioapic_affinity_irq_desc(desc, mask);
2400 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2402 unsigned vector, me;
2408 me = smp_processor_id();
2409 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2411 struct irq_desc *desc;
2412 struct irq_cfg *cfg;
2413 irq = __get_cpu_var(vector_irq)[vector];
2418 desc = irq_to_desc(irq);
2423 spin_lock(&desc->lock);
2424 if (!cfg->move_cleanup_count)
2427 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2430 __get_cpu_var(vector_irq)[vector] = -1;
2431 cfg->move_cleanup_count--;
2433 spin_unlock(&desc->lock);
2439 static void irq_complete_move(struct irq_desc **descp)
2441 struct irq_desc *desc = *descp;
2442 struct irq_cfg *cfg = desc->chip_data;
2443 unsigned vector, me;
2445 if (likely(!cfg->move_in_progress)) {
2446 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2447 if (likely(!cfg->move_desc_pending))
2450 /* domain has not changed, but affinity did */
2451 me = smp_processor_id();
2452 if (cpumask_test_cpu(me, desc->affinity)) {
2453 *descp = desc = move_irq_desc(desc, me);
2454 /* get the new one */
2455 cfg = desc->chip_data;
2456 cfg->move_desc_pending = 0;
2462 vector = ~get_irq_regs()->orig_ax;
2463 me = smp_processor_id();
2465 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2466 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2467 *descp = desc = move_irq_desc(desc, me);
2468 /* get the new one */
2469 cfg = desc->chip_data;
2471 send_cleanup_vector(cfg);
2475 static inline void irq_complete_move(struct irq_desc **descp) {}
2478 #ifdef CONFIG_INTR_REMAP
2479 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2482 struct irq_pin_list *entry;
2484 entry = cfg->irq_2_pin;
2492 io_apic_eoi(apic, pin);
2493 entry = entry->next;
2498 eoi_ioapic_irq(struct irq_desc *desc)
2500 struct irq_cfg *cfg;
2501 unsigned long flags;
2505 cfg = desc->chip_data;
2507 spin_lock_irqsave(&ioapic_lock, flags);
2508 __eoi_ioapic_irq(irq, cfg);
2509 spin_unlock_irqrestore(&ioapic_lock, flags);
2512 static void ack_x2apic_level(unsigned int irq)
2514 struct irq_desc *desc = irq_to_desc(irq);
2516 eoi_ioapic_irq(desc);
2519 static void ack_x2apic_edge(unsigned int irq)
2526 static void ack_apic_edge(unsigned int irq)
2528 struct irq_desc *desc = irq_to_desc(irq);
2530 irq_complete_move(&desc);
2531 move_native_irq(irq);
2535 atomic_t irq_mis_count;
2537 static void ack_apic_level(unsigned int irq)
2539 struct irq_desc *desc = irq_to_desc(irq);
2541 #ifdef CONFIG_X86_32
2545 struct irq_cfg *cfg;
2546 int do_unmask_irq = 0;
2548 irq_complete_move(&desc);
2549 #ifdef CONFIG_GENERIC_PENDING_IRQ
2550 /* If we are moving the irq we need to mask it */
2551 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2553 mask_IO_APIC_irq_desc(desc);
2557 #ifdef CONFIG_X86_32
2559 * It appears there is an erratum which affects at least version 0x11
2560 * of I/O APIC (that's the 82093AA and cores integrated into various
2561 * chipsets). Under certain conditions a level-triggered interrupt is
2562 * erroneously delivered as edge-triggered one but the respective IRR
2563 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2564 * message but it will never arrive and further interrupts are blocked
2565 * from the source. The exact reason is so far unknown, but the
2566 * phenomenon was observed when two consecutive interrupt requests
2567 * from a given source get delivered to the same CPU and the source is
2568 * temporarily disabled in between.
2570 * A workaround is to simulate an EOI message manually. We achieve it
2571 * by setting the trigger mode to edge and then to level when the edge
2572 * trigger mode gets detected in the TMR of a local APIC for a
2573 * level-triggered interrupt. We mask the source for the time of the
2574 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2575 * The idea is from Manfred Spraul. --macro
2577 cfg = desc->chip_data;
2580 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2584 * We must acknowledge the irq before we move it or the acknowledge will
2585 * not propagate properly.
2589 /* Now we can move and renable the irq */
2590 if (unlikely(do_unmask_irq)) {
2591 /* Only migrate the irq if the ack has been received.
2593 * On rare occasions the broadcast level triggered ack gets
2594 * delayed going to ioapics, and if we reprogram the
2595 * vector while Remote IRR is still set the irq will never
2598 * To prevent this scenario we read the Remote IRR bit
2599 * of the ioapic. This has two effects.
2600 * - On any sane system the read of the ioapic will
2601 * flush writes (and acks) going to the ioapic from
2603 * - We get to see if the ACK has actually been delivered.
2605 * Based on failed experiments of reprogramming the
2606 * ioapic entry from outside of irq context starting
2607 * with masking the ioapic entry and then polling until
2608 * Remote IRR was clear before reprogramming the
2609 * ioapic I don't trust the Remote IRR bit to be
2610 * completey accurate.
2612 * However there appears to be no other way to plug
2613 * this race, so if the Remote IRR bit is not
2614 * accurate and is causing problems then it is a hardware bug
2615 * and you can go talk to the chipset vendor about it.
2617 cfg = desc->chip_data;
2618 if (!io_apic_level_ack_pending(cfg))
2619 move_masked_irq(irq);
2620 unmask_IO_APIC_irq_desc(desc);
2623 #ifdef CONFIG_X86_32
2624 if (!(v & (1 << (i & 0x1f)))) {
2625 atomic_inc(&irq_mis_count);
2626 spin_lock(&ioapic_lock);
2627 __mask_and_edge_IO_APIC_irq(cfg);
2628 __unmask_and_level_IO_APIC_irq(cfg);
2629 spin_unlock(&ioapic_lock);
2634 static struct irq_chip ioapic_chip __read_mostly = {
2636 .startup = startup_ioapic_irq,
2637 .mask = mask_IO_APIC_irq,
2638 .unmask = unmask_IO_APIC_irq,
2639 .ack = ack_apic_edge,
2640 .eoi = ack_apic_level,
2642 .set_affinity = set_ioapic_affinity_irq,
2644 .retrigger = ioapic_retrigger_irq,
2647 #ifdef CONFIG_INTR_REMAP
2648 static struct irq_chip ir_ioapic_chip __read_mostly = {
2649 .name = "IR-IO-APIC",
2650 .startup = startup_ioapic_irq,
2651 .mask = mask_IO_APIC_irq,
2652 .unmask = unmask_IO_APIC_irq,
2653 .ack = ack_x2apic_edge,
2654 .eoi = ack_x2apic_level,
2656 .set_affinity = set_ir_ioapic_affinity_irq,
2658 .retrigger = ioapic_retrigger_irq,
2662 static inline void init_IO_APIC_traps(void)
2665 struct irq_desc *desc;
2666 struct irq_cfg *cfg;
2669 * NOTE! The local APIC isn't very good at handling
2670 * multiple interrupts at the same interrupt level.
2671 * As the interrupt level is determined by taking the
2672 * vector number and shifting that right by 4, we
2673 * want to spread these out a bit so that they don't
2674 * all fall in the same interrupt level.
2676 * Also, we've got to be careful not to trash gate
2677 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2679 for_each_irq_desc(irq, desc) {
2680 cfg = desc->chip_data;
2681 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2683 * Hmm.. We don't have an entry for this,
2684 * so default to an old-fashioned 8259
2685 * interrupt if we can..
2687 if (irq < NR_IRQS_LEGACY)
2688 make_8259A_irq(irq);
2690 /* Strange. Oh, well.. */
2691 desc->chip = &no_irq_chip;
2697 * The local APIC irq-chip implementation:
2700 static void mask_lapic_irq(unsigned int irq)
2704 v = apic_read(APIC_LVT0);
2705 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2708 static void unmask_lapic_irq(unsigned int irq)
2712 v = apic_read(APIC_LVT0);
2713 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2716 static void ack_lapic_irq(unsigned int irq)
2721 static struct irq_chip lapic_chip __read_mostly = {
2722 .name = "local-APIC",
2723 .mask = mask_lapic_irq,
2724 .unmask = unmask_lapic_irq,
2725 .ack = ack_lapic_irq,
2728 static void lapic_register_intr(int irq, struct irq_desc *desc)
2730 desc->status &= ~IRQ_LEVEL;
2731 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2735 static void __init setup_nmi(void)
2738 * Dirty trick to enable the NMI watchdog ...
2739 * We put the 8259A master into AEOI mode and
2740 * unmask on all local APICs LVT0 as NMI.
2742 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2743 * is from Maciej W. Rozycki - so we do not have to EOI from
2744 * the NMI handler or the timer interrupt.
2746 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2748 enable_NMI_through_LVT0();
2750 apic_printk(APIC_VERBOSE, " done.\n");
2754 * This looks a bit hackish but it's about the only one way of sending
2755 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2756 * not support the ExtINT mode, unfortunately. We need to send these
2757 * cycles as some i82489DX-based boards have glue logic that keeps the
2758 * 8259A interrupt line asserted until INTA. --macro
2760 static inline void __init unlock_ExtINT_logic(void)
2763 struct IO_APIC_route_entry entry0, entry1;
2764 unsigned char save_control, save_freq_select;
2766 pin = find_isa_irq_pin(8, mp_INT);
2771 apic = find_isa_irq_apic(8, mp_INT);
2777 entry0 = ioapic_read_entry(apic, pin);
2778 clear_IO_APIC_pin(apic, pin);
2780 memset(&entry1, 0, sizeof(entry1));
2782 entry1.dest_mode = 0; /* physical delivery */
2783 entry1.mask = 0; /* unmask IRQ now */
2784 entry1.dest = hard_smp_processor_id();
2785 entry1.delivery_mode = dest_ExtINT;
2786 entry1.polarity = entry0.polarity;
2790 ioapic_write_entry(apic, pin, entry1);
2792 save_control = CMOS_READ(RTC_CONTROL);
2793 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2794 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2796 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2801 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2805 CMOS_WRITE(save_control, RTC_CONTROL);
2806 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2807 clear_IO_APIC_pin(apic, pin);
2809 ioapic_write_entry(apic, pin, entry0);
2812 static int disable_timer_pin_1 __initdata;
2813 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2814 static int __init disable_timer_pin_setup(char *arg)
2816 disable_timer_pin_1 = 1;
2819 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2821 int timer_through_8259 __initdata;
2824 * This code may look a bit paranoid, but it's supposed to cooperate with
2825 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2826 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2827 * fanatically on his truly buggy board.
2829 * FIXME: really need to revamp this for all platforms.
2831 static inline void __init check_timer(void)
2833 struct irq_desc *desc = irq_to_desc(0);
2834 struct irq_cfg *cfg = desc->chip_data;
2835 int cpu = boot_cpu_id;
2836 int apic1, pin1, apic2, pin2;
2837 unsigned long flags;
2840 local_irq_save(flags);
2843 * get/set the timer IRQ vector:
2845 disable_8259A_irq(0);
2846 assign_irq_vector(0, cfg, apic->target_cpus());
2849 * As IRQ0 is to be enabled in the 8259A, the virtual
2850 * wire has to be disabled in the local APIC. Also
2851 * timer interrupts need to be acknowledged manually in
2852 * the 8259A for the i82489DX when using the NMI
2853 * watchdog as that APIC treats NMIs as level-triggered.
2854 * The AEOI mode will finish them in the 8259A
2857 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2859 #ifdef CONFIG_X86_32
2863 ver = apic_read(APIC_LVR);
2864 ver = GET_APIC_VERSION(ver);
2865 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2869 pin1 = find_isa_irq_pin(0, mp_INT);
2870 apic1 = find_isa_irq_apic(0, mp_INT);
2871 pin2 = ioapic_i8259.pin;
2872 apic2 = ioapic_i8259.apic;
2874 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2875 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2876 cfg->vector, apic1, pin1, apic2, pin2);
2879 * Some BIOS writers are clueless and report the ExtINTA
2880 * I/O APIC input from the cascaded 8259A as the timer
2881 * interrupt input. So just in case, if only one pin
2882 * was found above, try it both directly and through the
2886 #ifdef CONFIG_INTR_REMAP
2887 if (intr_remapping_enabled)
2888 panic("BIOS bug: timer not connected to IO-APIC");
2893 } else if (pin2 == -1) {
2900 * Ok, does IRQ0 through the IOAPIC work?
2903 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2904 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2906 /* for edge trigger, setup_IO_APIC_irq already
2907 * leave it unmasked.
2908 * so only need to unmask if it is level-trigger
2909 * do we really have level trigger timer?
2912 idx = find_irq_entry(apic1, pin1, mp_INT);
2913 if (idx != -1 && irq_trigger(idx))
2914 unmask_IO_APIC_irq_desc(desc);
2916 if (timer_irq_works()) {
2917 if (nmi_watchdog == NMI_IO_APIC) {
2919 enable_8259A_irq(0);
2921 if (disable_timer_pin_1 > 0)
2922 clear_IO_APIC_pin(0, pin1);
2925 #ifdef CONFIG_INTR_REMAP
2926 if (intr_remapping_enabled)
2927 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2929 local_irq_disable();
2930 clear_IO_APIC_pin(apic1, pin1);
2932 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2933 "8254 timer not connected to IO-APIC\n");
2935 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2936 "(IRQ0) through the 8259A ...\n");
2937 apic_printk(APIC_QUIET, KERN_INFO
2938 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2940 * legacy devices should be connected to IO APIC #0
2942 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2943 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2944 enable_8259A_irq(0);
2945 if (timer_irq_works()) {
2946 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2947 timer_through_8259 = 1;
2948 if (nmi_watchdog == NMI_IO_APIC) {
2949 disable_8259A_irq(0);
2951 enable_8259A_irq(0);
2956 * Cleanup, just in case ...
2958 local_irq_disable();
2959 disable_8259A_irq(0);
2960 clear_IO_APIC_pin(apic2, pin2);
2961 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2964 if (nmi_watchdog == NMI_IO_APIC) {
2965 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2966 "through the IO-APIC - disabling NMI Watchdog!\n");
2967 nmi_watchdog = NMI_NONE;
2969 #ifdef CONFIG_X86_32
2973 apic_printk(APIC_QUIET, KERN_INFO
2974 "...trying to set up timer as Virtual Wire IRQ...\n");
2976 lapic_register_intr(0, desc);
2977 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2978 enable_8259A_irq(0);
2980 if (timer_irq_works()) {
2981 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2984 local_irq_disable();
2985 disable_8259A_irq(0);
2986 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2987 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2989 apic_printk(APIC_QUIET, KERN_INFO
2990 "...trying to set up timer as ExtINT IRQ...\n");
2994 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2996 unlock_ExtINT_logic();
2998 if (timer_irq_works()) {
2999 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3002 local_irq_disable();
3003 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3004 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3005 "report. Then try booting with the 'noapic' option.\n");
3007 local_irq_restore(flags);
3011 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3012 * to devices. However there may be an I/O APIC pin available for
3013 * this interrupt regardless. The pin may be left unconnected, but
3014 * typically it will be reused as an ExtINT cascade interrupt for
3015 * the master 8259A. In the MPS case such a pin will normally be
3016 * reported as an ExtINT interrupt in the MP table. With ACPI
3017 * there is no provision for ExtINT interrupts, and in the absence
3018 * of an override it would be treated as an ordinary ISA I/O APIC
3019 * interrupt, that is edge-triggered and unmasked by default. We
3020 * used to do this, but it caused problems on some systems because
3021 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3022 * the same ExtINT cascade interrupt to drive the local APIC of the
3023 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3024 * the I/O APIC in all cases now. No actual device should request
3025 * it anyway. --macro
3027 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3029 void __init setup_IO_APIC(void)
3033 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3036 io_apic_irqs = ~PIC_IRQS;
3038 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3040 * Set up IO-APIC IRQ routing.
3042 #ifdef CONFIG_X86_32
3044 setup_ioapic_ids_from_mpc();
3047 setup_IO_APIC_irqs();
3048 init_IO_APIC_traps();
3053 * Called after all the initialization is done. If we didnt find any
3054 * APIC bugs then we can allow the modify fast path
3057 static int __init io_apic_bug_finalize(void)
3059 if (sis_apic_bug == -1)
3064 late_initcall(io_apic_bug_finalize);
3066 struct sysfs_ioapic_data {
3067 struct sys_device dev;
3068 struct IO_APIC_route_entry entry[0];
3070 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3072 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3074 struct IO_APIC_route_entry *entry;
3075 struct sysfs_ioapic_data *data;
3078 data = container_of(dev, struct sysfs_ioapic_data, dev);
3079 entry = data->entry;
3080 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3081 *entry = ioapic_read_entry(dev->id, i);
3086 static int ioapic_resume(struct sys_device *dev)
3088 struct IO_APIC_route_entry *entry;
3089 struct sysfs_ioapic_data *data;
3090 unsigned long flags;
3091 union IO_APIC_reg_00 reg_00;
3094 data = container_of(dev, struct sysfs_ioapic_data, dev);
3095 entry = data->entry;
3097 spin_lock_irqsave(&ioapic_lock, flags);
3098 reg_00.raw = io_apic_read(dev->id, 0);
3099 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3100 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3101 io_apic_write(dev->id, 0, reg_00.raw);
3103 spin_unlock_irqrestore(&ioapic_lock, flags);
3104 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3105 ioapic_write_entry(dev->id, i, entry[i]);
3110 static struct sysdev_class ioapic_sysdev_class = {
3112 .suspend = ioapic_suspend,
3113 .resume = ioapic_resume,
3116 static int __init ioapic_init_sysfs(void)
3118 struct sys_device * dev;
3121 error = sysdev_class_register(&ioapic_sysdev_class);
3125 for (i = 0; i < nr_ioapics; i++ ) {
3126 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3127 * sizeof(struct IO_APIC_route_entry);
3128 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3129 if (!mp_ioapic_data[i]) {
3130 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3133 dev = &mp_ioapic_data[i]->dev;
3135 dev->cls = &ioapic_sysdev_class;
3136 error = sysdev_register(dev);
3138 kfree(mp_ioapic_data[i]);
3139 mp_ioapic_data[i] = NULL;
3140 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3148 device_initcall(ioapic_init_sysfs);
3150 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3152 * Dynamic irq allocate and deallocation
3154 unsigned int create_irq_nr(unsigned int irq_want)
3156 /* Allocate an unused irq */
3159 unsigned long flags;
3160 struct irq_cfg *cfg_new = NULL;
3161 int cpu = boot_cpu_id;
3162 struct irq_desc *desc_new = NULL;
3165 if (irq_want < nr_irqs_gsi)
3166 irq_want = nr_irqs_gsi;
3168 spin_lock_irqsave(&vector_lock, flags);
3169 for (new = irq_want; new < nr_irqs; new++) {
3170 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3172 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3175 cfg_new = desc_new->chip_data;
3177 if (cfg_new->vector != 0)
3179 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3183 spin_unlock_irqrestore(&vector_lock, flags);
3186 dynamic_irq_init(irq);
3187 /* restore it, in case dynamic_irq_init clear it */
3189 desc_new->chip_data = cfg_new;
3194 int create_irq(void)
3196 unsigned int irq_want;
3199 irq_want = nr_irqs_gsi;
3200 irq = create_irq_nr(irq_want);
3208 void destroy_irq(unsigned int irq)
3210 unsigned long flags;
3211 struct irq_cfg *cfg;
3212 struct irq_desc *desc;
3214 /* store it, in case dynamic_irq_cleanup clear it */
3215 desc = irq_to_desc(irq);
3216 cfg = desc->chip_data;
3217 dynamic_irq_cleanup(irq);
3218 /* connect back irq_cfg */
3220 desc->chip_data = cfg;
3222 #ifdef CONFIG_INTR_REMAP
3225 spin_lock_irqsave(&vector_lock, flags);
3226 __clear_irq_vector(irq, cfg);
3227 spin_unlock_irqrestore(&vector_lock, flags);
3231 * MSI message composition
3233 #ifdef CONFIG_PCI_MSI
3234 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3236 struct irq_cfg *cfg;
3244 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3248 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3250 #ifdef CONFIG_INTR_REMAP
3251 if (irq_remapped(irq)) {
3256 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3257 BUG_ON(ir_index == -1);
3259 memset (&irte, 0, sizeof(irte));
3262 irte.dst_mode = apic->irq_dest_mode;
3263 irte.trigger_mode = 0; /* edge */
3264 irte.dlvry_mode = apic->irq_delivery_mode;
3265 irte.vector = cfg->vector;
3266 irte.dest_id = IRTE_DEST(dest);
3268 modify_irte(irq, &irte);
3270 msg->address_hi = MSI_ADDR_BASE_HI;
3271 msg->data = sub_handle;
3272 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3274 MSI_ADDR_IR_INDEX1(ir_index) |
3275 MSI_ADDR_IR_INDEX2(ir_index);
3279 if (x2apic_enabled())
3280 msg->address_hi = MSI_ADDR_BASE_HI |
3281 MSI_ADDR_EXT_DEST_ID(dest);
3283 msg->address_hi = MSI_ADDR_BASE_HI;
3287 ((apic->irq_dest_mode == 0) ?
3288 MSI_ADDR_DEST_MODE_PHYSICAL:
3289 MSI_ADDR_DEST_MODE_LOGICAL) |
3290 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3291 MSI_ADDR_REDIRECTION_CPU:
3292 MSI_ADDR_REDIRECTION_LOWPRI) |
3293 MSI_ADDR_DEST_ID(dest);
3296 MSI_DATA_TRIGGER_EDGE |
3297 MSI_DATA_LEVEL_ASSERT |
3298 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3299 MSI_DATA_DELIVERY_FIXED:
3300 MSI_DATA_DELIVERY_LOWPRI) |
3301 MSI_DATA_VECTOR(cfg->vector);
3307 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3309 struct irq_desc *desc = irq_to_desc(irq);
3310 struct irq_cfg *cfg;
3314 dest = set_desc_affinity(desc, mask);
3315 if (dest == BAD_APICID)
3318 cfg = desc->chip_data;
3320 read_msi_msg_desc(desc, &msg);
3322 msg.data &= ~MSI_DATA_VECTOR_MASK;
3323 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3324 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3325 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3327 write_msi_msg_desc(desc, &msg);
3329 #ifdef CONFIG_INTR_REMAP
3331 * Migrate the MSI irq to another cpumask. This migration is
3332 * done in the process context using interrupt-remapping hardware.
3335 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3337 struct irq_desc *desc = irq_to_desc(irq);
3338 struct irq_cfg *cfg = desc->chip_data;
3342 if (get_irte(irq, &irte))
3345 dest = set_desc_affinity(desc, mask);
3346 if (dest == BAD_APICID)
3349 irte.vector = cfg->vector;
3350 irte.dest_id = IRTE_DEST(dest);
3353 * atomically update the IRTE with the new destination and vector.
3355 modify_irte(irq, &irte);
3358 * After this point, all the interrupts will start arriving
3359 * at the new destination. So, time to cleanup the previous
3360 * vector allocation.
3362 if (cfg->move_in_progress)
3363 send_cleanup_vector(cfg);
3367 #endif /* CONFIG_SMP */
3370 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3371 * which implement the MSI or MSI-X Capability Structure.
3373 static struct irq_chip msi_chip = {
3375 .unmask = unmask_msi_irq,
3376 .mask = mask_msi_irq,
3377 .ack = ack_apic_edge,
3379 .set_affinity = set_msi_irq_affinity,
3381 .retrigger = ioapic_retrigger_irq,
3384 #ifdef CONFIG_INTR_REMAP
3385 static struct irq_chip msi_ir_chip = {
3386 .name = "IR-PCI-MSI",
3387 .unmask = unmask_msi_irq,
3388 .mask = mask_msi_irq,
3389 .ack = ack_x2apic_edge,
3391 .set_affinity = ir_set_msi_irq_affinity,
3393 .retrigger = ioapic_retrigger_irq,
3397 * Map the PCI dev to the corresponding remapping hardware unit
3398 * and allocate 'nvec' consecutive interrupt-remapping table entries
3401 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3403 struct intel_iommu *iommu;
3406 iommu = map_dev_to_ir(dev);
3409 "Unable to map PCI %s to iommu\n", pci_name(dev));
3413 index = alloc_irte(iommu, irq, nvec);
3416 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3424 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3429 ret = msi_compose_msg(dev, irq, &msg);
3433 set_irq_msi(irq, msidesc);
3434 write_msi_msg(irq, &msg);
3436 #ifdef CONFIG_INTR_REMAP
3437 if (irq_remapped(irq)) {
3438 struct irq_desc *desc = irq_to_desc(irq);
3440 * irq migration in process context
3442 desc->status |= IRQ_MOVE_PCNTXT;
3443 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3446 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3448 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3453 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3456 int ret, sub_handle;
3457 struct msi_desc *msidesc;
3458 unsigned int irq_want;
3460 #ifdef CONFIG_INTR_REMAP
3461 struct intel_iommu *iommu = 0;
3465 irq_want = nr_irqs_gsi;
3467 list_for_each_entry(msidesc, &dev->msi_list, list) {
3468 irq = create_irq_nr(irq_want);
3472 #ifdef CONFIG_INTR_REMAP
3473 if (!intr_remapping_enabled)
3478 * allocate the consecutive block of IRTE's
3481 index = msi_alloc_irte(dev, irq, nvec);
3487 iommu = map_dev_to_ir(dev);
3493 * setup the mapping between the irq and the IRTE
3494 * base index, the sub_handle pointing to the
3495 * appropriate interrupt remap table entry.
3497 set_irte_irq(irq, iommu, index, sub_handle);
3501 ret = setup_msi_irq(dev, msidesc, irq);
3513 void arch_teardown_msi_irq(unsigned int irq)
3518 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3520 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3522 struct irq_desc *desc = irq_to_desc(irq);
3523 struct irq_cfg *cfg;
3527 dest = set_desc_affinity(desc, mask);
3528 if (dest == BAD_APICID)
3531 cfg = desc->chip_data;
3533 dmar_msi_read(irq, &msg);
3535 msg.data &= ~MSI_DATA_VECTOR_MASK;
3536 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3537 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3538 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3540 dmar_msi_write(irq, &msg);
3543 #endif /* CONFIG_SMP */
3545 struct irq_chip dmar_msi_type = {
3547 .unmask = dmar_msi_unmask,
3548 .mask = dmar_msi_mask,
3549 .ack = ack_apic_edge,
3551 .set_affinity = dmar_msi_set_affinity,
3553 .retrigger = ioapic_retrigger_irq,
3556 int arch_setup_dmar_msi(unsigned int irq)
3561 ret = msi_compose_msg(NULL, irq, &msg);
3564 dmar_msi_write(irq, &msg);
3565 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3571 #ifdef CONFIG_HPET_TIMER
3574 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3576 struct irq_desc *desc = irq_to_desc(irq);
3577 struct irq_cfg *cfg;
3581 dest = set_desc_affinity(desc, mask);
3582 if (dest == BAD_APICID)
3585 cfg = desc->chip_data;
3587 hpet_msi_read(irq, &msg);
3589 msg.data &= ~MSI_DATA_VECTOR_MASK;
3590 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3591 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3592 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3594 hpet_msi_write(irq, &msg);
3597 #endif /* CONFIG_SMP */
3599 struct irq_chip hpet_msi_type = {
3601 .unmask = hpet_msi_unmask,
3602 .mask = hpet_msi_mask,
3603 .ack = ack_apic_edge,
3605 .set_affinity = hpet_msi_set_affinity,
3607 .retrigger = ioapic_retrigger_irq,
3610 int arch_setup_hpet_msi(unsigned int irq)
3615 ret = msi_compose_msg(NULL, irq, &msg);
3619 hpet_msi_write(irq, &msg);
3620 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3627 #endif /* CONFIG_PCI_MSI */
3629 * Hypertransport interrupt support
3631 #ifdef CONFIG_HT_IRQ
3635 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3637 struct ht_irq_msg msg;
3638 fetch_ht_irq_msg(irq, &msg);
3640 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3641 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3643 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3644 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3646 write_ht_irq_msg(irq, &msg);
3649 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3651 struct irq_desc *desc = irq_to_desc(irq);
3652 struct irq_cfg *cfg;
3655 dest = set_desc_affinity(desc, mask);
3656 if (dest == BAD_APICID)
3659 cfg = desc->chip_data;
3661 target_ht_irq(irq, dest, cfg->vector);
3666 static struct irq_chip ht_irq_chip = {
3668 .mask = mask_ht_irq,
3669 .unmask = unmask_ht_irq,
3670 .ack = ack_apic_edge,
3672 .set_affinity = set_ht_irq_affinity,
3674 .retrigger = ioapic_retrigger_irq,
3677 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3679 struct irq_cfg *cfg;
3686 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3688 struct ht_irq_msg msg;
3691 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3692 apic->target_cpus());
3694 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3698 HT_IRQ_LOW_DEST_ID(dest) |
3699 HT_IRQ_LOW_VECTOR(cfg->vector) |
3700 ((apic->irq_dest_mode == 0) ?
3701 HT_IRQ_LOW_DM_PHYSICAL :
3702 HT_IRQ_LOW_DM_LOGICAL) |
3703 HT_IRQ_LOW_RQEOI_EDGE |
3704 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3705 HT_IRQ_LOW_MT_FIXED :
3706 HT_IRQ_LOW_MT_ARBITRATED) |
3707 HT_IRQ_LOW_IRQ_MASKED;
3709 write_ht_irq_msg(irq, &msg);
3711 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3712 handle_edge_irq, "edge");
3714 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3718 #endif /* CONFIG_HT_IRQ */
3720 #ifdef CONFIG_X86_UV
3722 * Re-target the irq to the specified CPU and enable the specified MMR located
3723 * on the specified blade to allow the sending of MSIs to the specified CPU.
3725 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3726 unsigned long mmr_offset)
3728 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3729 struct irq_cfg *cfg;
3731 unsigned long mmr_value;
3732 struct uv_IO_APIC_route_entry *entry;
3733 unsigned long flags;
3738 err = assign_irq_vector(irq, cfg, eligible_cpu);
3742 spin_lock_irqsave(&vector_lock, flags);
3743 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3745 spin_unlock_irqrestore(&vector_lock, flags);
3748 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3749 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3751 entry->vector = cfg->vector;
3752 entry->delivery_mode = apic->irq_delivery_mode;
3753 entry->dest_mode = apic->irq_dest_mode;
3754 entry->polarity = 0;
3757 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3759 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3760 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3766 * Disable the specified MMR located on the specified blade so that MSIs are
3767 * longer allowed to be sent.
3769 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3771 unsigned long mmr_value;
3772 struct uv_IO_APIC_route_entry *entry;
3776 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3777 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3781 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3782 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3784 #endif /* CONFIG_X86_64 */
3786 int __init io_apic_get_redir_entries (int ioapic)
3788 union IO_APIC_reg_01 reg_01;
3789 unsigned long flags;
3791 spin_lock_irqsave(&ioapic_lock, flags);
3792 reg_01.raw = io_apic_read(ioapic, 1);
3793 spin_unlock_irqrestore(&ioapic_lock, flags);
3795 return reg_01.bits.entries;
3798 void __init probe_nr_irqs_gsi(void)
3802 nr = acpi_probe_gsi();
3803 if (nr > nr_irqs_gsi) {
3806 /* for acpi=off or acpi is not compiled in */
3810 for (idx = 0; idx < nr_ioapics; idx++)
3811 nr += io_apic_get_redir_entries(idx) + 1;
3813 if (nr > nr_irqs_gsi)
3817 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3820 #ifdef CONFIG_SPARSE_IRQ
3821 int __init arch_probe_nr_irqs(void)
3825 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3826 nr_irqs = NR_VECTORS * nr_cpu_ids;
3828 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3829 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3831 * for MSI and HT dyn irq
3833 nr += nr_irqs_gsi * 16;
3842 /* --------------------------------------------------------------------------
3843 ACPI-based IOAPIC Configuration
3844 -------------------------------------------------------------------------- */
3848 #ifdef CONFIG_X86_32
3849 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3851 union IO_APIC_reg_00 reg_00;
3852 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3854 unsigned long flags;
3858 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3859 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3860 * supports up to 16 on one shared APIC bus.
3862 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3863 * advantage of new APIC bus architecture.
3866 if (physids_empty(apic_id_map))
3867 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3869 spin_lock_irqsave(&ioapic_lock, flags);
3870 reg_00.raw = io_apic_read(ioapic, 0);
3871 spin_unlock_irqrestore(&ioapic_lock, flags);
3873 if (apic_id >= get_physical_broadcast()) {
3874 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3875 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3876 apic_id = reg_00.bits.ID;
3880 * Every APIC in a system must have a unique ID or we get lots of nice
3881 * 'stuck on smp_invalidate_needed IPI wait' messages.
3883 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3885 for (i = 0; i < get_physical_broadcast(); i++) {
3886 if (!apic->check_apicid_used(apic_id_map, i))
3890 if (i == get_physical_broadcast())
3891 panic("Max apic_id exceeded!\n");
3893 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3894 "trying %d\n", ioapic, apic_id, i);
3899 tmp = apic->apicid_to_cpu_present(apic_id);
3900 physids_or(apic_id_map, apic_id_map, tmp);
3902 if (reg_00.bits.ID != apic_id) {
3903 reg_00.bits.ID = apic_id;
3905 spin_lock_irqsave(&ioapic_lock, flags);
3906 io_apic_write(ioapic, 0, reg_00.raw);
3907 reg_00.raw = io_apic_read(ioapic, 0);
3908 spin_unlock_irqrestore(&ioapic_lock, flags);
3911 if (reg_00.bits.ID != apic_id) {
3912 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3917 apic_printk(APIC_VERBOSE, KERN_INFO
3918 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3923 int __init io_apic_get_version(int ioapic)
3925 union IO_APIC_reg_01 reg_01;
3926 unsigned long flags;
3928 spin_lock_irqsave(&ioapic_lock, flags);
3929 reg_01.raw = io_apic_read(ioapic, 1);
3930 spin_unlock_irqrestore(&ioapic_lock, flags);
3932 return reg_01.bits.version;
3936 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3938 struct irq_desc *desc;
3939 struct irq_cfg *cfg;
3940 int cpu = boot_cpu_id;
3942 if (!IO_APIC_IRQ(irq)) {
3943 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3948 desc = irq_to_desc_alloc_cpu(irq, cpu);
3950 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3955 * IRQs < 16 are already in the irq_2_pin[] map
3957 if (irq >= NR_IRQS_LEGACY) {
3958 cfg = desc->chip_data;
3959 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3962 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3968 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3972 if (skip_ioapic_setup)
3975 for (i = 0; i < mp_irq_entries; i++)
3976 if (mp_irqs[i].irqtype == mp_INT &&
3977 mp_irqs[i].srcbusirq == bus_irq)
3979 if (i >= mp_irq_entries)
3982 *trigger = irq_trigger(i);
3983 *polarity = irq_polarity(i);
3987 #endif /* CONFIG_ACPI */
3990 * This function currently is only a helper for the i386 smp boot process where
3991 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3992 * so mask in all cases should simply be apic->target_cpus()
3995 void __init setup_ioapic_dest(void)
3997 int pin, ioapic, irq, irq_entry;
3998 struct irq_desc *desc;
3999 struct irq_cfg *cfg;
4000 const struct cpumask *mask;
4002 if (skip_ioapic_setup == 1)
4005 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4006 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4007 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4008 if (irq_entry == -1)
4010 irq = pin_2_irq(irq_entry, ioapic, pin);
4012 /* setup_IO_APIC_irqs could fail to get vector for some device
4013 * when you have too many devices, because at that time only boot
4016 desc = irq_to_desc(irq);
4017 cfg = desc->chip_data;
4019 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4020 irq_trigger(irq_entry),
4021 irq_polarity(irq_entry));
4027 * Honour affinities which have been set in early boot
4030 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4031 mask = desc->affinity;
4033 mask = apic->target_cpus();
4035 #ifdef CONFIG_INTR_REMAP
4036 if (intr_remapping_enabled)
4037 set_ir_ioapic_affinity_irq_desc(desc, mask);
4040 set_ioapic_affinity_irq_desc(desc, mask);
4047 #define IOAPIC_RESOURCE_NAME_SIZE 11
4049 static struct resource *ioapic_resources;
4051 static struct resource * __init ioapic_setup_resources(void)
4054 struct resource *res;
4058 if (nr_ioapics <= 0)
4061 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4064 mem = alloc_bootmem(n);
4068 mem += sizeof(struct resource) * nr_ioapics;
4070 for (i = 0; i < nr_ioapics; i++) {
4072 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4073 sprintf(mem, "IOAPIC %u", i);
4074 mem += IOAPIC_RESOURCE_NAME_SIZE;
4078 ioapic_resources = res;
4083 void __init ioapic_init_mappings(void)
4085 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4086 struct resource *ioapic_res;
4089 ioapic_res = ioapic_setup_resources();
4090 for (i = 0; i < nr_ioapics; i++) {
4091 if (smp_found_config) {
4092 ioapic_phys = mp_ioapics[i].apicaddr;
4093 #ifdef CONFIG_X86_32
4096 "WARNING: bogus zero IO-APIC "
4097 "address found in MPTABLE, "
4098 "disabling IO/APIC support!\n");
4099 smp_found_config = 0;
4100 skip_ioapic_setup = 1;
4101 goto fake_ioapic_page;
4105 #ifdef CONFIG_X86_32
4108 ioapic_phys = (unsigned long)
4109 alloc_bootmem_pages(PAGE_SIZE);
4110 ioapic_phys = __pa(ioapic_phys);
4112 set_fixmap_nocache(idx, ioapic_phys);
4113 apic_printk(APIC_VERBOSE,
4114 "mapped IOAPIC to %08lx (%08lx)\n",
4115 __fix_to_virt(idx), ioapic_phys);
4118 if (ioapic_res != NULL) {
4119 ioapic_res->start = ioapic_phys;
4120 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4126 static int __init ioapic_insert_resources(void)
4129 struct resource *r = ioapic_resources;
4133 "IO APIC resources could be not be allocated.\n");
4137 for (i = 0; i < nr_ioapics; i++) {
4138 insert_resource(&iomem_resource, r);
4145 /* Insert the IO APIC resources after PCI initialization has occured to handle
4146 * IO APICS that are mapped in on a BAR in PCI space. */
4147 late_initcall(ioapic_insert_resources);