2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture or only set the
5 * aperture in the AGP bridge.
6 * If all fails map the aperture over some low memory. This is cheaper than
7 * doing bounce buffering. The memory is lost. This is done at early boot
8 * because only the bootmem allocator can allocate 32+MB.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/bootmem.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci_ids.h>
18 #include <linux/pci.h>
19 #include <linux/bitops.h>
20 #include <linux/ioport.h>
21 #include <linux/suspend.h>
25 #include <asm/pci-direct.h>
29 int gart_iommu_aperture;
30 int gart_iommu_aperture_disabled __initdata;
31 int gart_iommu_aperture_allowed __initdata;
33 int fallback_aper_order __initdata = 1; /* 64MB */
34 int fallback_aper_force __initdata;
36 int fix_aperture __initdata = 1;
38 struct bus_dev_range {
44 static struct bus_dev_range bus_dev_ranges[] __initdata = {
50 static struct resource gart_resource = {
52 .flags = IORESOURCE_MEM,
55 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
57 gart_resource.start = aper_base;
58 gart_resource.end = aper_base + aper_size - 1;
59 insert_resource(&iomem_resource, &gart_resource);
62 /* This code runs before the PCI subsystem is initialized, so just
63 access the northbridge directly. */
65 static u32 __init allocate_aperture(void)
70 /* aper_size should <= 1G */
71 if (fallback_aper_order > 5)
72 fallback_aper_order = 5;
73 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
76 * Aperture has to be naturally aligned. This means a 2GB aperture
77 * won't have much chance of finding a place in the lower 4GB of
78 * memory. Unfortunately we cannot move it up because that would
79 * make the IOMMU useless.
82 * using 512M as goal, in case kexec will load kernel_big
83 * that will do the on position decompress, and could overlap with
84 * that positon with gart that is used.
87 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
88 * ==> kernel_small(gart area become e820_reserved)
89 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
90 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
91 * so don't use 512M below as gart iommu, leave the space for kernel
94 p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20);
95 if (!p || __pa(p)+aper_size > 0xffffffff) {
97 "Cannot allocate aperture memory hole (%p,%uK)\n",
100 free_bootmem(__pa(p), aper_size);
103 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
104 aper_size >> 10, __pa(p));
105 insert_aperture_resource((u32)__pa(p), aper_size);
106 register_nosave_region((u32)__pa(p) >> PAGE_SHIFT,
107 (u32)__pa(p+aper_size) >> PAGE_SHIFT);
112 static int __init aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
117 if (aper_base + aper_size > 0x100000000UL) {
118 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
121 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
122 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
125 if (aper_size < min_size) {
126 printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
127 aper_size>>20, min_size>>20);
134 /* Find a PCI capability */
135 static __u32 __init find_cap(int bus, int slot, int func, int cap)
140 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
141 PCI_STATUS_CAP_LIST))
144 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
145 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
149 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
154 pos = read_pci_config_byte(bus, slot, func,
155 pos+PCI_CAP_LIST_NEXT);
160 /* Read a standard AGPv3 bridge header */
161 static __u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
166 u32 aper_low, aper_hi;
170 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
171 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
172 if (apsizereg == 0xffffffff) {
173 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
177 /* old_order could be the value from NB gart setting */
180 apsize = apsizereg & 0xfff;
181 /* Some BIOS use weird encodings not in the AGPv3 table. */
184 nbits = hweight16(apsize);
186 if ((int)*order < 0) /* < 32MB */
189 aper_low = read_pci_config(bus, slot, func, 0x10);
190 aper_hi = read_pci_config(bus, slot, func, 0x14);
191 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
194 * On some sick chips, APSIZE is 0. It means it wants 4G
195 * so let double check that order, and lets trust AMD NB settings:
197 printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
198 aper, 32 << old_order);
199 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
200 printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
201 32 << *order, apsizereg);
205 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
206 aper, 32 << *order, apsizereg);
208 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
214 * Look for an AGP bridge. Windows only expects the aperture in the
215 * AGP bridge and some BIOS forget to initialize the Northbridge too.
216 * Work around this here.
218 * Do an PCI bus scan by hand because we're running before the PCI
221 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
222 * generically. It's probably overkill to always scan all slots because
223 * the AGP bridges should be always an own bus on the HT hierarchy,
224 * but do it here for future safety.
226 static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
230 /* Poor man's PCI discovery */
231 for (bus = 0; bus < 256; bus++) {
232 for (slot = 0; slot < 32; slot++) {
233 for (func = 0; func < 8; func++) {
236 class = read_pci_config(bus, slot, func,
238 if (class == 0xffffffff)
241 switch (class >> 16) {
242 case PCI_CLASS_BRIDGE_HOST:
243 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
245 cap = find_cap(bus, slot, func,
250 return read_agp(bus, slot, func, cap,
254 /* No multi-function device? */
255 type = read_pci_config_byte(bus, slot, func,
262 printk(KERN_INFO "No AGP bridge found\n");
267 static int gart_fix_e820 __initdata = 1;
269 static int __init parse_gart_mem(char *p)
274 if (!strncmp(p, "off", 3))
276 else if (!strncmp(p, "on", 2))
281 early_param("gart_fix_e820", parse_gart_mem);
283 void __init early_gart_iommu_check(void)
286 * in case it is enabled before, esp for kexec/kdump,
287 * previous kernel already enable that. memset called
288 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
289 * or second kernel have different position for GART hole. and new
290 * kernel could use hole as RAM that is still used by GART set by
292 * or BIOS forget to put that in reserved.
293 * try to update e820 to make that region as reserved.
297 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
298 u64 aper_base = 0, last_aper_base = 0;
299 int aper_enabled = 0, last_aper_enabled = 0;
302 if (!early_pci_allowed())
306 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
308 int dev_base, dev_limit;
310 bus = bus_dev_ranges[i].bus;
311 dev_base = bus_dev_ranges[i].dev_base;
312 dev_limit = bus_dev_ranges[i].dev_limit;
314 for (slot = dev_base; slot < dev_limit; slot++) {
315 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
318 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
319 aper_enabled = ctl & AMD64_GARTEN;
320 aper_order = (ctl >> 1) & 7;
321 aper_size = (32 * 1024 * 1024) << aper_order;
322 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
325 if ((last_aper_order && aper_order != last_aper_order) ||
326 (last_aper_base && aper_base != last_aper_base) ||
327 (last_aper_enabled && aper_enabled != last_aper_enabled)) {
331 last_aper_order = aper_order;
332 last_aper_base = aper_base;
333 last_aper_enabled = aper_enabled;
338 if (!fix && !aper_enabled)
341 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
344 if (gart_fix_e820 && !fix && aper_enabled) {
345 if (!e820_all_mapped(aper_base, aper_base + aper_size,
347 /* reserved it, so we can resuse it in second kernel */
348 printk(KERN_INFO "update e820 for GART\n");
349 add_memory_region(aper_base, aper_size, E820_RESERVED);
355 /* different nodes have different setting, disable them all at first*/
356 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
358 int dev_base, dev_limit;
360 bus = bus_dev_ranges[i].bus;
361 dev_base = bus_dev_ranges[i].dev_base;
362 dev_limit = bus_dev_ranges[i].dev_limit;
364 for (slot = dev_base; slot < dev_limit; slot++) {
365 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
368 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
369 ctl &= ~AMD64_GARTEN;
370 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
376 static int __initdata printed_gart_size_msg;
378 void __init gart_iommu_hole_init(void)
380 u32 agp_aper_base = 0, agp_aper_order = 0;
381 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
382 u64 aper_base, last_aper_base = 0;
383 int fix, slot, valid_agp = 0;
386 if (gart_iommu_aperture_disabled || !fix_aperture ||
387 !early_pci_allowed())
390 printk(KERN_INFO "Checking aperture...\n");
392 if (!fallback_aper_force)
393 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
397 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
399 int dev_base, dev_limit;
401 bus = bus_dev_ranges[i].bus;
402 dev_base = bus_dev_ranges[i].dev_base;
403 dev_limit = bus_dev_ranges[i].dev_limit;
405 for (slot = dev_base; slot < dev_limit; slot++) {
406 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
410 gart_iommu_aperture = 1;
412 aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
413 aper_size = (32 * 1024 * 1024) << aper_order;
414 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
417 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
418 node, aper_base, aper_size >> 20);
421 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
422 if (valid_agp && agp_aper_base &&
423 agp_aper_base == aper_base &&
424 agp_aper_order == aper_order) {
425 /* the same between two setting from NB and agp */
426 if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
427 printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
428 printk(KERN_ERR "please increase GART size in your BIOS setup\n");
429 printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
430 printed_gart_size_msg = 1;
438 if ((last_aper_order && aper_order != last_aper_order) ||
439 (last_aper_base && aper_base != last_aper_base)) {
443 last_aper_order = aper_order;
444 last_aper_base = aper_base;
449 if (!fix && !fallback_aper_force) {
450 if (last_aper_base) {
451 unsigned long n = (32 * 1024 * 1024) << last_aper_order;
453 insert_aperture_resource((u32)last_aper_base, n);
458 if (!fallback_aper_force) {
459 aper_alloc = agp_aper_base;
460 aper_order = agp_aper_order;
464 /* Got the aperture from the AGP bridge */
465 } else if (swiotlb && !valid_agp) {
467 } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
470 fallback_aper_force) {
472 "Your BIOS doesn't leave a aperture memory hole\n");
474 "Please enable the IOMMU option in the BIOS setup\n");
476 "This costs you %d MB of RAM\n",
477 32 << fallback_aper_order);
479 aper_order = fallback_aper_order;
480 aper_alloc = allocate_aperture();
483 * Could disable AGP and IOMMU here, but it's
484 * probably not worth it. But the later users
485 * cannot deal with bad apertures and turning
486 * on the aperture over memory causes very
487 * strange problems, so it's better to panic
490 panic("Not enough memory for aperture");
496 /* Fix up the north bridges */
497 for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
499 int dev_base, dev_limit;
501 bus = bus_dev_ranges[i].bus;
502 dev_base = bus_dev_ranges[i].dev_base;
503 dev_limit = bus_dev_ranges[i].dev_limit;
504 for (slot = dev_base; slot < dev_limit; slot++) {
505 if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
508 /* Don't enable translation yet. That is done later.
509 Assume this BIOS didn't initialise the GART so
510 just overwrite all previous bits */
511 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
512 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);