2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
33 * definitions for the ACPI scanning code
35 #define IVRS_HEADER_LENGTH 48
37 #define ACPI_IVHD_TYPE 0x10
38 #define ACPI_IVMD_TYPE_ALL 0x20
39 #define ACPI_IVMD_TYPE 0x21
40 #define ACPI_IVMD_TYPE_RANGE 0x22
42 #define IVHD_DEV_ALL 0x01
43 #define IVHD_DEV_SELECT 0x02
44 #define IVHD_DEV_SELECT_RANGE_START 0x03
45 #define IVHD_DEV_RANGE_END 0x04
46 #define IVHD_DEV_ALIAS 0x42
47 #define IVHD_DEV_ALIAS_RANGE 0x43
48 #define IVHD_DEV_EXT_SELECT 0x46
49 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
51 #define IVHD_FLAG_HT_TUN_EN 0x00
52 #define IVHD_FLAG_PASSPW_EN 0x01
53 #define IVHD_FLAG_RESPASSPW_EN 0x02
54 #define IVHD_FLAG_ISOC_EN 0x03
56 #define IVMD_FLAG_EXCL_RANGE 0x08
57 #define IVMD_FLAG_UNITY_MAP 0x01
59 #define ACPI_DEVFLAG_INITPASS 0x01
60 #define ACPI_DEVFLAG_EXTINT 0x02
61 #define ACPI_DEVFLAG_NMI 0x04
62 #define ACPI_DEVFLAG_SYSMGT1 0x10
63 #define ACPI_DEVFLAG_SYSMGT2 0x20
64 #define ACPI_DEVFLAG_LINT0 0x40
65 #define ACPI_DEVFLAG_LINT1 0x80
66 #define ACPI_DEVFLAG_ATSDIS 0x10000000
69 * ACPI table definitions
71 * These data structures are laid over the table to parse the important values
76 * structure describing one IOMMU in the ACPI table. Typically followed by one
77 * or more ivhd_entrys.
89 } __attribute__((packed));
92 * A device entry describing which devices a specific IOMMU translates and
93 * which requestor ids they use.
100 } __attribute__((packed));
103 * An AMD IOMMU memory definition structure. It defines things like exclusion
104 * ranges for devices and regions that should be unity mapped.
115 } __attribute__((packed));
117 static int __initdata amd_iommu_detected;
119 u16 amd_iommu_last_bdf; /* largest PCI device id we have
121 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
123 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
124 int amd_iommu_isolate; /* if 1, device isolation is enabled */
126 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
130 * Pointer to the device table which is shared by all AMD IOMMUs
131 * it is indexed by the PCI device id or the HT unit id and contains
132 * information about the domain the device belongs to as well as the
133 * page table root pointer.
135 struct dev_table_entry *amd_iommu_dev_table;
138 * The alias table is a driver specific data structure which contains the
139 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
140 * More than one device can share the same requestor id.
142 u16 *amd_iommu_alias_table;
145 * The rlookup table is used to find the IOMMU which is responsible
146 * for a specific device. It is also indexed by the PCI device id.
148 struct amd_iommu **amd_iommu_rlookup_table;
151 * The pd table (protection domain table) is used to find the protection domain
152 * data structure a device belongs to. Indexed with the PCI device id too.
154 struct protection_domain **amd_iommu_pd_table;
157 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
158 * to know which ones are already in use.
160 unsigned long *amd_iommu_pd_alloc_bitmap;
162 static u32 dev_table_size; /* size of the device table */
163 static u32 alias_table_size; /* size of the alias table */
164 static u32 rlookup_table_size; /* size if the rlookup table */
166 static inline void update_last_devid(u16 devid)
168 if (devid > amd_iommu_last_bdf)
169 amd_iommu_last_bdf = devid;
172 static inline unsigned long tbl_size(int entry_size)
174 unsigned shift = PAGE_SHIFT +
175 get_order(amd_iommu_last_bdf * entry_size);
180 /****************************************************************************
182 * AMD IOMMU MMIO register space handling functions
184 * These functions are used to program the IOMMU device registers in
185 * MMIO space required for that driver.
187 ****************************************************************************/
190 * This function set the exclusion range in the IOMMU. DMA accesses to the
191 * exclusion range are passed through untranslated
193 static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
195 u64 start = iommu->exclusion_start & PAGE_MASK;
196 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
199 if (!iommu->exclusion_start)
202 entry = start | MMIO_EXCL_ENABLE_MASK;
203 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
204 &entry, sizeof(entry));
207 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
208 &entry, sizeof(entry));
211 /* Programs the physical address of the device table into the IOMMU hardware */
212 static void __init iommu_set_device_table(struct amd_iommu *iommu)
216 BUG_ON(iommu->mmio_base == NULL);
218 entry = virt_to_phys(amd_iommu_dev_table);
219 entry |= (dev_table_size >> 12) - 1;
220 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
221 &entry, sizeof(entry));
224 /* Generic functions to enable/disable certain features of the IOMMU. */
225 static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
229 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
231 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
234 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
238 ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
243 /* Function to enable the hardware */
244 void __init iommu_enable(struct amd_iommu *iommu)
246 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU "
247 "at %02x:%02x.%x cap 0x%hx\n",
248 iommu->dev->bus->number,
249 PCI_SLOT(iommu->dev->devfn),
250 PCI_FUNC(iommu->dev->devfn),
253 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
257 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
258 * the system has one.
260 static u8 * __init iommu_map_mmio_space(u64 address)
264 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
267 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
271 release_mem_region(address, MMIO_REGION_LENGTH);
276 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
278 if (iommu->mmio_base)
279 iounmap(iommu->mmio_base);
280 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
283 /****************************************************************************
285 * The functions below belong to the first pass of AMD IOMMU ACPI table
286 * parsing. In this pass we try to find out the highest device id this
287 * code has to handle. Upon this information the size of the shared data
288 * structures is determined later.
290 ****************************************************************************/
293 * This function reads the last device id the IOMMU has to handle from the PCI
294 * capability header for this IOMMU
296 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
300 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
301 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
307 * After reading the highest device id from the IOMMU PCI capability header
308 * this function looks if there is a higher device id defined in the ACPI table
310 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
312 u8 *p = (void *)h, *end = (void *)h;
313 struct ivhd_entry *dev;
318 find_last_devid_on_pci(PCI_BUS(h->devid),
324 dev = (struct ivhd_entry *)p;
326 case IVHD_DEV_SELECT:
327 case IVHD_DEV_RANGE_END:
329 case IVHD_DEV_EXT_SELECT:
330 /* all the above subfield types refer to device ids */
331 update_last_devid(dev->devid);
336 p += 0x04 << (*p >> 6);
345 * Iterate over all IVHD entries in the ACPI table and find the highest device
346 * id which we need to handle. This is the first of three functions which parse
347 * the ACPI table. So we check the checksum here.
349 static int __init find_last_devid_acpi(struct acpi_table_header *table)
352 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
353 struct ivhd_header *h;
356 * Validate checksum here so we don't need to do it when
357 * we actually parse the table
359 for (i = 0; i < table->length; ++i)
362 /* ACPI table corrupt */
365 p += IVRS_HEADER_LENGTH;
367 end += table->length;
369 h = (struct ivhd_header *)p;
372 find_last_devid_from_ivhd(h);
384 /****************************************************************************
386 * The following functions belong the the code path which parses the ACPI table
387 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
388 * data structures, initialize the device/alias/rlookup table and also
389 * basically initialize the hardware.
391 ****************************************************************************/
394 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
395 * write commands to that buffer later and the IOMMU will execute them
398 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
400 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
401 get_order(CMD_BUFFER_SIZE));
407 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
409 entry = (u64)virt_to_phys(cmd_buf);
410 entry |= MMIO_CMD_SIZE_512;
411 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
412 &entry, sizeof(entry));
414 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
419 static void __init free_command_buffer(struct amd_iommu *iommu)
421 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
424 /* allocates the memory where the IOMMU will log its events to */
425 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
428 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
429 get_order(EVT_BUFFER_SIZE));
431 if (iommu->evt_buf == NULL)
434 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
435 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
436 &entry, sizeof(entry));
438 iommu->evt_buf_size = EVT_BUFFER_SIZE;
440 return iommu->evt_buf;
443 static void __init free_event_buffer(struct amd_iommu *iommu)
445 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
448 /* sets a specific bit in the device table entry. */
449 static void set_dev_entry_bit(u16 devid, u8 bit)
451 int i = (bit >> 5) & 0x07;
452 int _bit = bit & 0x1f;
454 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
457 /* Writes the specific IOMMU for a device into the rlookup table */
458 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
460 amd_iommu_rlookup_table[devid] = iommu;
464 * This function takes the device specific flags read from the ACPI
465 * table and sets up the device table entry with that information
467 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
468 u16 devid, u32 flags, u32 ext_flags)
470 if (flags & ACPI_DEVFLAG_INITPASS)
471 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
472 if (flags & ACPI_DEVFLAG_EXTINT)
473 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
474 if (flags & ACPI_DEVFLAG_NMI)
475 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
476 if (flags & ACPI_DEVFLAG_SYSMGT1)
477 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
478 if (flags & ACPI_DEVFLAG_SYSMGT2)
479 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
480 if (flags & ACPI_DEVFLAG_LINT0)
481 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
482 if (flags & ACPI_DEVFLAG_LINT1)
483 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
485 set_iommu_for_device(iommu, devid);
489 * Reads the device exclusion range from ACPI and initialize IOMMU with
492 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
494 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
496 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
501 * We only can configure exclusion ranges per IOMMU, not
502 * per device. But we can enable the exclusion range per
503 * device. This is done here
505 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
506 iommu->exclusion_start = m->range_start;
507 iommu->exclusion_length = m->range_length;
512 * This function reads some important data from the IOMMU PCI space and
513 * initializes the driver data structure with it. It reads the hardware
514 * capabilities and the first/last device entries
516 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
518 int cap_ptr = iommu->cap_ptr;
521 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
523 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
525 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
528 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
530 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
532 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
536 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
537 * initializes the hardware and our data structures with it.
539 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
540 struct ivhd_header *h)
543 u8 *end = p, flags = 0;
544 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
547 struct ivhd_entry *e;
550 * First set the recommended feature enable bits from ACPI
551 * into the IOMMU control registers
553 h->flags & IVHD_FLAG_HT_TUN_EN ?
554 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
555 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
557 h->flags & IVHD_FLAG_PASSPW_EN ?
558 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
559 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
561 h->flags & IVHD_FLAG_RESPASSPW_EN ?
562 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
563 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
565 h->flags & IVHD_FLAG_ISOC_EN ?
566 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
567 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
570 * make IOMMU memory accesses cache coherent
572 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
575 * Done. Now parse the device entries
577 p += sizeof(struct ivhd_header);
581 e = (struct ivhd_entry *)p;
584 for (dev_i = iommu->first_device;
585 dev_i <= iommu->last_device; ++dev_i)
586 set_dev_entry_from_acpi(iommu, dev_i,
589 case IVHD_DEV_SELECT:
591 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
593 case IVHD_DEV_SELECT_RANGE_START:
594 devid_start = e->devid;
601 devid_to = e->ext >> 8;
602 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
603 amd_iommu_alias_table[devid] = devid_to;
605 case IVHD_DEV_ALIAS_RANGE:
606 devid_start = e->devid;
608 devid_to = e->ext >> 8;
612 case IVHD_DEV_EXT_SELECT:
614 set_dev_entry_from_acpi(iommu, devid, e->flags,
617 case IVHD_DEV_EXT_SELECT_RANGE:
618 devid_start = e->devid;
623 case IVHD_DEV_RANGE_END:
625 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
627 amd_iommu_alias_table[dev_i] = devid_to;
628 set_dev_entry_from_acpi(iommu,
629 amd_iommu_alias_table[dev_i],
637 p += 0x04 << (e->type >> 6);
641 /* Initializes the device->iommu mapping for the driver */
642 static int __init init_iommu_devices(struct amd_iommu *iommu)
646 for (i = iommu->first_device; i <= iommu->last_device; ++i)
647 set_iommu_for_device(iommu, i);
652 static void __init free_iommu_one(struct amd_iommu *iommu)
654 free_command_buffer(iommu);
655 free_event_buffer(iommu);
656 iommu_unmap_mmio_space(iommu);
659 static void __init free_iommu_all(void)
661 struct amd_iommu *iommu, *next;
663 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
664 list_del(&iommu->list);
665 free_iommu_one(iommu);
671 * This function clues the initialization function for one IOMMU
672 * together and also allocates the command buffer and programs the
673 * hardware. It does NOT enable the IOMMU. This is done afterwards.
675 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
677 spin_lock_init(&iommu->lock);
678 list_add_tail(&iommu->list, &amd_iommu_list);
681 * Copy data from ACPI table entry to the iommu struct
683 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
687 iommu->cap_ptr = h->cap_ptr;
688 iommu->pci_seg = h->pci_seg;
689 iommu->mmio_phys = h->mmio_phys;
690 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
691 if (!iommu->mmio_base)
694 iommu_set_device_table(iommu);
695 iommu->cmd_buf = alloc_command_buffer(iommu);
699 iommu->evt_buf = alloc_event_buffer(iommu);
703 iommu->int_enabled = false;
705 init_iommu_from_pci(iommu);
706 init_iommu_from_acpi(iommu, h);
707 init_iommu_devices(iommu);
709 pci_enable_device(iommu->dev);
715 * Iterates over all IOMMU entries in the ACPI table, allocates the
716 * IOMMU structure and initializes it with init_iommu_one()
718 static int __init init_iommu_all(struct acpi_table_header *table)
720 u8 *p = (u8 *)table, *end = (u8 *)table;
721 struct ivhd_header *h;
722 struct amd_iommu *iommu;
725 end += table->length;
726 p += IVRS_HEADER_LENGTH;
729 h = (struct ivhd_header *)p;
732 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
735 ret = init_iommu_one(iommu, h);
750 /****************************************************************************
752 * The following functions initialize the MSI interrupts for all IOMMUs
753 * in the system. Its a bit challenging because there could be multiple
754 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
757 ****************************************************************************/
759 static int __init iommu_setup_msix(struct amd_iommu *iommu)
761 struct amd_iommu *curr;
762 struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
765 list_for_each_entry(curr, &amd_iommu_list, list) {
766 if (curr->dev == iommu->dev) {
767 entries[nvec].entry = curr->evt_msi_num;
768 entries[nvec].vector = 0;
769 curr->int_enabled = true;
774 if (pci_enable_msix(iommu->dev, entries, nvec)) {
775 pci_disable_msix(iommu->dev);
779 for (i = 0; i < nvec; ++i) {
780 int r = request_irq(entries->vector, amd_iommu_int_handler,
791 for (i -= 1; i >= 0; --i)
792 free_irq(entries->vector, NULL);
794 pci_disable_msix(iommu->dev);
799 static int __init iommu_setup_msi(struct amd_iommu *iommu)
802 struct amd_iommu *curr;
804 list_for_each_entry(curr, &amd_iommu_list, list) {
805 if (curr->dev == iommu->dev)
806 curr->int_enabled = true;
810 if (pci_enable_msi(iommu->dev))
813 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
819 pci_disable_msi(iommu->dev);
826 static int __init iommu_init_msi(struct amd_iommu *iommu)
828 if (iommu->int_enabled)
831 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX))
832 return iommu_setup_msix(iommu);
833 else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
834 return iommu_setup_msi(iommu);
839 /****************************************************************************
841 * The next functions belong to the third pass of parsing the ACPI
842 * table. In this last pass the memory mapping requirements are
843 * gathered (like exclusion and unity mapping reanges).
845 ****************************************************************************/
847 static void __init free_unity_maps(void)
849 struct unity_map_entry *entry, *next;
851 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
852 list_del(&entry->list);
857 /* called when we find an exclusion range definition in ACPI */
858 static int __init init_exclusion_range(struct ivmd_header *m)
864 set_device_exclusion_range(m->devid, m);
866 case ACPI_IVMD_TYPE_ALL:
867 for (i = 0; i <= amd_iommu_last_bdf; ++i)
868 set_device_exclusion_range(i, m);
870 case ACPI_IVMD_TYPE_RANGE:
871 for (i = m->devid; i <= m->aux; ++i)
872 set_device_exclusion_range(i, m);
881 /* called for unity map ACPI definition */
882 static int __init init_unity_map_range(struct ivmd_header *m)
884 struct unity_map_entry *e = 0;
886 e = kzalloc(sizeof(*e), GFP_KERNEL);
893 e->devid_start = e->devid_end = m->devid;
895 case ACPI_IVMD_TYPE_ALL:
897 e->devid_end = amd_iommu_last_bdf;
899 case ACPI_IVMD_TYPE_RANGE:
900 e->devid_start = m->devid;
901 e->devid_end = m->aux;
904 e->address_start = PAGE_ALIGN(m->range_start);
905 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
906 e->prot = m->flags >> 1;
908 list_add_tail(&e->list, &amd_iommu_unity_map);
913 /* iterates over all memory definitions we find in the ACPI table */
914 static int __init init_memory_definitions(struct acpi_table_header *table)
916 u8 *p = (u8 *)table, *end = (u8 *)table;
917 struct ivmd_header *m;
919 end += table->length;
920 p += IVRS_HEADER_LENGTH;
923 m = (struct ivmd_header *)p;
924 if (m->flags & IVMD_FLAG_EXCL_RANGE)
925 init_exclusion_range(m);
926 else if (m->flags & IVMD_FLAG_UNITY_MAP)
927 init_unity_map_range(m);
936 * Init the device table to not allow DMA access for devices and
937 * suppress all page faults
939 static void init_device_table(void)
943 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
944 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
945 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
946 set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
951 * This function finally enables all IOMMUs found in the system after
952 * they have been initialized
954 static void __init enable_iommus(void)
956 struct amd_iommu *iommu;
958 list_for_each_entry(iommu, &amd_iommu_list, list) {
959 iommu_set_exclusion_range(iommu);
960 iommu_init_msi(iommu);
966 * Suspend/Resume support
967 * disable suspend until real resume implemented
970 static int amd_iommu_resume(struct sys_device *dev)
975 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
980 static struct sysdev_class amd_iommu_sysdev_class = {
982 .suspend = amd_iommu_suspend,
983 .resume = amd_iommu_resume,
986 static struct sys_device device_amd_iommu = {
988 .cls = &amd_iommu_sysdev_class,
992 * This is the core init function for AMD IOMMU hardware in the system.
993 * This function is called from the generic x86 DMA layer initialization
996 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
999 * 1 pass) Find the highest PCI device id the driver has to handle.
1000 * Upon this information the size of the data structures is
1001 * determined that needs to be allocated.
1003 * 2 pass) Initialize the data structures just allocated with the
1004 * information in the ACPI table about available AMD IOMMUs
1005 * in the system. It also maps the PCI devices in the
1006 * system to specific IOMMUs
1008 * 3 pass) After the basic data structures are allocated and
1009 * initialized we update them with information about memory
1010 * remapping requirements parsed out of the ACPI table in
1013 * After that the hardware is initialized and ready to go. In the last
1014 * step we do some Linux specific things like registering the driver in
1015 * the dma_ops interface and initializing the suspend/resume support
1016 * functions. Finally it prints some information about AMD IOMMUs and
1017 * the driver state and enables the hardware.
1019 int __init amd_iommu_init(void)
1025 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1029 if (!amd_iommu_detected)
1033 * First parse ACPI tables to find the largest Bus/Dev/Func
1034 * we need to handle. Upon this information the shared data
1035 * structures for the IOMMUs in the system will be allocated
1037 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1040 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1041 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1042 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1046 /* Device table - directly used by all IOMMUs */
1047 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1048 get_order(dev_table_size));
1049 if (amd_iommu_dev_table == NULL)
1053 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1054 * IOMMU see for that device
1056 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1057 get_order(alias_table_size));
1058 if (amd_iommu_alias_table == NULL)
1061 /* IOMMU rlookup table - find the IOMMU for a specific device */
1062 amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
1063 get_order(rlookup_table_size));
1064 if (amd_iommu_rlookup_table == NULL)
1068 * Protection Domain table - maps devices to protection domains
1069 * This table has the same size as the rlookup_table
1071 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1072 get_order(rlookup_table_size));
1073 if (amd_iommu_pd_table == NULL)
1076 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1077 GFP_KERNEL | __GFP_ZERO,
1078 get_order(MAX_DOMAIN_ID/8));
1079 if (amd_iommu_pd_alloc_bitmap == NULL)
1082 /* init the device table */
1083 init_device_table();
1086 * let all alias entries point to itself
1088 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1089 amd_iommu_alias_table[i] = i;
1092 * never allocate domain 0 because its used as the non-allocated and
1093 * error value placeholder
1095 amd_iommu_pd_alloc_bitmap[0] = 1;
1098 * now the data structures are allocated and basically initialized
1099 * start the real acpi table scan
1102 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1105 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1108 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1112 ret = sysdev_register(&device_amd_iommu);
1116 ret = amd_iommu_init_dma_ops();
1122 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
1123 (1 << (amd_iommu_aperture_order-20)));
1125 printk(KERN_INFO "AMD IOMMU: device isolation ");
1126 if (amd_iommu_isolate)
1127 printk("enabled\n");
1129 printk("disabled\n");
1131 if (iommu_fullflush)
1132 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1134 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1140 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
1142 free_pages((unsigned long)amd_iommu_pd_table,
1143 get_order(rlookup_table_size));
1145 free_pages((unsigned long)amd_iommu_rlookup_table,
1146 get_order(rlookup_table_size));
1148 free_pages((unsigned long)amd_iommu_alias_table,
1149 get_order(alias_table_size));
1151 free_pages((unsigned long)amd_iommu_dev_table,
1152 get_order(dev_table_size));
1161 /****************************************************************************
1163 * Early detect code. This code runs at IOMMU detection time in the DMA
1164 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1167 ****************************************************************************/
1168 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1173 void __init amd_iommu_detect(void)
1175 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1178 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1180 amd_iommu_detected = 1;
1181 #ifdef CONFIG_GART_IOMMU
1182 gart_iommu_aperture_disabled = 1;
1183 gart_iommu_aperture = 0;
1188 /****************************************************************************
1190 * Parsing functions for the AMD IOMMU specific kernel command line
1193 ****************************************************************************/
1195 static int __init parse_amd_iommu_options(char *str)
1197 for (; *str; ++str) {
1198 if (strncmp(str, "isolate", 7) == 0)
1199 amd_iommu_isolate = 1;
1205 static int __init parse_amd_iommu_size_options(char *str)
1207 unsigned order = PAGE_SHIFT + get_order(memparse(str, &str));
1209 if ((order > 24) && (order < 31))
1210 amd_iommu_aperture_order = order;
1215 __setup("amd_iommu=", parse_amd_iommu_options);
1216 __setup("amd_iommu_size=", parse_amd_iommu_size_options);