2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
33 * definitions for the ACPI scanning code
35 #define IVRS_HEADER_LENGTH 48
37 #define ACPI_IVHD_TYPE 0x10
38 #define ACPI_IVMD_TYPE_ALL 0x20
39 #define ACPI_IVMD_TYPE 0x21
40 #define ACPI_IVMD_TYPE_RANGE 0x22
42 #define IVHD_DEV_ALL 0x01
43 #define IVHD_DEV_SELECT 0x02
44 #define IVHD_DEV_SELECT_RANGE_START 0x03
45 #define IVHD_DEV_RANGE_END 0x04
46 #define IVHD_DEV_ALIAS 0x42
47 #define IVHD_DEV_ALIAS_RANGE 0x43
48 #define IVHD_DEV_EXT_SELECT 0x46
49 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
51 #define IVHD_FLAG_HT_TUN_EN 0x00
52 #define IVHD_FLAG_PASSPW_EN 0x01
53 #define IVHD_FLAG_RESPASSPW_EN 0x02
54 #define IVHD_FLAG_ISOC_EN 0x03
56 #define IVMD_FLAG_EXCL_RANGE 0x08
57 #define IVMD_FLAG_UNITY_MAP 0x01
59 #define ACPI_DEVFLAG_INITPASS 0x01
60 #define ACPI_DEVFLAG_EXTINT 0x02
61 #define ACPI_DEVFLAG_NMI 0x04
62 #define ACPI_DEVFLAG_SYSMGT1 0x10
63 #define ACPI_DEVFLAG_SYSMGT2 0x20
64 #define ACPI_DEVFLAG_LINT0 0x40
65 #define ACPI_DEVFLAG_LINT1 0x80
66 #define ACPI_DEVFLAG_ATSDIS 0x10000000
69 * ACPI table definitions
71 * These data structures are laid over the table to parse the important values
76 * structure describing one IOMMU in the ACPI table. Typically followed by one
77 * or more ivhd_entrys.
89 } __attribute__((packed));
92 * A device entry describing which devices a specific IOMMU translates and
93 * which requestor ids they use.
100 } __attribute__((packed));
103 * An AMD IOMMU memory definition structure. It defines things like exclusion
104 * ranges for devices and regions that should be unity mapped.
115 } __attribute__((packed));
117 static int __initdata amd_iommu_detected;
119 u16 amd_iommu_last_bdf; /* largest PCI device id we have
121 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
123 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
124 int amd_iommu_isolate; /* if 1, device isolation is enabled */
126 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
130 * Pointer to the device table which is shared by all AMD IOMMUs
131 * it is indexed by the PCI device id or the HT unit id and contains
132 * information about the domain the device belongs to as well as the
133 * page table root pointer.
135 struct dev_table_entry *amd_iommu_dev_table;
138 * The alias table is a driver specific data structure which contains the
139 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
140 * More than one device can share the same requestor id.
142 u16 *amd_iommu_alias_table;
145 * The rlookup table is used to find the IOMMU which is responsible
146 * for a specific device. It is also indexed by the PCI device id.
148 struct amd_iommu **amd_iommu_rlookup_table;
151 * The pd table (protection domain table) is used to find the protection domain
152 * data structure a device belongs to. Indexed with the PCI device id too.
154 struct protection_domain **amd_iommu_pd_table;
157 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
158 * to know which ones are already in use.
160 unsigned long *amd_iommu_pd_alloc_bitmap;
162 static u32 dev_table_size; /* size of the device table */
163 static u32 alias_table_size; /* size of the alias table */
164 static u32 rlookup_table_size; /* size if the rlookup table */
166 static inline void update_last_devid(u16 devid)
168 if (devid > amd_iommu_last_bdf)
169 amd_iommu_last_bdf = devid;
172 static inline unsigned long tbl_size(int entry_size)
174 unsigned shift = PAGE_SHIFT +
175 get_order(amd_iommu_last_bdf * entry_size);
180 /****************************************************************************
182 * AMD IOMMU MMIO register space handling functions
184 * These functions are used to program the IOMMU device registers in
185 * MMIO space required for that driver.
187 ****************************************************************************/
190 * This function set the exclusion range in the IOMMU. DMA accesses to the
191 * exclusion range are passed through untranslated
193 static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
195 u64 start = iommu->exclusion_start & PAGE_MASK;
196 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
199 if (!iommu->exclusion_start)
202 entry = start | MMIO_EXCL_ENABLE_MASK;
203 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
204 &entry, sizeof(entry));
207 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
208 &entry, sizeof(entry));
211 /* Programs the physical address of the device table into the IOMMU hardware */
212 static void __init iommu_set_device_table(struct amd_iommu *iommu)
216 BUG_ON(iommu->mmio_base == NULL);
218 entry = virt_to_phys(amd_iommu_dev_table);
219 entry |= (dev_table_size >> 12) - 1;
220 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
221 &entry, sizeof(entry));
224 /* Generic functions to enable/disable certain features of the IOMMU. */
225 static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
229 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
231 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
234 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
238 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
243 /* Function to enable the hardware */
244 void __init iommu_enable(struct amd_iommu *iommu)
246 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU "
247 "at %02x:%02x.%x cap 0x%hx\n",
248 iommu->dev->bus->number,
249 PCI_SLOT(iommu->dev->devfn),
250 PCI_FUNC(iommu->dev->devfn),
253 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
256 /* Function to enable IOMMU event logging and event interrupts */
257 void __init iommu_enable_event_logging(struct amd_iommu *iommu)
259 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
260 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
264 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
265 * the system has one.
267 static u8 * __init iommu_map_mmio_space(u64 address)
271 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
274 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
278 release_mem_region(address, MMIO_REGION_LENGTH);
283 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
285 if (iommu->mmio_base)
286 iounmap(iommu->mmio_base);
287 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
290 /****************************************************************************
292 * The functions below belong to the first pass of AMD IOMMU ACPI table
293 * parsing. In this pass we try to find out the highest device id this
294 * code has to handle. Upon this information the size of the shared data
295 * structures is determined later.
297 ****************************************************************************/
300 * This function calculates the length of a given IVHD entry
302 static inline int ivhd_entry_length(u8 *ivhd)
304 return 0x04 << (*ivhd >> 6);
308 * This function reads the last device id the IOMMU has to handle from the PCI
309 * capability header for this IOMMU
311 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
315 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
316 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
322 * After reading the highest device id from the IOMMU PCI capability header
323 * this function looks if there is a higher device id defined in the ACPI table
325 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
327 u8 *p = (void *)h, *end = (void *)h;
328 struct ivhd_entry *dev;
333 find_last_devid_on_pci(PCI_BUS(h->devid),
339 dev = (struct ivhd_entry *)p;
341 case IVHD_DEV_SELECT:
342 case IVHD_DEV_RANGE_END:
344 case IVHD_DEV_EXT_SELECT:
345 /* all the above subfield types refer to device ids */
346 update_last_devid(dev->devid);
351 p += ivhd_entry_length(p);
360 * Iterate over all IVHD entries in the ACPI table and find the highest device
361 * id which we need to handle. This is the first of three functions which parse
362 * the ACPI table. So we check the checksum here.
364 static int __init find_last_devid_acpi(struct acpi_table_header *table)
367 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
368 struct ivhd_header *h;
371 * Validate checksum here so we don't need to do it when
372 * we actually parse the table
374 for (i = 0; i < table->length; ++i)
377 /* ACPI table corrupt */
380 p += IVRS_HEADER_LENGTH;
382 end += table->length;
384 h = (struct ivhd_header *)p;
387 find_last_devid_from_ivhd(h);
399 /****************************************************************************
401 * The following functions belong the the code path which parses the ACPI table
402 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
403 * data structures, initialize the device/alias/rlookup table and also
404 * basically initialize the hardware.
406 ****************************************************************************/
409 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
410 * write commands to that buffer later and the IOMMU will execute them
413 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
415 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
416 get_order(CMD_BUFFER_SIZE));
422 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
424 entry = (u64)virt_to_phys(cmd_buf);
425 entry |= MMIO_CMD_SIZE_512;
426 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
427 &entry, sizeof(entry));
429 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
434 static void __init free_command_buffer(struct amd_iommu *iommu)
436 free_pages((unsigned long)iommu->cmd_buf,
437 get_order(iommu->cmd_buf_size));
440 /* allocates the memory where the IOMMU will log its events to */
441 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
444 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
445 get_order(EVT_BUFFER_SIZE));
447 if (iommu->evt_buf == NULL)
450 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
451 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
452 &entry, sizeof(entry));
454 iommu->evt_buf_size = EVT_BUFFER_SIZE;
456 return iommu->evt_buf;
459 static void __init free_event_buffer(struct amd_iommu *iommu)
461 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
464 /* sets a specific bit in the device table entry. */
465 static void set_dev_entry_bit(u16 devid, u8 bit)
467 int i = (bit >> 5) & 0x07;
468 int _bit = bit & 0x1f;
470 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
473 /* Writes the specific IOMMU for a device into the rlookup table */
474 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
476 amd_iommu_rlookup_table[devid] = iommu;
480 * This function takes the device specific flags read from the ACPI
481 * table and sets up the device table entry with that information
483 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
484 u16 devid, u32 flags, u32 ext_flags)
486 if (flags & ACPI_DEVFLAG_INITPASS)
487 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
488 if (flags & ACPI_DEVFLAG_EXTINT)
489 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
490 if (flags & ACPI_DEVFLAG_NMI)
491 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
492 if (flags & ACPI_DEVFLAG_SYSMGT1)
493 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
494 if (flags & ACPI_DEVFLAG_SYSMGT2)
495 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
496 if (flags & ACPI_DEVFLAG_LINT0)
497 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
498 if (flags & ACPI_DEVFLAG_LINT1)
499 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
501 set_iommu_for_device(iommu, devid);
505 * Reads the device exclusion range from ACPI and initialize IOMMU with
508 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
510 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
512 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
517 * We only can configure exclusion ranges per IOMMU, not
518 * per device. But we can enable the exclusion range per
519 * device. This is done here
521 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
522 iommu->exclusion_start = m->range_start;
523 iommu->exclusion_length = m->range_length;
528 * This function reads some important data from the IOMMU PCI space and
529 * initializes the driver data structure with it. It reads the hardware
530 * capabilities and the first/last device entries
532 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
534 int cap_ptr = iommu->cap_ptr;
537 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
539 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
541 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
544 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
546 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
548 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
552 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
553 * initializes the hardware and our data structures with it.
555 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
556 struct ivhd_header *h)
559 u8 *end = p, flags = 0;
560 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
563 struct ivhd_entry *e;
566 * First set the recommended feature enable bits from ACPI
567 * into the IOMMU control registers
569 h->flags & IVHD_FLAG_HT_TUN_EN ?
570 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
571 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
573 h->flags & IVHD_FLAG_PASSPW_EN ?
574 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
575 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
577 h->flags & IVHD_FLAG_RESPASSPW_EN ?
578 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
579 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
581 h->flags & IVHD_FLAG_ISOC_EN ?
582 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
583 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
586 * make IOMMU memory accesses cache coherent
588 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
591 * Done. Now parse the device entries
593 p += sizeof(struct ivhd_header);
597 e = (struct ivhd_entry *)p;
600 for (dev_i = iommu->first_device;
601 dev_i <= iommu->last_device; ++dev_i)
602 set_dev_entry_from_acpi(iommu, dev_i,
605 case IVHD_DEV_SELECT:
607 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
609 case IVHD_DEV_SELECT_RANGE_START:
610 devid_start = e->devid;
617 devid_to = e->ext >> 8;
618 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
619 amd_iommu_alias_table[devid] = devid_to;
621 case IVHD_DEV_ALIAS_RANGE:
622 devid_start = e->devid;
624 devid_to = e->ext >> 8;
628 case IVHD_DEV_EXT_SELECT:
630 set_dev_entry_from_acpi(iommu, devid, e->flags,
633 case IVHD_DEV_EXT_SELECT_RANGE:
634 devid_start = e->devid;
639 case IVHD_DEV_RANGE_END:
641 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
643 amd_iommu_alias_table[dev_i] = devid_to;
644 set_dev_entry_from_acpi(iommu,
645 amd_iommu_alias_table[dev_i],
653 p += ivhd_entry_length(p);
657 /* Initializes the device->iommu mapping for the driver */
658 static int __init init_iommu_devices(struct amd_iommu *iommu)
662 for (i = iommu->first_device; i <= iommu->last_device; ++i)
663 set_iommu_for_device(iommu, i);
668 static void __init free_iommu_one(struct amd_iommu *iommu)
670 free_command_buffer(iommu);
671 free_event_buffer(iommu);
672 iommu_unmap_mmio_space(iommu);
675 static void __init free_iommu_all(void)
677 struct amd_iommu *iommu, *next;
679 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
680 list_del(&iommu->list);
681 free_iommu_one(iommu);
687 * This function clues the initialization function for one IOMMU
688 * together and also allocates the command buffer and programs the
689 * hardware. It does NOT enable the IOMMU. This is done afterwards.
691 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
693 spin_lock_init(&iommu->lock);
694 list_add_tail(&iommu->list, &amd_iommu_list);
697 * Copy data from ACPI table entry to the iommu struct
699 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
703 iommu->cap_ptr = h->cap_ptr;
704 iommu->pci_seg = h->pci_seg;
705 iommu->mmio_phys = h->mmio_phys;
706 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
707 if (!iommu->mmio_base)
710 iommu_set_device_table(iommu);
711 iommu->cmd_buf = alloc_command_buffer(iommu);
715 iommu->evt_buf = alloc_event_buffer(iommu);
719 iommu->int_enabled = false;
721 init_iommu_from_pci(iommu);
722 init_iommu_from_acpi(iommu, h);
723 init_iommu_devices(iommu);
725 pci_enable_device(iommu->dev);
731 * Iterates over all IOMMU entries in the ACPI table, allocates the
732 * IOMMU structure and initializes it with init_iommu_one()
734 static int __init init_iommu_all(struct acpi_table_header *table)
736 u8 *p = (u8 *)table, *end = (u8 *)table;
737 struct ivhd_header *h;
738 struct amd_iommu *iommu;
741 end += table->length;
742 p += IVRS_HEADER_LENGTH;
745 h = (struct ivhd_header *)p;
748 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
751 ret = init_iommu_one(iommu, h);
766 /****************************************************************************
768 * The following functions initialize the MSI interrupts for all IOMMUs
769 * in the system. Its a bit challenging because there could be multiple
770 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
773 ****************************************************************************/
775 static int __init iommu_setup_msix(struct amd_iommu *iommu)
777 struct amd_iommu *curr;
778 struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
781 list_for_each_entry(curr, &amd_iommu_list, list) {
782 if (curr->dev == iommu->dev) {
783 entries[nvec].entry = curr->evt_msi_num;
784 entries[nvec].vector = 0;
785 curr->int_enabled = true;
790 if (pci_enable_msix(iommu->dev, entries, nvec)) {
791 pci_disable_msix(iommu->dev);
795 for (i = 0; i < nvec; ++i) {
796 int r = request_irq(entries->vector, amd_iommu_int_handler,
807 for (i -= 1; i >= 0; --i)
808 free_irq(entries->vector, NULL);
810 pci_disable_msix(iommu->dev);
815 static int __init iommu_setup_msi(struct amd_iommu *iommu)
818 struct amd_iommu *curr;
820 list_for_each_entry(curr, &amd_iommu_list, list) {
821 if (curr->dev == iommu->dev)
822 curr->int_enabled = true;
826 if (pci_enable_msi(iommu->dev))
829 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
835 pci_disable_msi(iommu->dev);
842 static int __init iommu_init_msi(struct amd_iommu *iommu)
844 if (iommu->int_enabled)
847 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX))
848 return iommu_setup_msix(iommu);
849 else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
850 return iommu_setup_msi(iommu);
855 /****************************************************************************
857 * The next functions belong to the third pass of parsing the ACPI
858 * table. In this last pass the memory mapping requirements are
859 * gathered (like exclusion and unity mapping reanges).
861 ****************************************************************************/
863 static void __init free_unity_maps(void)
865 struct unity_map_entry *entry, *next;
867 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
868 list_del(&entry->list);
873 /* called when we find an exclusion range definition in ACPI */
874 static int __init init_exclusion_range(struct ivmd_header *m)
880 set_device_exclusion_range(m->devid, m);
882 case ACPI_IVMD_TYPE_ALL:
883 for (i = 0; i <= amd_iommu_last_bdf; ++i)
884 set_device_exclusion_range(i, m);
886 case ACPI_IVMD_TYPE_RANGE:
887 for (i = m->devid; i <= m->aux; ++i)
888 set_device_exclusion_range(i, m);
897 /* called for unity map ACPI definition */
898 static int __init init_unity_map_range(struct ivmd_header *m)
900 struct unity_map_entry *e = 0;
902 e = kzalloc(sizeof(*e), GFP_KERNEL);
909 e->devid_start = e->devid_end = m->devid;
911 case ACPI_IVMD_TYPE_ALL:
913 e->devid_end = amd_iommu_last_bdf;
915 case ACPI_IVMD_TYPE_RANGE:
916 e->devid_start = m->devid;
917 e->devid_end = m->aux;
920 e->address_start = PAGE_ALIGN(m->range_start);
921 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
922 e->prot = m->flags >> 1;
924 list_add_tail(&e->list, &amd_iommu_unity_map);
929 /* iterates over all memory definitions we find in the ACPI table */
930 static int __init init_memory_definitions(struct acpi_table_header *table)
932 u8 *p = (u8 *)table, *end = (u8 *)table;
933 struct ivmd_header *m;
935 end += table->length;
936 p += IVRS_HEADER_LENGTH;
939 m = (struct ivmd_header *)p;
940 if (m->flags & IVMD_FLAG_EXCL_RANGE)
941 init_exclusion_range(m);
942 else if (m->flags & IVMD_FLAG_UNITY_MAP)
943 init_unity_map_range(m);
952 * Init the device table to not allow DMA access for devices and
953 * suppress all page faults
955 static void init_device_table(void)
959 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
960 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
961 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
966 * This function finally enables all IOMMUs found in the system after
967 * they have been initialized
969 static void __init enable_iommus(void)
971 struct amd_iommu *iommu;
973 list_for_each_entry(iommu, &amd_iommu_list, list) {
974 iommu_set_exclusion_range(iommu);
975 iommu_init_msi(iommu);
976 iommu_enable_event_logging(iommu);
982 * Suspend/Resume support
983 * disable suspend until real resume implemented
986 static int amd_iommu_resume(struct sys_device *dev)
991 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
996 static struct sysdev_class amd_iommu_sysdev_class = {
998 .suspend = amd_iommu_suspend,
999 .resume = amd_iommu_resume,
1002 static struct sys_device device_amd_iommu = {
1004 .cls = &amd_iommu_sysdev_class,
1008 * This is the core init function for AMD IOMMU hardware in the system.
1009 * This function is called from the generic x86 DMA layer initialization
1012 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1015 * 1 pass) Find the highest PCI device id the driver has to handle.
1016 * Upon this information the size of the data structures is
1017 * determined that needs to be allocated.
1019 * 2 pass) Initialize the data structures just allocated with the
1020 * information in the ACPI table about available AMD IOMMUs
1021 * in the system. It also maps the PCI devices in the
1022 * system to specific IOMMUs
1024 * 3 pass) After the basic data structures are allocated and
1025 * initialized we update them with information about memory
1026 * remapping requirements parsed out of the ACPI table in
1029 * After that the hardware is initialized and ready to go. In the last
1030 * step we do some Linux specific things like registering the driver in
1031 * the dma_ops interface and initializing the suspend/resume support
1032 * functions. Finally it prints some information about AMD IOMMUs and
1033 * the driver state and enables the hardware.
1035 int __init amd_iommu_init(void)
1041 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1045 if (!amd_iommu_detected)
1049 * First parse ACPI tables to find the largest Bus/Dev/Func
1050 * we need to handle. Upon this information the shared data
1051 * structures for the IOMMUs in the system will be allocated
1053 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1056 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1057 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1058 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1062 /* Device table - directly used by all IOMMUs */
1063 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1064 get_order(dev_table_size));
1065 if (amd_iommu_dev_table == NULL)
1069 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1070 * IOMMU see for that device
1072 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1073 get_order(alias_table_size));
1074 if (amd_iommu_alias_table == NULL)
1077 /* IOMMU rlookup table - find the IOMMU for a specific device */
1078 amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
1079 get_order(rlookup_table_size));
1080 if (amd_iommu_rlookup_table == NULL)
1084 * Protection Domain table - maps devices to protection domains
1085 * This table has the same size as the rlookup_table
1087 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1088 get_order(rlookup_table_size));
1089 if (amd_iommu_pd_table == NULL)
1092 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1093 GFP_KERNEL | __GFP_ZERO,
1094 get_order(MAX_DOMAIN_ID/8));
1095 if (amd_iommu_pd_alloc_bitmap == NULL)
1098 /* init the device table */
1099 init_device_table();
1102 * let all alias entries point to itself
1104 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1105 amd_iommu_alias_table[i] = i;
1108 * never allocate domain 0 because its used as the non-allocated and
1109 * error value placeholder
1111 amd_iommu_pd_alloc_bitmap[0] = 1;
1114 * now the data structures are allocated and basically initialized
1115 * start the real acpi table scan
1118 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1121 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1124 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1128 ret = sysdev_register(&device_amd_iommu);
1132 ret = amd_iommu_init_dma_ops();
1138 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
1139 (1 << (amd_iommu_aperture_order-20)));
1141 printk(KERN_INFO "AMD IOMMU: device isolation ");
1142 if (amd_iommu_isolate)
1143 printk("enabled\n");
1145 printk("disabled\n");
1147 if (iommu_fullflush)
1148 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1150 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1156 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1157 get_order(MAX_DOMAIN_ID/8));
1159 free_pages((unsigned long)amd_iommu_pd_table,
1160 get_order(rlookup_table_size));
1162 free_pages((unsigned long)amd_iommu_rlookup_table,
1163 get_order(rlookup_table_size));
1165 free_pages((unsigned long)amd_iommu_alias_table,
1166 get_order(alias_table_size));
1168 free_pages((unsigned long)amd_iommu_dev_table,
1169 get_order(dev_table_size));
1178 /****************************************************************************
1180 * Early detect code. This code runs at IOMMU detection time in the DMA
1181 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1184 ****************************************************************************/
1185 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1190 void __init amd_iommu_detect(void)
1192 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1195 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1197 amd_iommu_detected = 1;
1198 #ifdef CONFIG_GART_IOMMU
1199 gart_iommu_aperture_disabled = 1;
1200 gart_iommu_aperture = 0;
1205 /****************************************************************************
1207 * Parsing functions for the AMD IOMMU specific kernel command line
1210 ****************************************************************************/
1212 static int __init parse_amd_iommu_options(char *str)
1214 for (; *str; ++str) {
1215 if (strncmp(str, "isolate", 7) == 0)
1216 amd_iommu_isolate = 1;
1222 static int __init parse_amd_iommu_size_options(char *str)
1224 unsigned order = PAGE_SHIFT + get_order(memparse(str, &str));
1226 if ((order > 24) && (order < 31))
1227 amd_iommu_aperture_order = order;
1232 __setup("amd_iommu=", parse_amd_iommu_options);
1233 __setup("amd_iommu_size=", parse_amd_iommu_size_options);