2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
33 * definitions for the ACPI scanning code
35 #define PCI_BUS(x) (((x) >> 8) & 0xff)
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN 0x00
53 #define IVHD_FLAG_PASSPW_EN 0x01
54 #define IVHD_FLAG_RESPASSPW_EN 0x02
55 #define IVHD_FLAG_ISOC_EN 0x03
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed));
118 static int __initdata amd_iommu_detected;
120 u16 amd_iommu_last_bdf; /* largest PCI device id we have
122 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
124 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
125 int amd_iommu_isolate; /* if 1, device isolation is enabled */
127 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
131 * Pointer to the device table which is shared by all AMD IOMMUs
132 * it is indexed by the PCI device id or the HT unit id and contains
133 * information about the domain the device belongs to as well as the
134 * page table root pointer.
136 struct dev_table_entry *amd_iommu_dev_table;
139 * The alias table is a driver specific data structure which contains the
140 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
141 * More than one device can share the same requestor id.
143 u16 *amd_iommu_alias_table;
146 * The rlookup table is used to find the IOMMU which is responsible
147 * for a specific device. It is also indexed by the PCI device id.
149 struct amd_iommu **amd_iommu_rlookup_table;
152 * The pd table (protection domain table) is used to find the protection domain
153 * data structure a device belongs to. Indexed with the PCI device id too.
155 struct protection_domain **amd_iommu_pd_table;
158 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
159 * to know which ones are already in use.
161 unsigned long *amd_iommu_pd_alloc_bitmap;
163 static u32 dev_table_size; /* size of the device table */
164 static u32 alias_table_size; /* size of the alias table */
165 static u32 rlookup_table_size; /* size if the rlookup table */
167 static inline void update_last_devid(u16 devid)
169 if (devid > amd_iommu_last_bdf)
170 amd_iommu_last_bdf = devid;
173 static inline unsigned long tbl_size(int entry_size)
175 unsigned shift = PAGE_SHIFT +
176 get_order(amd_iommu_last_bdf * entry_size);
181 /****************************************************************************
183 * AMD IOMMU MMIO register space handling functions
185 * These functions are used to program the IOMMU device registers in
186 * MMIO space required for that driver.
188 ****************************************************************************/
191 * This function set the exclusion range in the IOMMU. DMA accesses to the
192 * exclusion range are passed through untranslated
194 static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
196 u64 start = iommu->exclusion_start & PAGE_MASK;
197 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
200 if (!iommu->exclusion_start)
203 entry = start | MMIO_EXCL_ENABLE_MASK;
204 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
205 &entry, sizeof(entry));
208 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
209 &entry, sizeof(entry));
212 /* Programs the physical address of the device table into the IOMMU hardware */
213 static void __init iommu_set_device_table(struct amd_iommu *iommu)
217 BUG_ON(iommu->mmio_base == NULL);
219 entry = virt_to_phys(amd_iommu_dev_table);
220 entry |= (dev_table_size >> 12) - 1;
221 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
222 &entry, sizeof(entry));
225 /* Generic functions to enable/disable certain features of the IOMMU. */
226 static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
230 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
232 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
235 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
239 ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
241 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
244 /* Function to enable the hardware */
245 void __init iommu_enable(struct amd_iommu *iommu)
247 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU "
248 "at %02x:%02x.%x cap 0x%hx\n",
249 iommu->dev->bus->number,
250 PCI_SLOT(iommu->dev->devfn),
251 PCI_FUNC(iommu->dev->devfn),
254 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
258 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
259 * the system has one.
261 static u8 * __init iommu_map_mmio_space(u64 address)
265 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
268 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
272 release_mem_region(address, MMIO_REGION_LENGTH);
277 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
279 if (iommu->mmio_base)
280 iounmap(iommu->mmio_base);
281 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
284 /****************************************************************************
286 * The functions below belong to the first pass of AMD IOMMU ACPI table
287 * parsing. In this pass we try to find out the highest device id this
288 * code has to handle. Upon this information the size of the shared data
289 * structures is determined later.
291 ****************************************************************************/
294 * This function reads the last device id the IOMMU has to handle from the PCI
295 * capability header for this IOMMU
297 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
301 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
302 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
308 * After reading the highest device id from the IOMMU PCI capability header
309 * this function looks if there is a higher device id defined in the ACPI table
311 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
313 u8 *p = (void *)h, *end = (void *)h;
314 struct ivhd_entry *dev;
319 find_last_devid_on_pci(PCI_BUS(h->devid),
325 dev = (struct ivhd_entry *)p;
327 case IVHD_DEV_SELECT:
328 case IVHD_DEV_RANGE_END:
330 case IVHD_DEV_EXT_SELECT:
331 /* all the above subfield types refer to device ids */
332 update_last_devid(dev->devid);
337 p += 0x04 << (*p >> 6);
346 * Iterate over all IVHD entries in the ACPI table and find the highest device
347 * id which we need to handle. This is the first of three functions which parse
348 * the ACPI table. So we check the checksum here.
350 static int __init find_last_devid_acpi(struct acpi_table_header *table)
353 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
354 struct ivhd_header *h;
357 * Validate checksum here so we don't need to do it when
358 * we actually parse the table
360 for (i = 0; i < table->length; ++i)
363 /* ACPI table corrupt */
366 p += IVRS_HEADER_LENGTH;
368 end += table->length;
370 h = (struct ivhd_header *)p;
373 find_last_devid_from_ivhd(h);
385 /****************************************************************************
387 * The following functions belong the the code path which parses the ACPI table
388 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
389 * data structures, initialize the device/alias/rlookup table and also
390 * basically initialize the hardware.
392 ****************************************************************************/
395 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
396 * write commands to that buffer later and the IOMMU will execute them
399 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
401 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
402 get_order(CMD_BUFFER_SIZE));
408 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
410 entry = (u64)virt_to_phys(cmd_buf);
411 entry |= MMIO_CMD_SIZE_512;
412 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
413 &entry, sizeof(entry));
415 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
420 static void __init free_command_buffer(struct amd_iommu *iommu)
422 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
425 /* allocates the memory where the IOMMU will log its events to */
426 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
429 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
430 get_order(EVT_BUFFER_SIZE));
432 if (iommu->evt_buf == NULL)
435 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
436 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
437 &entry, sizeof(entry));
439 iommu->evt_buf_size = EVT_BUFFER_SIZE;
441 return iommu->evt_buf;
444 static void __init free_event_buffer(struct amd_iommu *iommu)
446 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
449 /* sets a specific bit in the device table entry. */
450 static void set_dev_entry_bit(u16 devid, u8 bit)
452 int i = (bit >> 5) & 0x07;
453 int _bit = bit & 0x1f;
455 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
458 /* Writes the specific IOMMU for a device into the rlookup table */
459 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
461 amd_iommu_rlookup_table[devid] = iommu;
465 * This function takes the device specific flags read from the ACPI
466 * table and sets up the device table entry with that information
468 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
469 u16 devid, u32 flags, u32 ext_flags)
471 if (flags & ACPI_DEVFLAG_INITPASS)
472 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
473 if (flags & ACPI_DEVFLAG_EXTINT)
474 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
475 if (flags & ACPI_DEVFLAG_NMI)
476 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
477 if (flags & ACPI_DEVFLAG_SYSMGT1)
478 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
479 if (flags & ACPI_DEVFLAG_SYSMGT2)
480 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
481 if (flags & ACPI_DEVFLAG_LINT0)
482 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
483 if (flags & ACPI_DEVFLAG_LINT1)
484 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
486 set_iommu_for_device(iommu, devid);
490 * Reads the device exclusion range from ACPI and initialize IOMMU with
493 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
495 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
497 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
502 * We only can configure exclusion ranges per IOMMU, not
503 * per device. But we can enable the exclusion range per
504 * device. This is done here
506 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
507 iommu->exclusion_start = m->range_start;
508 iommu->exclusion_length = m->range_length;
513 * This function reads some important data from the IOMMU PCI space and
514 * initializes the driver data structure with it. It reads the hardware
515 * capabilities and the first/last device entries
517 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
519 int cap_ptr = iommu->cap_ptr;
522 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
524 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
526 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
529 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
531 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
533 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
537 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
538 * initializes the hardware and our data structures with it.
540 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
541 struct ivhd_header *h)
544 u8 *end = p, flags = 0;
545 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
548 struct ivhd_entry *e;
551 * First set the recommended feature enable bits from ACPI
552 * into the IOMMU control registers
554 h->flags & IVHD_FLAG_HT_TUN_EN ?
555 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
556 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
558 h->flags & IVHD_FLAG_PASSPW_EN ?
559 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
560 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
562 h->flags & IVHD_FLAG_RESPASSPW_EN ?
563 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
564 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
566 h->flags & IVHD_FLAG_ISOC_EN ?
567 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
568 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
571 * make IOMMU memory accesses cache coherent
573 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
576 * Done. Now parse the device entries
578 p += sizeof(struct ivhd_header);
582 e = (struct ivhd_entry *)p;
585 for (dev_i = iommu->first_device;
586 dev_i <= iommu->last_device; ++dev_i)
587 set_dev_entry_from_acpi(iommu, dev_i,
590 case IVHD_DEV_SELECT:
592 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
594 case IVHD_DEV_SELECT_RANGE_START:
595 devid_start = e->devid;
602 devid_to = e->ext >> 8;
603 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
604 amd_iommu_alias_table[devid] = devid_to;
606 case IVHD_DEV_ALIAS_RANGE:
607 devid_start = e->devid;
609 devid_to = e->ext >> 8;
613 case IVHD_DEV_EXT_SELECT:
615 set_dev_entry_from_acpi(iommu, devid, e->flags,
618 case IVHD_DEV_EXT_SELECT_RANGE:
619 devid_start = e->devid;
624 case IVHD_DEV_RANGE_END:
626 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
628 amd_iommu_alias_table[dev_i] = devid_to;
629 set_dev_entry_from_acpi(iommu,
630 amd_iommu_alias_table[dev_i],
638 p += 0x04 << (e->type >> 6);
642 /* Initializes the device->iommu mapping for the driver */
643 static int __init init_iommu_devices(struct amd_iommu *iommu)
647 for (i = iommu->first_device; i <= iommu->last_device; ++i)
648 set_iommu_for_device(iommu, i);
653 static void __init free_iommu_one(struct amd_iommu *iommu)
655 free_command_buffer(iommu);
656 free_event_buffer(iommu);
657 iommu_unmap_mmio_space(iommu);
660 static void __init free_iommu_all(void)
662 struct amd_iommu *iommu, *next;
664 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
665 list_del(&iommu->list);
666 free_iommu_one(iommu);
672 * This function clues the initialization function for one IOMMU
673 * together and also allocates the command buffer and programs the
674 * hardware. It does NOT enable the IOMMU. This is done afterwards.
676 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
678 spin_lock_init(&iommu->lock);
679 list_add_tail(&iommu->list, &amd_iommu_list);
682 * Copy data from ACPI table entry to the iommu struct
684 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
688 iommu->cap_ptr = h->cap_ptr;
689 iommu->pci_seg = h->pci_seg;
690 iommu->mmio_phys = h->mmio_phys;
691 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
692 if (!iommu->mmio_base)
695 iommu_set_device_table(iommu);
696 iommu->cmd_buf = alloc_command_buffer(iommu);
700 iommu->evt_buf = alloc_event_buffer(iommu);
704 iommu->int_enabled = false;
706 init_iommu_from_pci(iommu);
707 init_iommu_from_acpi(iommu, h);
708 init_iommu_devices(iommu);
710 pci_enable_device(iommu->dev);
716 * Iterates over all IOMMU entries in the ACPI table, allocates the
717 * IOMMU structure and initializes it with init_iommu_one()
719 static int __init init_iommu_all(struct acpi_table_header *table)
721 u8 *p = (u8 *)table, *end = (u8 *)table;
722 struct ivhd_header *h;
723 struct amd_iommu *iommu;
726 end += table->length;
727 p += IVRS_HEADER_LENGTH;
730 h = (struct ivhd_header *)p;
733 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
736 ret = init_iommu_one(iommu, h);
751 /****************************************************************************
753 * The following functions initialize the MSI interrupts for all IOMMUs
754 * in the system. Its a bit challenging because there could be multiple
755 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
758 ****************************************************************************/
760 static int __init iommu_setup_msix(struct amd_iommu *iommu)
762 struct amd_iommu *curr;
763 struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
766 list_for_each_entry(curr, &amd_iommu_list, list) {
767 if (curr->dev == iommu->dev) {
768 entries[nvec].entry = curr->evt_msi_num;
769 entries[nvec].vector = 0;
770 curr->int_enabled = true;
775 if (pci_enable_msix(iommu->dev, entries, nvec)) {
776 pci_disable_msix(iommu->dev);
780 for (i = 0; i < nvec; ++i) {
781 int r = request_irq(entries->vector, amd_iommu_int_handler,
792 for (i -= 1; i >= 0; --i)
793 free_irq(entries->vector, NULL);
795 pci_disable_msix(iommu->dev);
800 static int __init iommu_setup_msi(struct amd_iommu *iommu)
803 struct amd_iommu *curr;
805 list_for_each_entry(curr, &amd_iommu_list, list) {
806 if (curr->dev == iommu->dev)
807 curr->int_enabled = true;
811 if (pci_enable_msi(iommu->dev))
814 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
820 pci_disable_msi(iommu->dev);
827 static int __init iommu_init_msi(struct amd_iommu *iommu)
829 if (iommu->int_enabled)
832 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX))
833 return iommu_setup_msix(iommu);
834 else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
835 return iommu_setup_msi(iommu);
840 /****************************************************************************
842 * The next functions belong to the third pass of parsing the ACPI
843 * table. In this last pass the memory mapping requirements are
844 * gathered (like exclusion and unity mapping reanges).
846 ****************************************************************************/
848 static void __init free_unity_maps(void)
850 struct unity_map_entry *entry, *next;
852 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
853 list_del(&entry->list);
858 /* called when we find an exclusion range definition in ACPI */
859 static int __init init_exclusion_range(struct ivmd_header *m)
865 set_device_exclusion_range(m->devid, m);
867 case ACPI_IVMD_TYPE_ALL:
868 for (i = 0; i <= amd_iommu_last_bdf; ++i)
869 set_device_exclusion_range(i, m);
871 case ACPI_IVMD_TYPE_RANGE:
872 for (i = m->devid; i <= m->aux; ++i)
873 set_device_exclusion_range(i, m);
882 /* called for unity map ACPI definition */
883 static int __init init_unity_map_range(struct ivmd_header *m)
885 struct unity_map_entry *e = 0;
887 e = kzalloc(sizeof(*e), GFP_KERNEL);
894 e->devid_start = e->devid_end = m->devid;
896 case ACPI_IVMD_TYPE_ALL:
898 e->devid_end = amd_iommu_last_bdf;
900 case ACPI_IVMD_TYPE_RANGE:
901 e->devid_start = m->devid;
902 e->devid_end = m->aux;
905 e->address_start = PAGE_ALIGN(m->range_start);
906 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
907 e->prot = m->flags >> 1;
909 list_add_tail(&e->list, &amd_iommu_unity_map);
914 /* iterates over all memory definitions we find in the ACPI table */
915 static int __init init_memory_definitions(struct acpi_table_header *table)
917 u8 *p = (u8 *)table, *end = (u8 *)table;
918 struct ivmd_header *m;
920 end += table->length;
921 p += IVRS_HEADER_LENGTH;
924 m = (struct ivmd_header *)p;
925 if (m->flags & IVMD_FLAG_EXCL_RANGE)
926 init_exclusion_range(m);
927 else if (m->flags & IVMD_FLAG_UNITY_MAP)
928 init_unity_map_range(m);
937 * Init the device table to not allow DMA access for devices and
938 * suppress all page faults
940 static void init_device_table(void)
944 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
945 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
946 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
947 set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
952 * This function finally enables all IOMMUs found in the system after
953 * they have been initialized
955 static void __init enable_iommus(void)
957 struct amd_iommu *iommu;
959 list_for_each_entry(iommu, &amd_iommu_list, list) {
960 iommu_set_exclusion_range(iommu);
961 iommu_init_msi(iommu);
967 * Suspend/Resume support
968 * disable suspend until real resume implemented
971 static int amd_iommu_resume(struct sys_device *dev)
976 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
981 static struct sysdev_class amd_iommu_sysdev_class = {
983 .suspend = amd_iommu_suspend,
984 .resume = amd_iommu_resume,
987 static struct sys_device device_amd_iommu = {
989 .cls = &amd_iommu_sysdev_class,
993 * This is the core init function for AMD IOMMU hardware in the system.
994 * This function is called from the generic x86 DMA layer initialization
997 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1000 * 1 pass) Find the highest PCI device id the driver has to handle.
1001 * Upon this information the size of the data structures is
1002 * determined that needs to be allocated.
1004 * 2 pass) Initialize the data structures just allocated with the
1005 * information in the ACPI table about available AMD IOMMUs
1006 * in the system. It also maps the PCI devices in the
1007 * system to specific IOMMUs
1009 * 3 pass) After the basic data structures are allocated and
1010 * initialized we update them with information about memory
1011 * remapping requirements parsed out of the ACPI table in
1014 * After that the hardware is initialized and ready to go. In the last
1015 * step we do some Linux specific things like registering the driver in
1016 * the dma_ops interface and initializing the suspend/resume support
1017 * functions. Finally it prints some information about AMD IOMMUs and
1018 * the driver state and enables the hardware.
1020 int __init amd_iommu_init(void)
1026 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1030 if (!amd_iommu_detected)
1034 * First parse ACPI tables to find the largest Bus/Dev/Func
1035 * we need to handle. Upon this information the shared data
1036 * structures for the IOMMUs in the system will be allocated
1038 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1041 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1042 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1043 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1047 /* Device table - directly used by all IOMMUs */
1048 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1049 get_order(dev_table_size));
1050 if (amd_iommu_dev_table == NULL)
1054 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1055 * IOMMU see for that device
1057 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1058 get_order(alias_table_size));
1059 if (amd_iommu_alias_table == NULL)
1062 /* IOMMU rlookup table - find the IOMMU for a specific device */
1063 amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
1064 get_order(rlookup_table_size));
1065 if (amd_iommu_rlookup_table == NULL)
1069 * Protection Domain table - maps devices to protection domains
1070 * This table has the same size as the rlookup_table
1072 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1073 get_order(rlookup_table_size));
1074 if (amd_iommu_pd_table == NULL)
1077 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1078 GFP_KERNEL | __GFP_ZERO,
1079 get_order(MAX_DOMAIN_ID/8));
1080 if (amd_iommu_pd_alloc_bitmap == NULL)
1083 /* init the device table */
1084 init_device_table();
1087 * let all alias entries point to itself
1089 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1090 amd_iommu_alias_table[i] = i;
1093 * never allocate domain 0 because its used as the non-allocated and
1094 * error value placeholder
1096 amd_iommu_pd_alloc_bitmap[0] = 1;
1099 * now the data structures are allocated and basically initialized
1100 * start the real acpi table scan
1103 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1106 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1109 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1113 ret = sysdev_register(&device_amd_iommu);
1117 ret = amd_iommu_init_dma_ops();
1123 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
1124 (1 << (amd_iommu_aperture_order-20)));
1126 printk(KERN_INFO "AMD IOMMU: device isolation ");
1127 if (amd_iommu_isolate)
1128 printk("enabled\n");
1130 printk("disabled\n");
1132 if (iommu_fullflush)
1133 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1135 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1141 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
1143 free_pages((unsigned long)amd_iommu_pd_table,
1144 get_order(rlookup_table_size));
1146 free_pages((unsigned long)amd_iommu_rlookup_table,
1147 get_order(rlookup_table_size));
1149 free_pages((unsigned long)amd_iommu_alias_table,
1150 get_order(alias_table_size));
1152 free_pages((unsigned long)amd_iommu_dev_table,
1153 get_order(dev_table_size));
1162 /****************************************************************************
1164 * Early detect code. This code runs at IOMMU detection time in the DMA
1165 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1168 ****************************************************************************/
1169 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1174 void __init amd_iommu_detect(void)
1176 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1179 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1181 amd_iommu_detected = 1;
1182 #ifdef CONFIG_GART_IOMMU
1183 gart_iommu_aperture_disabled = 1;
1184 gart_iommu_aperture = 0;
1189 /****************************************************************************
1191 * Parsing functions for the AMD IOMMU specific kernel command line
1194 ****************************************************************************/
1196 static int __init parse_amd_iommu_options(char *str)
1198 for (; *str; ++str) {
1199 if (strncmp(str, "isolate", 7) == 0)
1200 amd_iommu_isolate = 1;
1206 static int __init parse_amd_iommu_size_options(char *str)
1208 unsigned order = PAGE_SHIFT + get_order(memparse(str, &str));
1210 if ((order > 24) && (order < 31))
1211 amd_iommu_aperture_order = order;
1216 __setup("amd_iommu=", parse_amd_iommu_options);
1217 __setup("amd_iommu_size=", parse_amd_iommu_size_options);