2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
32 #define EXIT_LOOP_COUNT 10000000
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 * general struct to manage commands send to an IOMMU
43 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
44 struct unity_map_entry *e);
46 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
47 static int iommu_has_npcache(struct amd_iommu *iommu)
49 return iommu->cap & IOMMU_CAP_NPCACHE;
52 /****************************************************************************
54 * IOMMU command queuing functions
56 ****************************************************************************/
59 * Writes the command to the IOMMUs command buffer and informs the
60 * hardware about the new command. Must be called with iommu->lock held.
62 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
67 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
68 target = iommu->cmd_buf + tail;
69 memcpy_toio(target, cmd, sizeof(*cmd));
70 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
71 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
74 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
80 * General queuing function for commands. Takes iommu->lock and calls
81 * __iommu_queue_command().
83 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
88 spin_lock_irqsave(&iommu->lock, flags);
89 ret = __iommu_queue_command(iommu, cmd);
90 spin_unlock_irqrestore(&iommu->lock, flags);
96 * This function is called whenever we need to ensure that the IOMMU has
97 * completed execution of all commands we sent. It sends a
98 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
99 * us about that by writing a value to a physical address we pass with
102 static int iommu_completion_wait(struct amd_iommu *iommu)
106 struct iommu_cmd cmd;
109 memset(&cmd, 0, sizeof(cmd));
110 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
111 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
113 iommu->need_sync = 0;
115 ret = iommu_queue_command(iommu, &cmd);
120 while (!ready && (i < EXIT_LOOP_COUNT)) {
122 /* wait for the bit to become one */
123 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
124 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
127 /* set bit back to zero */
128 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
129 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
131 if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
132 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
138 * Command send function for invalidating a device table entry
140 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
142 struct iommu_cmd cmd;
145 BUG_ON(iommu == NULL);
147 memset(&cmd, 0, sizeof(cmd));
148 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
151 ret = iommu_queue_command(iommu, &cmd);
153 iommu->need_sync = 1;
159 * Generic command send function for invalidaing TLB entries
161 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
162 u64 address, u16 domid, int pde, int s)
164 struct iommu_cmd cmd;
167 memset(&cmd, 0, sizeof(cmd));
168 address &= PAGE_MASK;
169 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
170 cmd.data[1] |= domid;
171 cmd.data[2] = lower_32_bits(address);
172 cmd.data[3] = upper_32_bits(address);
173 if (s) /* size bit - we flush more than one 4kb page */
174 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
175 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
176 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
178 ret = iommu_queue_command(iommu, &cmd);
180 iommu->need_sync = 1;
186 * TLB invalidation function which is called from the mapping functions.
187 * It invalidates a single PTE if the range to flush is within a single
188 * page. Otherwise it flushes the whole TLB of the IOMMU.
190 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
191 u64 address, size_t size)
194 unsigned pages = iommu_num_pages(address, size);
196 address &= PAGE_MASK;
200 * If we have to flush more than one page, flush all
201 * TLB entries for this domain
203 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
207 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
212 /****************************************************************************
214 * The functions below are used the create the page table mappings for
215 * unity mapped regions.
217 ****************************************************************************/
220 * Generic mapping functions. It maps a physical address into a DMA
221 * address space. It allocates the page table pages if necessary.
222 * In the future it can be extended to a generic mapping function
223 * supporting all features of AMD IOMMU page tables like level skipping
224 * and full 64 bit address spaces.
226 static int iommu_map(struct protection_domain *dom,
227 unsigned long bus_addr,
228 unsigned long phys_addr,
231 u64 __pte, *pte, *page;
233 bus_addr = PAGE_ALIGN(bus_addr);
234 phys_addr = PAGE_ALIGN(bus_addr);
236 /* only support 512GB address spaces for now */
237 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
240 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
242 if (!IOMMU_PTE_PRESENT(*pte)) {
243 page = (u64 *)get_zeroed_page(GFP_KERNEL);
246 *pte = IOMMU_L2_PDE(virt_to_phys(page));
249 pte = IOMMU_PTE_PAGE(*pte);
250 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
252 if (!IOMMU_PTE_PRESENT(*pte)) {
253 page = (u64 *)get_zeroed_page(GFP_KERNEL);
256 *pte = IOMMU_L1_PDE(virt_to_phys(page));
259 pte = IOMMU_PTE_PAGE(*pte);
260 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
262 if (IOMMU_PTE_PRESENT(*pte))
265 __pte = phys_addr | IOMMU_PTE_P;
266 if (prot & IOMMU_PROT_IR)
267 __pte |= IOMMU_PTE_IR;
268 if (prot & IOMMU_PROT_IW)
269 __pte |= IOMMU_PTE_IW;
277 * This function checks if a specific unity mapping entry is needed for
278 * this specific IOMMU.
280 static int iommu_for_unity_map(struct amd_iommu *iommu,
281 struct unity_map_entry *entry)
285 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
286 bdf = amd_iommu_alias_table[i];
287 if (amd_iommu_rlookup_table[bdf] == iommu)
295 * Init the unity mappings for a specific IOMMU in the system
297 * Basically iterates over all unity mapping entries and applies them to
298 * the default domain DMA of that IOMMU if necessary.
300 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
302 struct unity_map_entry *entry;
305 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
306 if (!iommu_for_unity_map(iommu, entry))
308 ret = dma_ops_unity_map(iommu->default_dom, entry);
317 * This function actually applies the mapping to the page table of the
320 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
321 struct unity_map_entry *e)
326 for (addr = e->address_start; addr < e->address_end;
328 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
332 * if unity mapping is in aperture range mark the page
333 * as allocated in the aperture
335 if (addr < dma_dom->aperture_size)
336 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
343 * Inits the unity mappings required for a specific device
345 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
348 struct unity_map_entry *e;
351 list_for_each_entry(e, &amd_iommu_unity_map, list) {
352 if (!(devid >= e->devid_start && devid <= e->devid_end))
354 ret = dma_ops_unity_map(dma_dom, e);
362 /****************************************************************************
364 * The next functions belong to the address allocator for the dma_ops
365 * interface functions. They work like the allocators in the other IOMMU
366 * drivers. Its basically a bitmap which marks the allocated pages in
367 * the aperture. Maybe it could be enhanced in the future to a more
368 * efficient allocator.
370 ****************************************************************************/
371 static unsigned long dma_mask_to_pages(unsigned long mask)
373 return (mask >> PAGE_SHIFT) +
374 (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
378 * The address allocator core function.
380 * called with domain->lock held
382 static unsigned long dma_ops_alloc_addresses(struct device *dev,
383 struct dma_ops_domain *dom,
386 unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
387 unsigned long address;
388 unsigned long size = dom->aperture_size >> PAGE_SHIFT;
389 unsigned long boundary_size;
391 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
392 PAGE_SIZE) >> PAGE_SHIFT;
393 limit = limit < size ? limit : size;
395 if (dom->next_bit >= limit)
398 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
399 0 , boundary_size, 0);
401 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
402 0, boundary_size, 0);
404 if (likely(address != -1)) {
405 dom->next_bit = address + pages;
406 address <<= PAGE_SHIFT;
408 address = bad_dma_address;
410 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
416 * The address free function.
418 * called with domain->lock held
420 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
421 unsigned long address,
424 address >>= PAGE_SHIFT;
425 iommu_area_free(dom->bitmap, address, pages);
428 /****************************************************************************
430 * The next functions belong to the domain allocation. A domain is
431 * allocated for every IOMMU as the default domain. If device isolation
432 * is enabled, every device get its own domain. The most important thing
433 * about domains is the page table mapping the DMA address space they
436 ****************************************************************************/
438 static u16 domain_id_alloc(void)
443 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
444 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
446 if (id > 0 && id < MAX_DOMAIN_ID)
447 __set_bit(id, amd_iommu_pd_alloc_bitmap);
450 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
456 * Used to reserve address ranges in the aperture (e.g. for exclusion
459 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
460 unsigned long start_page,
463 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
465 if (start_page + pages > last_page)
466 pages = last_page - start_page;
468 set_bit_string(dom->bitmap, start_page, pages);
471 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
476 p1 = dma_dom->domain.pt_root;
481 for (i = 0; i < 512; ++i) {
482 if (!IOMMU_PTE_PRESENT(p1[i]))
485 p2 = IOMMU_PTE_PAGE(p1[i]);
486 for (j = 0; j < 512; ++i) {
487 if (!IOMMU_PTE_PRESENT(p2[j]))
489 p3 = IOMMU_PTE_PAGE(p2[j]);
490 free_page((unsigned long)p3);
493 free_page((unsigned long)p2);
496 free_page((unsigned long)p1);
500 * Free a domain, only used if something went wrong in the
501 * allocation path and we need to free an already allocated page table
503 static void dma_ops_domain_free(struct dma_ops_domain *dom)
508 dma_ops_free_pagetable(dom);
510 kfree(dom->pte_pages);
518 * Allocates a new protection domain usable for the dma_ops functions.
519 * It also intializes the page table and the address allocator data
520 * structures required for the dma_ops interface
522 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
525 struct dma_ops_domain *dma_dom;
526 unsigned i, num_pte_pages;
531 * Currently the DMA aperture must be between 32 MB and 1GB in size
533 if ((order < 25) || (order > 30))
536 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
540 spin_lock_init(&dma_dom->domain.lock);
542 dma_dom->domain.id = domain_id_alloc();
543 if (dma_dom->domain.id == 0)
545 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
546 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
547 dma_dom->domain.priv = dma_dom;
548 if (!dma_dom->domain.pt_root)
550 dma_dom->aperture_size = (1ULL << order);
551 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
553 if (!dma_dom->bitmap)
556 * mark the first page as allocated so we never return 0 as
557 * a valid dma-address. So we can use 0 as error value
559 dma_dom->bitmap[0] = 1;
560 dma_dom->next_bit = 0;
562 /* Intialize the exclusion range if necessary */
563 if (iommu->exclusion_start &&
564 iommu->exclusion_start < dma_dom->aperture_size) {
565 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
566 int pages = iommu_num_pages(iommu->exclusion_start,
567 iommu->exclusion_length);
568 dma_ops_reserve_addresses(dma_dom, startpage, pages);
572 * At the last step, build the page tables so we don't need to
573 * allocate page table pages in the dma_ops mapping/unmapping
576 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
577 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
579 if (!dma_dom->pte_pages)
582 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
586 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
588 for (i = 0; i < num_pte_pages; ++i) {
589 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
590 if (!dma_dom->pte_pages[i])
592 address = virt_to_phys(dma_dom->pte_pages[i]);
593 l2_pde[i] = IOMMU_L1_PDE(address);
599 dma_ops_domain_free(dma_dom);
605 * Find out the protection domain structure for a given PCI device. This
606 * will give us the pointer to the page table root for example.
608 static struct protection_domain *domain_for_device(u16 devid)
610 struct protection_domain *dom;
613 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
614 dom = amd_iommu_pd_table[devid];
615 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
621 * If a device is not yet associated with a domain, this function does
622 * assigns it visible for the hardware
624 static void set_device_domain(struct amd_iommu *iommu,
625 struct protection_domain *domain,
630 u64 pte_root = virt_to_phys(domain->pt_root);
632 pte_root |= (domain->mode & 0x07) << 9;
633 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
635 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
636 amd_iommu_dev_table[devid].data[0] = pte_root;
637 amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
638 amd_iommu_dev_table[devid].data[2] = domain->id;
640 amd_iommu_pd_table[devid] = domain;
641 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
643 iommu_queue_inv_dev_entry(iommu, devid);
645 iommu->need_sync = 1;
648 /*****************************************************************************
650 * The next functions belong to the dma_ops mapping/unmapping code.
652 *****************************************************************************/
655 * In the dma_ops path we only have the struct device. This function
656 * finds the corresponding IOMMU, the protection domain and the
657 * requestor id for a given device.
658 * If the device is not yet associated with a domain this is also done
661 static int get_device_resources(struct device *dev,
662 struct amd_iommu **iommu,
663 struct protection_domain **domain,
666 struct dma_ops_domain *dma_dom;
667 struct pci_dev *pcidev;
670 BUG_ON(!dev || dev->bus != &pci_bus_type || !dev->dma_mask);
672 pcidev = to_pci_dev(dev);
673 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
675 /* device not translated by any IOMMU in the system? */
676 if (_bdf > amd_iommu_last_bdf) {
683 *bdf = amd_iommu_alias_table[_bdf];
685 *iommu = amd_iommu_rlookup_table[*bdf];
688 dma_dom = (*iommu)->default_dom;
689 *domain = domain_for_device(*bdf);
690 if (*domain == NULL) {
691 *domain = &dma_dom->domain;
692 set_device_domain(*iommu, *domain, *bdf);
693 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
694 "device ", (*domain)->id);
695 print_devid(_bdf, 1);
702 * This is the generic map function. It maps one 4kb page at paddr to
703 * the given address in the DMA address space for the domain.
705 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
706 struct dma_ops_domain *dom,
707 unsigned long address,
713 WARN_ON(address > dom->aperture_size);
717 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
718 pte += IOMMU_PTE_L0_INDEX(address);
720 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
722 if (direction == DMA_TO_DEVICE)
723 __pte |= IOMMU_PTE_IR;
724 else if (direction == DMA_FROM_DEVICE)
725 __pte |= IOMMU_PTE_IW;
726 else if (direction == DMA_BIDIRECTIONAL)
727 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
733 return (dma_addr_t)address;
737 * The generic unmapping function for on page in the DMA address space.
739 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
740 struct dma_ops_domain *dom,
741 unsigned long address)
745 if (address >= dom->aperture_size)
748 WARN_ON(address & 0xfffULL || address > dom->aperture_size);
750 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
751 pte += IOMMU_PTE_L0_INDEX(address);
759 * This function contains common code for mapping of a physically
760 * contiguous memory region into DMA address space. It is uses by all
761 * mapping functions provided by this IOMMU driver.
762 * Must be called with the domain lock held.
764 static dma_addr_t __map_single(struct device *dev,
765 struct amd_iommu *iommu,
766 struct dma_ops_domain *dma_dom,
771 dma_addr_t offset = paddr & ~PAGE_MASK;
772 dma_addr_t address, start;
776 pages = iommu_num_pages(paddr, size);
779 address = dma_ops_alloc_addresses(dev, dma_dom, pages);
780 if (unlikely(address == bad_dma_address))
784 for (i = 0; i < pages; ++i) {
785 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
796 * Does the reverse of the __map_single function. Must be called with
797 * the domain lock held too
799 static void __unmap_single(struct amd_iommu *iommu,
800 struct dma_ops_domain *dma_dom,
808 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
811 pages = iommu_num_pages(dma_addr, size);
812 dma_addr &= PAGE_MASK;
815 for (i = 0; i < pages; ++i) {
816 dma_ops_domain_unmap(iommu, dma_dom, start);
820 dma_ops_free_addresses(dma_dom, dma_addr, pages);
824 * The exported map_single function for dma_ops.
826 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
827 size_t size, int dir)
830 struct amd_iommu *iommu;
831 struct protection_domain *domain;
835 get_device_resources(dev, &iommu, &domain, &devid);
837 if (iommu == NULL || domain == NULL)
838 /* device not handled by any AMD IOMMU */
839 return (dma_addr_t)paddr;
841 spin_lock_irqsave(&domain->lock, flags);
842 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir);
843 if (addr == bad_dma_address)
846 if (iommu_has_npcache(iommu))
847 iommu_flush_pages(iommu, domain->id, addr, size);
849 if (iommu->need_sync)
850 iommu_completion_wait(iommu);
853 spin_unlock_irqrestore(&domain->lock, flags);
859 * The exported unmap_single function for dma_ops.
861 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
862 size_t size, int dir)
865 struct amd_iommu *iommu;
866 struct protection_domain *domain;
869 if (!get_device_resources(dev, &iommu, &domain, &devid))
870 /* device not handled by any AMD IOMMU */
873 spin_lock_irqsave(&domain->lock, flags);
875 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
877 iommu_flush_pages(iommu, domain->id, dma_addr, size);
879 if (iommu->need_sync)
880 iommu_completion_wait(iommu);
882 spin_unlock_irqrestore(&domain->lock, flags);
886 * This is a special map_sg function which is used if we should map a
887 * device which is not handled by an AMD IOMMU in the system.
889 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
892 struct scatterlist *s;
895 for_each_sg(sglist, s, nelems, i) {
896 s->dma_address = (dma_addr_t)sg_phys(s);
897 s->dma_length = s->length;
904 * The exported map_sg function for dma_ops (handles scatter-gather
907 static int map_sg(struct device *dev, struct scatterlist *sglist,
911 struct amd_iommu *iommu;
912 struct protection_domain *domain;
915 struct scatterlist *s;
917 int mapped_elems = 0;
919 get_device_resources(dev, &iommu, &domain, &devid);
921 if (!iommu || !domain)
922 return map_sg_no_iommu(dev, sglist, nelems, dir);
924 spin_lock_irqsave(&domain->lock, flags);
926 for_each_sg(sglist, s, nelems, i) {
929 s->dma_address = __map_single(dev, iommu, domain->priv,
930 paddr, s->length, dir);
932 if (s->dma_address) {
933 s->dma_length = s->length;
937 if (iommu_has_npcache(iommu))
938 iommu_flush_pages(iommu, domain->id, s->dma_address,
942 if (iommu->need_sync)
943 iommu_completion_wait(iommu);
946 spin_unlock_irqrestore(&domain->lock, flags);
950 for_each_sg(sglist, s, mapped_elems, i) {
952 __unmap_single(iommu, domain->priv, s->dma_address,
954 s->dma_address = s->dma_length = 0;
963 * The exported map_sg function for dma_ops (handles scatter-gather
966 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
970 struct amd_iommu *iommu;
971 struct protection_domain *domain;
972 struct scatterlist *s;
976 if (!get_device_resources(dev, &iommu, &domain, &devid))
979 spin_lock_irqsave(&domain->lock, flags);
981 for_each_sg(sglist, s, nelems, i) {
982 __unmap_single(iommu, domain->priv, s->dma_address,
984 iommu_flush_pages(iommu, domain->id, s->dma_address,
986 s->dma_address = s->dma_length = 0;
989 if (iommu->need_sync)
990 iommu_completion_wait(iommu);
992 spin_unlock_irqrestore(&domain->lock, flags);
996 * The exported alloc_coherent function for dma_ops.
998 static void *alloc_coherent(struct device *dev, size_t size,
999 dma_addr_t *dma_addr, gfp_t flag)
1001 unsigned long flags;
1003 struct amd_iommu *iommu;
1004 struct protection_domain *domain;
1008 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1012 memset(virt_addr, 0, size);
1013 paddr = virt_to_phys(virt_addr);
1015 get_device_resources(dev, &iommu, &domain, &devid);
1017 if (!iommu || !domain) {
1018 *dma_addr = (dma_addr_t)paddr;
1022 spin_lock_irqsave(&domain->lock, flags);
1024 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1025 size, DMA_BIDIRECTIONAL);
1027 if (*dma_addr == bad_dma_address) {
1028 free_pages((unsigned long)virt_addr, get_order(size));
1033 if (iommu_has_npcache(iommu))
1034 iommu_flush_pages(iommu, domain->id, *dma_addr, size);
1036 if (iommu->need_sync)
1037 iommu_completion_wait(iommu);
1040 spin_unlock_irqrestore(&domain->lock, flags);
1046 * The exported free_coherent function for dma_ops.
1047 * FIXME: fix the generic x86 DMA layer so that it actually calls that
1050 static void free_coherent(struct device *dev, size_t size,
1051 void *virt_addr, dma_addr_t dma_addr)
1053 unsigned long flags;
1054 struct amd_iommu *iommu;
1055 struct protection_domain *domain;
1058 get_device_resources(dev, &iommu, &domain, &devid);
1060 if (!iommu || !domain)
1063 spin_lock_irqsave(&domain->lock, flags);
1065 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1066 iommu_flush_pages(iommu, domain->id, dma_addr, size);
1068 if (iommu->need_sync)
1069 iommu_completion_wait(iommu);
1071 spin_unlock_irqrestore(&domain->lock, flags);
1074 free_pages((unsigned long)virt_addr, get_order(size));
1078 * The function for pre-allocating protection domains.
1080 * If the driver core informs the DMA layer if a driver grabs a device
1081 * we don't need to preallocate the protection domains anymore.
1082 * For now we have to.
1084 void prealloc_protection_domains(void)
1086 struct pci_dev *dev = NULL;
1087 struct dma_ops_domain *dma_dom;
1088 struct amd_iommu *iommu;
1089 int order = amd_iommu_aperture_order;
1092 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1093 devid = (dev->bus->number << 8) | dev->devfn;
1094 if (devid > amd_iommu_last_bdf)
1096 devid = amd_iommu_alias_table[devid];
1097 if (domain_for_device(devid))
1099 iommu = amd_iommu_rlookup_table[devid];
1102 dma_dom = dma_ops_domain_alloc(iommu, order);
1105 init_unity_mappings_for_device(dma_dom, devid);
1106 set_device_domain(iommu, &dma_dom->domain, devid);
1107 printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
1108 dma_dom->domain.id);
1109 print_devid(devid, 1);
1113 static struct dma_mapping_ops amd_iommu_dma_ops = {
1114 .alloc_coherent = alloc_coherent,
1115 .free_coherent = free_coherent,
1116 .map_single = map_single,
1117 .unmap_single = unmap_single,
1119 .unmap_sg = unmap_sg,
1123 * The function which clues the AMD IOMMU driver into dma_ops.
1125 int __init amd_iommu_init_dma_ops(void)
1127 struct amd_iommu *iommu;
1128 int order = amd_iommu_aperture_order;
1132 * first allocate a default protection domain for every IOMMU we
1133 * found in the system. Devices not assigned to any other
1134 * protection domain will be assigned to the default one.
1136 list_for_each_entry(iommu, &amd_iommu_list, list) {
1137 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1138 if (iommu->default_dom == NULL)
1140 ret = iommu_init_unity_mappings(iommu);
1146 * If device isolation is enabled, pre-allocate the protection
1147 * domains for each device.
1149 if (amd_iommu_isolate)
1150 prealloc_protection_domains();
1154 bad_dma_address = 0;
1155 #ifdef CONFIG_GART_IOMMU
1156 gart_iommu_aperture_disabled = 1;
1157 gart_iommu_aperture = 0;
1160 /* Make the driver finally visible to the drivers */
1161 dma_ops = &amd_iommu_dma_ops;
1167 list_for_each_entry(iommu, &amd_iommu_list, list) {
1168 if (iommu->default_dom)
1169 dma_ops_domain_free(iommu->default_dom);