1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
30 #include <asm/system.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
41 #include <asm/starfire.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
46 #include <asm/hypervisor.h>
48 #include <asm/sstate.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
52 #define MAX_PHYS_ADDRESS (1UL << 42UL)
53 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
54 #define KPTE_BITMAP_BYTES \
55 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
57 unsigned long kern_linear_pte_xor[2] __read_mostly;
59 /* A bitmap, one bit for every 256MB of physical memory. If the bit
60 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
61 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
63 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
65 #ifndef CONFIG_DEBUG_PAGEALLOC
66 /* A special kernel TSB for 4MB and 256MB linear mappings.
67 * Space is allocated for this right after the trap table
68 * in arch/sparc64/kernel/head.S
70 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
75 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
76 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
77 static int pavail_ents __initdata;
78 static int pavail_rescan_ents __initdata;
80 static int cmp_p64(const void *a, const void *b)
82 const struct linux_prom64_registers *x = a, *y = b;
84 if (x->phys_addr > y->phys_addr)
86 if (x->phys_addr < y->phys_addr)
91 static void __init read_obp_memory(const char *property,
92 struct linux_prom64_registers *regs,
95 int node = prom_finddevice("/memory");
96 int prop_size = prom_getproplen(node, property);
99 ents = prop_size / sizeof(struct linux_prom64_registers);
100 if (ents > MAX_BANKS) {
101 prom_printf("The machine has more %s property entries than "
102 "this kernel can support (%d).\n",
103 property, MAX_BANKS);
107 ret = prom_getproperty(node, property, (char *) regs, prop_size);
109 prom_printf("Couldn't get %s property from /memory.\n");
113 /* Sanitize what we got from the firmware, by page aligning
116 for (i = 0; i < ents; i++) {
117 unsigned long base, size;
119 base = regs[i].phys_addr;
120 size = regs[i].reg_size;
123 if (base & ~PAGE_MASK) {
124 unsigned long new_base = PAGE_ALIGN(base);
126 size -= new_base - base;
127 if ((long) size < 0L)
132 /* If it is empty, simply get rid of it.
133 * This simplifies the logic of the other
134 * functions that process these arrays.
136 memmove(®s[i], ®s[i + 1],
137 (ents - i - 1) * sizeof(regs[0]));
142 regs[i].phys_addr = base;
143 regs[i].reg_size = size;
148 sort(regs, ents, sizeof(struct linux_prom64_registers),
152 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
154 /* Kernel physical address base and size in bytes. */
155 unsigned long kern_base __read_mostly;
156 unsigned long kern_size __read_mostly;
158 /* Initial ramdisk setup */
159 extern unsigned long sparc_ramdisk_image64;
160 extern unsigned int sparc_ramdisk_image;
161 extern unsigned int sparc_ramdisk_size;
163 struct page *mem_map_zero __read_mostly;
165 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
167 unsigned long sparc64_kern_pri_context __read_mostly;
168 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
169 unsigned long sparc64_kern_sec_context __read_mostly;
171 int num_kernel_image_mappings;
173 #ifdef CONFIG_DEBUG_DCFLUSH
174 atomic_t dcpage_flushes = ATOMIC_INIT(0);
176 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
180 inline void flush_dcache_page_impl(struct page *page)
182 BUG_ON(tlb_type == hypervisor);
183 #ifdef CONFIG_DEBUG_DCFLUSH
184 atomic_inc(&dcpage_flushes);
187 #ifdef DCACHE_ALIASING_POSSIBLE
188 __flush_dcache_page(page_address(page),
189 ((tlb_type == spitfire) &&
190 page_mapping(page) != NULL));
192 if (page_mapping(page) != NULL &&
193 tlb_type == spitfire)
194 __flush_icache_page(__pa(page_address(page)));
198 #define PG_dcache_dirty PG_arch_1
199 #define PG_dcache_cpu_shift 32UL
200 #define PG_dcache_cpu_mask \
201 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
203 #define dcache_dirty_cpu(page) \
204 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
206 static inline void set_dcache_dirty(struct page *page, int this_cpu)
208 unsigned long mask = this_cpu;
209 unsigned long non_cpu_bits;
211 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
212 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
214 __asm__ __volatile__("1:\n\t"
216 "and %%g7, %1, %%g1\n\t"
217 "or %%g1, %0, %%g1\n\t"
218 "casx [%2], %%g7, %%g1\n\t"
220 "membar #StoreLoad | #StoreStore\n\t"
221 "bne,pn %%xcc, 1b\n\t"
224 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
228 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
230 unsigned long mask = (1UL << PG_dcache_dirty);
232 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
235 "srlx %%g7, %4, %%g1\n\t"
236 "and %%g1, %3, %%g1\n\t"
238 "bne,pn %%icc, 2f\n\t"
239 " andn %%g7, %1, %%g1\n\t"
240 "casx [%2], %%g7, %%g1\n\t"
242 "membar #StoreLoad | #StoreStore\n\t"
243 "bne,pn %%xcc, 1b\n\t"
247 : "r" (cpu), "r" (mask), "r" (&page->flags),
248 "i" (PG_dcache_cpu_mask),
249 "i" (PG_dcache_cpu_shift)
253 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
255 unsigned long tsb_addr = (unsigned long) ent;
257 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
258 tsb_addr = __pa(tsb_addr);
260 __tsb_insert(tsb_addr, tag, pte);
263 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
264 unsigned long _PAGE_SZBITS __read_mostly;
266 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
268 struct mm_struct *mm;
270 unsigned long tag, flags;
271 unsigned long tsb_index, tsb_hash_shift;
273 if (tlb_type != hypervisor) {
274 unsigned long pfn = pte_pfn(pte);
275 unsigned long pg_flags;
278 if (pfn_valid(pfn) &&
279 (page = pfn_to_page(pfn), page_mapping(page)) &&
280 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
281 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
283 int this_cpu = get_cpu();
285 /* This is just to optimize away some function calls
289 flush_dcache_page_impl(page);
291 smp_flush_dcache_page_impl(page, cpu);
293 clear_dcache_dirty_cpu(page, cpu);
301 tsb_index = MM_TSB_BASE;
302 tsb_hash_shift = PAGE_SHIFT;
304 spin_lock_irqsave(&mm->context.lock, flags);
306 #ifdef CONFIG_HUGETLB_PAGE
307 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
308 if ((tlb_type == hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
310 (tlb_type != hypervisor &&
311 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
312 tsb_index = MM_TSB_HUGE;
313 tsb_hash_shift = HPAGE_SHIFT;
318 tsb = mm->context.tsb_block[tsb_index].tsb;
319 tsb += ((address >> tsb_hash_shift) &
320 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
321 tag = (address >> 22UL);
322 tsb_insert(tsb, tag, pte_val(pte));
324 spin_unlock_irqrestore(&mm->context.lock, flags);
327 void flush_dcache_page(struct page *page)
329 struct address_space *mapping;
332 if (tlb_type == hypervisor)
335 /* Do not bother with the expensive D-cache flush if it
336 * is merely the zero page. The 'bigcore' testcase in GDB
337 * causes this case to run millions of times.
339 if (page == ZERO_PAGE(0))
342 this_cpu = get_cpu();
344 mapping = page_mapping(page);
345 if (mapping && !mapping_mapped(mapping)) {
346 int dirty = test_bit(PG_dcache_dirty, &page->flags);
348 int dirty_cpu = dcache_dirty_cpu(page);
350 if (dirty_cpu == this_cpu)
352 smp_flush_dcache_page_impl(page, dirty_cpu);
354 set_dcache_dirty(page, this_cpu);
356 /* We could delay the flush for the !page_mapping
357 * case too. But that case is for exec env/arg
358 * pages and those are %99 certainly going to get
359 * faulted into the tlb (and thus flushed) anyways.
361 flush_dcache_page_impl(page);
368 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
370 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
371 if (tlb_type == spitfire) {
374 /* This code only runs on Spitfire cpus so this is
375 * why we can assume _PAGE_PADDR_4U.
377 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
378 unsigned long paddr, mask = _PAGE_PADDR_4U;
380 if (kaddr >= PAGE_OFFSET)
381 paddr = kaddr & mask;
383 pgd_t *pgdp = pgd_offset_k(kaddr);
384 pud_t *pudp = pud_offset(pgdp, kaddr);
385 pmd_t *pmdp = pmd_offset(pudp, kaddr);
386 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
388 paddr = pte_val(*ptep) & mask;
390 __flush_icache_page(paddr);
397 unsigned long total = 0, reserved = 0;
398 unsigned long shared = 0, cached = 0;
401 printk(KERN_INFO "Mem-info:\n");
403 printk(KERN_INFO "Free swap: %6ldkB\n",
404 nr_swap_pages << (PAGE_SHIFT-10));
405 for_each_online_pgdat(pgdat) {
406 unsigned long i, flags;
408 pgdat_resize_lock(pgdat, &flags);
409 for (i = 0; i < pgdat->node_spanned_pages; i++) {
410 struct page *page = pgdat_page_nr(pgdat, i);
412 if (PageReserved(page))
414 else if (PageSwapCache(page))
416 else if (page_count(page))
417 shared += page_count(page) - 1;
419 pgdat_resize_unlock(pgdat, &flags);
422 printk(KERN_INFO "%lu pages of RAM\n", total);
423 printk(KERN_INFO "%lu reserved pages\n", reserved);
424 printk(KERN_INFO "%lu pages shared\n", shared);
425 printk(KERN_INFO "%lu pages swap cached\n", cached);
427 printk(KERN_INFO "%lu pages dirty\n",
428 global_page_state(NR_FILE_DIRTY));
429 printk(KERN_INFO "%lu pages writeback\n",
430 global_page_state(NR_WRITEBACK));
431 printk(KERN_INFO "%lu pages mapped\n",
432 global_page_state(NR_FILE_MAPPED));
433 printk(KERN_INFO "%lu pages slab\n",
434 global_page_state(NR_SLAB_RECLAIMABLE) +
435 global_page_state(NR_SLAB_UNRECLAIMABLE));
436 printk(KERN_INFO "%lu pages pagetables\n",
437 global_page_state(NR_PAGETABLE));
440 void mmu_info(struct seq_file *m)
442 if (tlb_type == cheetah)
443 seq_printf(m, "MMU Type\t: Cheetah\n");
444 else if (tlb_type == cheetah_plus)
445 seq_printf(m, "MMU Type\t: Cheetah+\n");
446 else if (tlb_type == spitfire)
447 seq_printf(m, "MMU Type\t: Spitfire\n");
448 else if (tlb_type == hypervisor)
449 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
451 seq_printf(m, "MMU Type\t: ???\n");
453 #ifdef CONFIG_DEBUG_DCFLUSH
454 seq_printf(m, "DCPageFlushes\t: %d\n",
455 atomic_read(&dcpage_flushes));
457 seq_printf(m, "DCPageFlushesXC\t: %d\n",
458 atomic_read(&dcpage_flushes_xcall));
459 #endif /* CONFIG_SMP */
460 #endif /* CONFIG_DEBUG_DCFLUSH */
463 struct linux_prom_translation {
469 /* Exported for kernel TLB miss handling in ktlb.S */
470 struct linux_prom_translation prom_trans[512] __read_mostly;
471 unsigned int prom_trans_ents __read_mostly;
473 /* Exported for SMP bootup purposes. */
474 unsigned long kern_locked_tte_data;
476 /* The obp translations are saved based on 8k pagesize, since obp can
477 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
478 * HI_OBP_ADDRESS range are handled in ktlb.S.
480 static inline int in_obp_range(unsigned long vaddr)
482 return (vaddr >= LOW_OBP_ADDRESS &&
483 vaddr < HI_OBP_ADDRESS);
486 static int cmp_ptrans(const void *a, const void *b)
488 const struct linux_prom_translation *x = a, *y = b;
490 if (x->virt > y->virt)
492 if (x->virt < y->virt)
497 /* Read OBP translations property into 'prom_trans[]'. */
498 static void __init read_obp_translations(void)
500 int n, node, ents, first, last, i;
502 node = prom_finddevice("/virtual-memory");
503 n = prom_getproplen(node, "translations");
504 if (unlikely(n == 0 || n == -1)) {
505 prom_printf("prom_mappings: Couldn't get size.\n");
508 if (unlikely(n > sizeof(prom_trans))) {
509 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
513 if ((n = prom_getproperty(node, "translations",
514 (char *)&prom_trans[0],
515 sizeof(prom_trans))) == -1) {
516 prom_printf("prom_mappings: Couldn't get property.\n");
520 n = n / sizeof(struct linux_prom_translation);
524 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
527 /* Now kick out all the non-OBP entries. */
528 for (i = 0; i < ents; i++) {
529 if (in_obp_range(prom_trans[i].virt))
533 for (; i < ents; i++) {
534 if (!in_obp_range(prom_trans[i].virt))
539 for (i = 0; i < (last - first); i++) {
540 struct linux_prom_translation *src = &prom_trans[i + first];
541 struct linux_prom_translation *dest = &prom_trans[i];
545 for (; i < ents; i++) {
546 struct linux_prom_translation *dest = &prom_trans[i];
547 dest->virt = dest->size = dest->data = 0x0UL;
550 prom_trans_ents = last - first;
552 if (tlb_type == spitfire) {
553 /* Clear diag TTE bits. */
554 for (i = 0; i < prom_trans_ents; i++)
555 prom_trans[i].data &= ~0x0003fe0000000000UL;
559 static void __init hypervisor_tlb_lock(unsigned long vaddr,
563 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
566 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
567 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
572 static unsigned long kern_large_tte(unsigned long paddr);
574 static void __init remap_kernel(void)
576 unsigned long phys_page, tte_vaddr, tte_data;
577 int i, tlb_ent = sparc64_highest_locked_tlbent();
579 tte_vaddr = (unsigned long) KERNBASE;
580 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
581 tte_data = kern_large_tte(phys_page);
583 kern_locked_tte_data = tte_data;
585 /* Now lock us into the TLBs via Hypervisor or OBP. */
586 if (tlb_type == hypervisor) {
587 for (i = 0; i < num_kernel_image_mappings; i++) {
588 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
589 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
590 tte_vaddr += 0x400000;
591 tte_data += 0x400000;
594 for (i = 0; i < num_kernel_image_mappings; i++) {
595 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
596 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
597 tte_vaddr += 0x400000;
598 tte_data += 0x400000;
600 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
602 if (tlb_type == cheetah_plus) {
603 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
604 CTX_CHEETAH_PLUS_NUC);
605 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
606 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
611 static void __init inherit_prom_mappings(void)
613 read_obp_translations();
615 /* Now fixup OBP's idea about where we really are mapped. */
616 printk("Remapping the kernel... ");
621 void prom_world(int enter)
624 set_fs((mm_segment_t) { get_thread_current_ds() });
626 __asm__ __volatile__("flushw");
629 void __flush_dcache_range(unsigned long start, unsigned long end)
633 if (tlb_type == spitfire) {
636 for (va = start; va < end; va += 32) {
637 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
641 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
644 for (va = start; va < end; va += 32)
645 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
649 "i" (ASI_DCACHE_INVALIDATE));
653 /* get_new_mmu_context() uses "cache + 1". */
654 DEFINE_SPINLOCK(ctx_alloc_lock);
655 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
656 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
657 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
658 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
660 /* Caller does TLB context flushing on local CPU if necessary.
661 * The caller also ensures that CTX_VALID(mm->context) is false.
663 * We must be careful about boundary cases so that we never
664 * let the user have CTX 0 (nucleus) or we ever use a CTX
665 * version of zero (and thus NO_CONTEXT would not be caught
666 * by version mis-match tests in mmu_context.h).
668 * Always invoked with interrupts disabled.
670 void get_new_mmu_context(struct mm_struct *mm)
672 unsigned long ctx, new_ctx;
673 unsigned long orig_pgsz_bits;
677 spin_lock_irqsave(&ctx_alloc_lock, flags);
678 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
679 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
680 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
682 if (new_ctx >= (1 << CTX_NR_BITS)) {
683 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
684 if (new_ctx >= ctx) {
686 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
689 new_ctx = CTX_FIRST_VERSION;
691 /* Don't call memset, for 16 entries that's just
694 mmu_context_bmap[0] = 3;
695 mmu_context_bmap[1] = 0;
696 mmu_context_bmap[2] = 0;
697 mmu_context_bmap[3] = 0;
698 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
699 mmu_context_bmap[i + 0] = 0;
700 mmu_context_bmap[i + 1] = 0;
701 mmu_context_bmap[i + 2] = 0;
702 mmu_context_bmap[i + 3] = 0;
708 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
709 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
711 tlb_context_cache = new_ctx;
712 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
713 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
715 if (unlikely(new_version))
716 smp_new_mmu_context_version();
719 /* Find a free area for the bootmem map, avoiding the kernel image
720 * and the initial ramdisk.
722 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
723 unsigned long end_pfn)
725 unsigned long avoid_start, avoid_end, bootmap_size;
728 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
729 bootmap_size <<= PAGE_SHIFT;
731 avoid_start = avoid_end = 0;
732 #ifdef CONFIG_BLK_DEV_INITRD
733 avoid_start = initrd_start;
734 avoid_end = PAGE_ALIGN(initrd_end);
737 for (i = 0; i < pavail_ents; i++) {
738 unsigned long start, end;
740 start = pavail[i].phys_addr;
741 end = start + pavail[i].reg_size;
743 while (start < end) {
744 if (start >= kern_base &&
745 start < PAGE_ALIGN(kern_base + kern_size)) {
746 start = PAGE_ALIGN(kern_base + kern_size);
749 if (start >= avoid_start && start < avoid_end) {
754 if ((end - start) < bootmap_size)
757 if (start < kern_base &&
758 (start + bootmap_size) > kern_base) {
759 start = PAGE_ALIGN(kern_base + kern_size);
763 if (start < avoid_start &&
764 (start + bootmap_size) > avoid_start) {
769 /* OK, it doesn't overlap anything, use it. */
770 return start >> PAGE_SHIFT;
774 prom_printf("Cannot find free area for bootmap, aborting.\n");
778 static void __init trim_pavail(unsigned long *cur_size_p,
779 unsigned long *end_of_phys_p)
781 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
782 unsigned long avoid_start, avoid_end;
785 to_trim = PAGE_ALIGN(to_trim);
787 avoid_start = avoid_end = 0;
788 #ifdef CONFIG_BLK_DEV_INITRD
789 avoid_start = initrd_start;
790 avoid_end = PAGE_ALIGN(initrd_end);
793 /* Trim some pavail[] entries in order to satisfy the
794 * requested "mem=xxx" kernel command line specification.
796 * We must not trim off the kernel image area nor the
797 * initial ramdisk range (if any). Also, we must not trim
798 * any pavail[] entry down to zero in order to preserve
799 * the invariant that all pavail[] entries have a non-zero
800 * size which is assumed by all of the code in here.
802 for (i = 0; i < pavail_ents; i++) {
803 unsigned long start, end, kern_end;
804 unsigned long trim_low, trim_high, n;
806 kern_end = PAGE_ALIGN(kern_base + kern_size);
808 trim_low = start = pavail[i].phys_addr;
809 trim_high = end = start + pavail[i].reg_size;
811 if (kern_base >= start &&
813 trim_low = kern_base;
817 if (kern_end >= start &&
819 trim_high = kern_end;
822 avoid_start >= start &&
824 if (trim_low > avoid_start)
825 trim_low = avoid_start;
826 if (avoid_end >= end)
830 avoid_end >= start &&
832 if (trim_high < avoid_end)
833 trim_high = avoid_end;
836 if (trim_high <= trim_low)
839 if (trim_low == start && trim_high == end) {
840 /* Whole chunk is available for trimming.
841 * Trim all except one page, in order to keep
844 n = (end - start) - PAGE_SIZE;
849 pavail[i].phys_addr += n;
850 pavail[i].reg_size -= n;
854 n = (trim_low - start);
859 pavail[i].phys_addr += n;
860 pavail[i].reg_size -= n;
868 pavail[i].reg_size -= n;
880 for (i = 0; i < pavail_ents; i++) {
881 *end_of_phys_p = pavail[i].phys_addr +
883 *cur_size_p += pavail[i].reg_size;
887 static void __init find_ramdisk(unsigned long phys_base)
889 #ifdef CONFIG_BLK_DEV_INITRD
890 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
891 unsigned long ramdisk_image;
893 /* Older versions of the bootloader only supported a
894 * 32-bit physical address for the ramdisk image
895 * location, stored at sparc_ramdisk_image. Newer
896 * SILO versions set sparc_ramdisk_image to zero and
897 * provide a full 64-bit physical address at
898 * sparc_ramdisk_image64.
900 ramdisk_image = sparc_ramdisk_image;
902 ramdisk_image = sparc_ramdisk_image64;
904 /* Another bootloader quirk. The bootloader normalizes
905 * the physical address to KERNBASE, so we have to
906 * factor that back out and add in the lowest valid
907 * physical page address to get the true physical address.
909 ramdisk_image -= KERNBASE;
910 ramdisk_image += phys_base;
912 initrd_start = ramdisk_image;
913 initrd_end = ramdisk_image + sparc_ramdisk_size;
915 lmb_reserve(initrd_start, initrd_end);
920 /* About pages_avail, this is the value we will use to calculate
921 * the zholes_size[] argument given to free_area_init_node(). The
922 * page allocator uses this to calculate nr_kernel_pages,
923 * nr_all_pages and zone->present_pages. On NUMA it is used
924 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
926 * So this number should really be set to what the page allocator
927 * actually ends up with. This means:
928 * 1) It should include bootmem map pages, we'll release those.
929 * 2) It should not include the kernel image, except for the
930 * __init sections which we will also release.
931 * 3) It should include the initrd image, since we'll release
934 static unsigned long __init bootmem_init(unsigned long *pages_avail,
935 unsigned long phys_base)
937 unsigned long bootmap_size, end_pfn;
938 unsigned long end_of_phys_memory = 0UL;
939 unsigned long bootmap_pfn, bytes_avail, size;
943 for (i = 0; i < pavail_ents; i++) {
944 end_of_phys_memory = pavail[i].phys_addr +
946 bytes_avail += pavail[i].reg_size;
949 if (cmdline_memory_size &&
950 bytes_avail > cmdline_memory_size)
951 trim_pavail(&bytes_avail,
952 &end_of_phys_memory);
954 *pages_avail = bytes_avail >> PAGE_SHIFT;
956 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
958 /* Initialize the boot-time allocator. */
959 max_pfn = max_low_pfn = end_pfn;
960 min_low_pfn = (phys_base >> PAGE_SHIFT);
962 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
964 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
965 min_low_pfn, end_pfn);
967 /* Now register the available physical memory with the
970 for (i = 0; i < pavail_ents; i++)
971 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
973 #ifdef CONFIG_BLK_DEV_INITRD
975 size = initrd_end - initrd_start;
977 /* Reserve the initrd image area. */
978 reserve_bootmem(initrd_start, size, BOOTMEM_DEFAULT);
980 initrd_start += PAGE_OFFSET;
981 initrd_end += PAGE_OFFSET;
984 /* Reserve the kernel text/data/bss. */
985 reserve_bootmem(kern_base, kern_size, BOOTMEM_DEFAULT);
986 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
988 /* Add back in the initmem pages. */
989 size = ((unsigned long)(__init_end) & PAGE_MASK) -
990 PAGE_ALIGN((unsigned long)__init_begin);
991 *pages_avail += size >> PAGE_SHIFT;
993 /* Reserve the bootmem map. We do not account for it
994 * in pages_avail because we will release that memory
995 * in free_all_bootmem.
998 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size, BOOTMEM_DEFAULT);
1000 for (i = 0; i < pavail_ents; i++) {
1001 unsigned long start_pfn, end_pfn;
1003 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1004 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1005 memory_present(0, start_pfn, end_pfn);
1013 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1014 static int pall_ents __initdata;
1016 #ifdef CONFIG_DEBUG_PAGEALLOC
1017 static unsigned long __ref kernel_map_range(unsigned long pstart,
1018 unsigned long pend, pgprot_t prot)
1020 unsigned long vstart = PAGE_OFFSET + pstart;
1021 unsigned long vend = PAGE_OFFSET + pend;
1022 unsigned long alloc_bytes = 0UL;
1024 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1025 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1030 while (vstart < vend) {
1031 unsigned long this_end, paddr = __pa(vstart);
1032 pgd_t *pgd = pgd_offset_k(vstart);
1037 pud = pud_offset(pgd, vstart);
1038 if (pud_none(*pud)) {
1041 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1042 alloc_bytes += PAGE_SIZE;
1043 pud_populate(&init_mm, pud, new);
1046 pmd = pmd_offset(pud, vstart);
1047 if (!pmd_present(*pmd)) {
1050 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1051 alloc_bytes += PAGE_SIZE;
1052 pmd_populate_kernel(&init_mm, pmd, new);
1055 pte = pte_offset_kernel(pmd, vstart);
1056 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1057 if (this_end > vend)
1060 while (vstart < this_end) {
1061 pte_val(*pte) = (paddr | pgprot_val(prot));
1063 vstart += PAGE_SIZE;
1072 extern unsigned int kvmap_linear_patch[1];
1073 #endif /* CONFIG_DEBUG_PAGEALLOC */
1075 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1077 const unsigned long shift_256MB = 28;
1078 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1079 const unsigned long size_256MB = (1UL << shift_256MB);
1081 while (start < end) {
1084 remains = end - start;
1085 if (remains < size_256MB)
1088 if (start & mask_256MB) {
1089 start = (start + size_256MB) & ~mask_256MB;
1093 while (remains >= size_256MB) {
1094 unsigned long index = start >> shift_256MB;
1096 __set_bit(index, kpte_linear_bitmap);
1098 start += size_256MB;
1099 remains -= size_256MB;
1104 static void __init init_kpte_bitmap(void)
1108 for (i = 0; i < pall_ents; i++) {
1109 unsigned long phys_start, phys_end;
1111 phys_start = pall[i].phys_addr;
1112 phys_end = phys_start + pall[i].reg_size;
1114 mark_kpte_bitmap(phys_start, phys_end);
1118 static void __init kernel_physical_mapping_init(void)
1120 #ifdef CONFIG_DEBUG_PAGEALLOC
1121 unsigned long i, mem_alloced = 0UL;
1123 for (i = 0; i < pall_ents; i++) {
1124 unsigned long phys_start, phys_end;
1126 phys_start = pall[i].phys_addr;
1127 phys_end = phys_start + pall[i].reg_size;
1129 mem_alloced += kernel_map_range(phys_start, phys_end,
1133 printk("Allocated %ld bytes for kernel page tables.\n",
1136 kvmap_linear_patch[0] = 0x01000000; /* nop */
1137 flushi(&kvmap_linear_patch[0]);
1143 #ifdef CONFIG_DEBUG_PAGEALLOC
1144 void kernel_map_pages(struct page *page, int numpages, int enable)
1146 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1147 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1149 kernel_map_range(phys_start, phys_end,
1150 (enable ? PAGE_KERNEL : __pgprot(0)));
1152 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1153 PAGE_OFFSET + phys_end);
1155 /* we should perform an IPI and flush all tlbs,
1156 * but that can deadlock->flush only current cpu.
1158 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1159 PAGE_OFFSET + phys_end);
1163 unsigned long __init find_ecache_flush_span(unsigned long size)
1167 for (i = 0; i < pavail_ents; i++) {
1168 if (pavail[i].reg_size >= size)
1169 return pavail[i].phys_addr;
1175 static void __init tsb_phys_patch(void)
1177 struct tsb_ldquad_phys_patch_entry *pquad;
1178 struct tsb_phys_patch_entry *p;
1180 pquad = &__tsb_ldquad_phys_patch;
1181 while (pquad < &__tsb_ldquad_phys_patch_end) {
1182 unsigned long addr = pquad->addr;
1184 if (tlb_type == hypervisor)
1185 *(unsigned int *) addr = pquad->sun4v_insn;
1187 *(unsigned int *) addr = pquad->sun4u_insn;
1189 __asm__ __volatile__("flush %0"
1196 p = &__tsb_phys_patch;
1197 while (p < &__tsb_phys_patch_end) {
1198 unsigned long addr = p->addr;
1200 *(unsigned int *) addr = p->insn;
1202 __asm__ __volatile__("flush %0"
1210 /* Don't mark as init, we give this to the Hypervisor. */
1211 #ifndef CONFIG_DEBUG_PAGEALLOC
1212 #define NUM_KTSB_DESCR 2
1214 #define NUM_KTSB_DESCR 1
1216 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1217 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1219 static void __init sun4v_ktsb_init(void)
1221 unsigned long ktsb_pa;
1223 /* First KTSB for PAGE_SIZE mappings. */
1224 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1226 switch (PAGE_SIZE) {
1229 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1230 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1234 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1235 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1239 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1240 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1243 case 4 * 1024 * 1024:
1244 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1245 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1249 ktsb_descr[0].assoc = 1;
1250 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1251 ktsb_descr[0].ctx_idx = 0;
1252 ktsb_descr[0].tsb_base = ktsb_pa;
1253 ktsb_descr[0].resv = 0;
1255 #ifndef CONFIG_DEBUG_PAGEALLOC
1256 /* Second KTSB for 4MB/256MB mappings. */
1257 ktsb_pa = (kern_base +
1258 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1260 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1261 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1262 HV_PGSZ_MASK_256MB);
1263 ktsb_descr[1].assoc = 1;
1264 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1265 ktsb_descr[1].ctx_idx = 0;
1266 ktsb_descr[1].tsb_base = ktsb_pa;
1267 ktsb_descr[1].resv = 0;
1271 void __cpuinit sun4v_ktsb_register(void)
1273 unsigned long pa, ret;
1275 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1277 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1279 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1280 "errors with %lx\n", pa, ret);
1285 /* paging_init() sets up the page tables */
1287 extern void central_probe(void);
1289 static unsigned long last_valid_pfn;
1290 pgd_t swapper_pg_dir[2048];
1292 static void sun4u_pgprot_init(void);
1293 static void sun4v_pgprot_init(void);
1295 /* Dummy function */
1296 void __init setup_per_cpu_areas(void)
1300 void __init paging_init(void)
1302 unsigned long end_pfn, pages_avail, shift, phys_base;
1303 unsigned long real_end, i;
1305 /* These build time checkes make sure that the dcache_dirty_cpu()
1306 * page->flags usage will work.
1308 * When a page gets marked as dcache-dirty, we store the
1309 * cpu number starting at bit 32 in the page->flags. Also,
1310 * functions like clear_dcache_dirty_cpu use the cpu mask
1311 * in 13-bit signed-immediate instruction fields.
1313 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1314 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1315 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1316 BUILD_BUG_ON(NR_CPUS > 4096);
1318 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1319 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1323 /* Invalidate both kernel TSBs. */
1324 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1325 #ifndef CONFIG_DEBUG_PAGEALLOC
1326 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1329 if (tlb_type == hypervisor)
1330 sun4v_pgprot_init();
1332 sun4u_pgprot_init();
1334 if (tlb_type == cheetah_plus ||
1335 tlb_type == hypervisor)
1338 if (tlb_type == hypervisor) {
1339 sun4v_patch_tlb_handlers();
1345 /* Find available physical memory... */
1346 read_obp_memory("available", &pavail[0], &pavail_ents);
1348 phys_base = 0xffffffffffffffffUL;
1349 for (i = 0; i < pavail_ents; i++) {
1350 phys_base = min(phys_base, pavail[i].phys_addr);
1351 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1354 lmb_reserve(kern_base, kern_size);
1356 find_ramdisk(phys_base);
1361 set_bit(0, mmu_context_bmap);
1363 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1365 real_end = (unsigned long)_end;
1366 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1367 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1368 num_kernel_image_mappings);
1370 /* Set kernel pgd to upper alias so physical page computations
1373 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1375 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1377 /* Now can init the kernel/bad page tables. */
1378 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1379 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1381 inherit_prom_mappings();
1383 read_obp_memory("reg", &pall[0], &pall_ents);
1387 /* Ok, we can use our TLB miss and window trap handlers safely. */
1392 if (tlb_type == hypervisor)
1393 sun4v_ktsb_register();
1395 /* Setup bootmem... */
1397 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1399 max_mapnr = last_valid_pfn;
1401 kernel_physical_mapping_init();
1403 real_setup_per_cpu_areas();
1405 prom_build_devicetree();
1407 if (tlb_type == hypervisor)
1411 unsigned long zones_size[MAX_NR_ZONES];
1412 unsigned long zholes_size[MAX_NR_ZONES];
1415 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1416 zones_size[znum] = zholes_size[znum] = 0;
1418 zones_size[ZONE_NORMAL] = end_pfn;
1419 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1421 free_area_init_node(0, &contig_page_data, zones_size,
1422 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1426 printk("Booting Linux...\n");
1432 static void __init taint_real_pages(void)
1436 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1438 /* Find changes discovered in the physmem available rescan and
1439 * reserve the lost portions in the bootmem maps.
1441 for (i = 0; i < pavail_ents; i++) {
1442 unsigned long old_start, old_end;
1444 old_start = pavail[i].phys_addr;
1445 old_end = old_start +
1447 while (old_start < old_end) {
1450 for (n = 0; n < pavail_rescan_ents; n++) {
1451 unsigned long new_start, new_end;
1453 new_start = pavail_rescan[n].phys_addr;
1454 new_end = new_start +
1455 pavail_rescan[n].reg_size;
1457 if (new_start <= old_start &&
1458 new_end >= (old_start + PAGE_SIZE)) {
1459 set_bit(old_start >> 22,
1460 sparc64_valid_addr_bitmap);
1464 reserve_bootmem(old_start, PAGE_SIZE, BOOTMEM_DEFAULT);
1467 old_start += PAGE_SIZE;
1472 int __init page_in_phys_avail(unsigned long paddr)
1478 for (i = 0; i < pavail_rescan_ents; i++) {
1479 unsigned long start, end;
1481 start = pavail_rescan[i].phys_addr;
1482 end = start + pavail_rescan[i].reg_size;
1484 if (paddr >= start && paddr < end)
1487 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1489 #ifdef CONFIG_BLK_DEV_INITRD
1490 if (paddr >= __pa(initrd_start) &&
1491 paddr < __pa(PAGE_ALIGN(initrd_end)))
1498 void __init mem_init(void)
1500 unsigned long codepages, datapages, initpages;
1501 unsigned long addr, last;
1504 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1506 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1507 if (sparc64_valid_addr_bitmap == NULL) {
1508 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1511 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1513 addr = PAGE_OFFSET + kern_base;
1514 last = PAGE_ALIGN(kern_size) + addr;
1515 while (addr < last) {
1516 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1522 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1524 /* We subtract one to account for the mem_map_zero page
1527 totalram_pages = num_physpages = free_all_bootmem() - 1;
1530 * Set up the zero page, mark it reserved, so that page count
1531 * is not manipulated when freeing the page from user ptes.
1533 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1534 if (mem_map_zero == NULL) {
1535 prom_printf("paging_init: Cannot alloc zero page.\n");
1538 SetPageReserved(mem_map_zero);
1540 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1541 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1542 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1543 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1544 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1545 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1547 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1548 nr_free_pages() << (PAGE_SHIFT-10),
1549 codepages << (PAGE_SHIFT-10),
1550 datapages << (PAGE_SHIFT-10),
1551 initpages << (PAGE_SHIFT-10),
1552 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1554 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1555 cheetah_ecache_flush_init();
1558 void free_initmem(void)
1560 unsigned long addr, initend;
1563 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1565 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1566 initend = (unsigned long)(__init_end) & PAGE_MASK;
1567 for (; addr < initend; addr += PAGE_SIZE) {
1572 ((unsigned long) __va(kern_base)) -
1573 ((unsigned long) KERNBASE));
1574 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1575 p = virt_to_page(page);
1577 ClearPageReserved(p);
1585 #ifdef CONFIG_BLK_DEV_INITRD
1586 void free_initrd_mem(unsigned long start, unsigned long end)
1589 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1590 for (; start < end; start += PAGE_SIZE) {
1591 struct page *p = virt_to_page(start);
1593 ClearPageReserved(p);
1602 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1603 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1604 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1605 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1606 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1607 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1609 pgprot_t PAGE_KERNEL __read_mostly;
1610 EXPORT_SYMBOL(PAGE_KERNEL);
1612 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1613 pgprot_t PAGE_COPY __read_mostly;
1615 pgprot_t PAGE_SHARED __read_mostly;
1616 EXPORT_SYMBOL(PAGE_SHARED);
1618 pgprot_t PAGE_EXEC __read_mostly;
1619 unsigned long pg_iobits __read_mostly;
1621 unsigned long _PAGE_IE __read_mostly;
1622 EXPORT_SYMBOL(_PAGE_IE);
1624 unsigned long _PAGE_E __read_mostly;
1625 EXPORT_SYMBOL(_PAGE_E);
1627 unsigned long _PAGE_CACHE __read_mostly;
1628 EXPORT_SYMBOL(_PAGE_CACHE);
1630 #ifdef CONFIG_SPARSEMEM_VMEMMAP
1632 #define VMEMMAP_CHUNK_SHIFT 22
1633 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1634 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1635 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1637 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1638 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1639 unsigned long vmemmap_table[VMEMMAP_SIZE];
1641 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
1643 unsigned long vstart = (unsigned long) start;
1644 unsigned long vend = (unsigned long) (start + nr);
1645 unsigned long phys_start = (vstart - VMEMMAP_BASE);
1646 unsigned long phys_end = (vend - VMEMMAP_BASE);
1647 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
1648 unsigned long end = VMEMMAP_ALIGN(phys_end);
1649 unsigned long pte_base;
1651 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1652 _PAGE_CP_4U | _PAGE_CV_4U |
1653 _PAGE_P_4U | _PAGE_W_4U);
1654 if (tlb_type == hypervisor)
1655 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1656 _PAGE_CP_4V | _PAGE_CV_4V |
1657 _PAGE_P_4V | _PAGE_W_4V);
1659 for (; addr < end; addr += VMEMMAP_CHUNK) {
1660 unsigned long *vmem_pp =
1661 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
1664 if (!(*vmem_pp & _PAGE_VALID)) {
1665 block = vmemmap_alloc_block(1UL << 22, node);
1669 *vmem_pp = pte_base | __pa(block);
1671 printk(KERN_INFO "[%p-%p] page_structs=%lu "
1672 "node=%d entry=%lu/%lu\n", start, block, nr,
1674 addr >> VMEMMAP_CHUNK_SHIFT,
1675 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
1680 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
1682 static void prot_init_common(unsigned long page_none,
1683 unsigned long page_shared,
1684 unsigned long page_copy,
1685 unsigned long page_readonly,
1686 unsigned long page_exec_bit)
1688 PAGE_COPY = __pgprot(page_copy);
1689 PAGE_SHARED = __pgprot(page_shared);
1691 protection_map[0x0] = __pgprot(page_none);
1692 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1693 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1694 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1695 protection_map[0x4] = __pgprot(page_readonly);
1696 protection_map[0x5] = __pgprot(page_readonly);
1697 protection_map[0x6] = __pgprot(page_copy);
1698 protection_map[0x7] = __pgprot(page_copy);
1699 protection_map[0x8] = __pgprot(page_none);
1700 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1701 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1702 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1703 protection_map[0xc] = __pgprot(page_readonly);
1704 protection_map[0xd] = __pgprot(page_readonly);
1705 protection_map[0xe] = __pgprot(page_shared);
1706 protection_map[0xf] = __pgprot(page_shared);
1709 static void __init sun4u_pgprot_init(void)
1711 unsigned long page_none, page_shared, page_copy, page_readonly;
1712 unsigned long page_exec_bit;
1714 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1715 _PAGE_CACHE_4U | _PAGE_P_4U |
1716 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1718 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1719 _PAGE_CACHE_4U | _PAGE_P_4U |
1720 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1721 _PAGE_EXEC_4U | _PAGE_L_4U);
1722 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1724 _PAGE_IE = _PAGE_IE_4U;
1725 _PAGE_E = _PAGE_E_4U;
1726 _PAGE_CACHE = _PAGE_CACHE_4U;
1728 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1729 __ACCESS_BITS_4U | _PAGE_E_4U);
1731 #ifdef CONFIG_DEBUG_PAGEALLOC
1732 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1735 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1738 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1739 _PAGE_P_4U | _PAGE_W_4U);
1741 /* XXX Should use 256MB on Panther. XXX */
1742 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1744 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1745 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1746 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1747 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1750 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1751 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1752 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1753 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1754 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1755 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1756 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1758 page_exec_bit = _PAGE_EXEC_4U;
1760 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1764 static void __init sun4v_pgprot_init(void)
1766 unsigned long page_none, page_shared, page_copy, page_readonly;
1767 unsigned long page_exec_bit;
1769 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1770 _PAGE_CACHE_4V | _PAGE_P_4V |
1771 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1773 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1774 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1776 _PAGE_IE = _PAGE_IE_4V;
1777 _PAGE_E = _PAGE_E_4V;
1778 _PAGE_CACHE = _PAGE_CACHE_4V;
1780 #ifdef CONFIG_DEBUG_PAGEALLOC
1781 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1784 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1787 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1788 _PAGE_P_4V | _PAGE_W_4V);
1790 #ifdef CONFIG_DEBUG_PAGEALLOC
1791 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1794 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1797 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1798 _PAGE_P_4V | _PAGE_W_4V);
1800 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1801 __ACCESS_BITS_4V | _PAGE_E_4V);
1803 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1804 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1805 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1806 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1807 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1809 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1810 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1811 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1812 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1813 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1814 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1815 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1817 page_exec_bit = _PAGE_EXEC_4V;
1819 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1823 unsigned long pte_sz_bits(unsigned long sz)
1825 if (tlb_type == hypervisor) {
1829 return _PAGE_SZ8K_4V;
1831 return _PAGE_SZ64K_4V;
1833 return _PAGE_SZ512K_4V;
1834 case 4 * 1024 * 1024:
1835 return _PAGE_SZ4MB_4V;
1841 return _PAGE_SZ8K_4U;
1843 return _PAGE_SZ64K_4U;
1845 return _PAGE_SZ512K_4U;
1846 case 4 * 1024 * 1024:
1847 return _PAGE_SZ4MB_4U;
1852 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1856 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1857 pte_val(pte) |= (((unsigned long)space) << 32);
1858 pte_val(pte) |= pte_sz_bits(page_size);
1863 static unsigned long kern_large_tte(unsigned long paddr)
1867 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1868 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1869 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1870 if (tlb_type == hypervisor)
1871 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1872 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1873 _PAGE_EXEC_4V | _PAGE_W_4V);
1878 /* If not locked, zap it. */
1879 void __flush_tlb_all(void)
1881 unsigned long pstate;
1884 __asm__ __volatile__("flushw\n\t"
1885 "rdpr %%pstate, %0\n\t"
1886 "wrpr %0, %1, %%pstate"
1889 if (tlb_type == hypervisor) {
1890 sun4v_mmu_demap_all();
1891 } else if (tlb_type == spitfire) {
1892 for (i = 0; i < 64; i++) {
1893 /* Spitfire Errata #32 workaround */
1894 /* NOTE: Always runs on spitfire, so no
1895 * cheetah+ page size encodings.
1897 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1901 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1903 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1904 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1907 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1908 spitfire_put_dtlb_data(i, 0x0UL);
1911 /* Spitfire Errata #32 workaround */
1912 /* NOTE: Always runs on spitfire, so no
1913 * cheetah+ page size encodings.
1915 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1919 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1921 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1922 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1925 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1926 spitfire_put_itlb_data(i, 0x0UL);
1929 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1930 cheetah_flush_dtlb_all();
1931 cheetah_flush_itlb_all();
1933 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1937 #ifdef CONFIG_MEMORY_HOTPLUG
1939 void online_page(struct page *page)
1941 ClearPageReserved(page);
1942 init_page_count(page);
1948 #endif /* CONFIG_MEMORY_HOTPLUG */