arch/sparc64/mm/init.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/poison.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26 #include <linux/percpu.h>
  27 #include <linux/lmb.h>
  28 #include <linux/mmzone.h>
  29
  30 #include <asm/head.h>
  31 #include <asm/system.h>
  32 #include <asm/page.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/oplib.h>
  36 #include <asm/iommu.h>
  37 #include <asm/io.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/dma.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/spitfire.h>
  45 #include <asm/sections.h>
  46 #include <asm/tsb.h>
  47 #include <asm/hypervisor.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/cpudata.h>
  51 #include <asm/irq.h>
  52
  53 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
  54 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
  55 #define KPTE_BITMAP_BYTES       \
  56         ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
  57
  58 unsigned long kern_linear_pte_xor[2] __read_mostly;
  59
  60 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
  61  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
  62  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
  63  */
  64 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  65
  66 #ifndef CONFIG_DEBUG_PAGEALLOC
  67 /* A special kernel TSB for 4MB and 256MB linear mappings.
  68  * Space is allocated for this right after the trap table
  69  * in arch/sparc64/kernel/head.S
  70  */
  71 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  72 #endif
  73
  74 #define MAX_BANKS       32
  75
  76 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  77 static int pavail_ents __initdata;
  78
  79 static int cmp_p64(const void *a, const void *b)
  80 {
  81         const struct linux_prom64_registers *x = a, *y = b;
  82
  83         if (x->phys_addr > y->phys_addr)
  84                 return 1;
  85         if (x->phys_addr < y->phys_addr)
  86                 return -1;
  87         return 0;
  88 }
  89
  90 static void __init read_obp_memory(const char *property,
  91                                    struct linux_prom64_registers *regs,
  92                                    int *num_ents)
  93 {
  94         int node = prom_finddevice("/memory");
  95         int prop_size = prom_getproplen(node, property);
  96         int ents, ret, i;
  97
  98         ents = prop_size / sizeof(struct linux_prom64_registers);
  99         if (ents > MAX_BANKS) {
 100                 prom_printf("The machine has more %s property entries than "
 101                             "this kernel can support (%d).\n",
 102                             property, MAX_BANKS);
 103                 prom_halt();
 104         }
 105
 106         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 107         if (ret == -1) {
 108                 prom_printf("Couldn't get %s property from /memory.\n");
 109                 prom_halt();
 110         }
 111
 112         /* Sanitize what we got from the firmware, by page aligning
 113          * everything.
 114          */
 115         for (i = 0; i < ents; i++) {
 116                 unsigned long base, size;
 117
 118                 base = regs[i].phys_addr;
 119                 size = regs[i].reg_size;
 120
 121                 size &= PAGE_MASK;
 122                 if (base & ~PAGE_MASK) {
 123                         unsigned long new_base = PAGE_ALIGN(base);
 124
 125                         size -= new_base - base;
 126                         if ((long) size < 0L)
 127                                 size = 0UL;
 128                         base = new_base;
 129                 }
 130                 if (size == 0UL) {
 131                         /* If it is empty, simply get rid of it.
 132                          * This simplifies the logic of the other
 133                          * functions that process these arrays.
 134                          */
 135                         memmove(&regs[i], &regs[i + 1],
 136                                 (ents - i - 1) * sizeof(regs[0]));
 137                         i--;
 138                         ents--;
 139                         continue;
 140                 }
 141                 regs[i].phys_addr = base;
 142                 regs[i].reg_size = size;
 143         }
 144
 145         *num_ents = ents;
 146
 147         sort(regs, ents, sizeof(struct linux_prom64_registers),
 148              cmp_p64, NULL);
 149 }
 150
 151 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 152
 153 /* Kernel physical address base and size in bytes.  */
 154 unsigned long kern_base __read_mostly;
 155 unsigned long kern_size __read_mostly;
 156
 157 /* Initial ramdisk setup */
 158 extern unsigned long sparc_ramdisk_image64;
 159 extern unsigned int sparc_ramdisk_image;
 160 extern unsigned int sparc_ramdisk_size;
 161
 162 struct page *mem_map_zero __read_mostly;
 163 EXPORT_SYMBOL(mem_map_zero);
 164
 165 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 166
 167 unsigned long sparc64_kern_pri_context __read_mostly;
 168 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 169 unsigned long sparc64_kern_sec_context __read_mostly;
 170
 171 int num_kernel_image_mappings;
 172
 173 #ifdef CONFIG_DEBUG_DCFLUSH
 174 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 175 #ifdef CONFIG_SMP
 176 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 177 #endif
 178 #endif
 179
 180 inline void flush_dcache_page_impl(struct page *page)
 181 {
 182         BUG_ON(tlb_type == hypervisor);
 183 #ifdef CONFIG_DEBUG_DCFLUSH
 184         atomic_inc(&dcpage_flushes);
 185 #endif
 186
 187 #ifdef DCACHE_ALIASING_POSSIBLE
 188         __flush_dcache_page(page_address(page),
 189                             ((tlb_type == spitfire) &&
 190                              page_mapping(page) != NULL));
 191 #else
 192         if (page_mapping(page) != NULL &&
 193             tlb_type == spitfire)
 194                 __flush_icache_page(__pa(page_address(page)));
 195 #endif
 196 }
 197
 198 #define PG_dcache_dirty         PG_arch_1
 199 #define PG_dcache_cpu_shift     32UL
 200 #define PG_dcache_cpu_mask      \
 201         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 202
 203 #define dcache_dirty_cpu(page) \
 204         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 205
 206 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 207 {
 208         unsigned long mask = this_cpu;
 209         unsigned long non_cpu_bits;
 210
 211         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 212         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 213
 214         __asm__ __volatile__("1:\n\t"
 215                              "ldx       [%2], %%g7\n\t"
 216                              "and       %%g7, %1, %%g1\n\t"
 217                              "or        %%g1, %0, %%g1\n\t"
 218                              "casx      [%2], %%g7, %%g1\n\t"
 219                              "cmp       %%g7, %%g1\n\t"
 220                              "membar    #StoreLoad | #StoreStore\n\t"
 221                              "bne,pn    %%xcc, 1b\n\t"
 222                              " nop"
 223                              : /* no outputs */
 224                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 225                              : "g1", "g7");
 226 }
 227
 228 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 229 {
 230         unsigned long mask = (1UL << PG_dcache_dirty);
 231
 232         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 233                              "1:\n\t"
 234                              "ldx       [%2], %%g7\n\t"
 235                              "srlx      %%g7, %4, %%g1\n\t"
 236                              "and       %%g1, %3, %%g1\n\t"
 237                              "cmp       %%g1, %0\n\t"
 238                              "bne,pn    %%icc, 2f\n\t"
 239                              " andn     %%g7, %1, %%g1\n\t"
 240                              "casx      [%2], %%g7, %%g1\n\t"
 241                              "cmp       %%g7, %%g1\n\t"
 242                              "membar    #StoreLoad | #StoreStore\n\t"
 243                              "bne,pn    %%xcc, 1b\n\t"
 244                              " nop\n"
 245                              "2:"
 246                              : /* no outputs */
 247                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 248                                "i" (PG_dcache_cpu_mask),
 249                                "i" (PG_dcache_cpu_shift)
 250                              : "g1", "g7");
 251 }
 252
 253 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 254 {
 255         unsigned long tsb_addr = (unsigned long) ent;
 256
 257         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 258                 tsb_addr = __pa(tsb_addr);
 259
 260         __tsb_insert(tsb_addr, tag, pte);
 261 }
 262
 263 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 264 unsigned long _PAGE_SZBITS __read_mostly;
 265
 266 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 267 {
 268         struct mm_struct *mm;
 269         struct tsb *tsb;
 270         unsigned long tag, flags;
 271         unsigned long tsb_index, tsb_hash_shift;
 272
 273         if (tlb_type != hypervisor) {
 274                 unsigned long pfn = pte_pfn(pte);
 275                 unsigned long pg_flags;
 276                 struct page *page;
 277
 278                 if (pfn_valid(pfn) &&
 279                     (page = pfn_to_page(pfn), page_mapping(page)) &&
 280                     ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 281                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 282                                    PG_dcache_cpu_mask);
 283                         int this_cpu = get_cpu();
 284
 285                         /* This is just to optimize away some function calls
 286                          * in the SMP case.
 287                          */
 288                         if (cpu == this_cpu)
 289                                 flush_dcache_page_impl(page);
 290                         else
 291                                 smp_flush_dcache_page_impl(page, cpu);
 292
 293                         clear_dcache_dirty_cpu(page, cpu);
 294
 295                         put_cpu();
 296                 }
 297         }
 298
 299         mm = vma->vm_mm;
 300
 301         tsb_index = MM_TSB_BASE;
 302         tsb_hash_shift = PAGE_SHIFT;
 303
 304         spin_lock_irqsave(&mm->context.lock, flags);
 305
 306 #ifdef CONFIG_HUGETLB_PAGE
 307         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
 308                 if ((tlb_type == hypervisor &&
 309                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 310                     (tlb_type != hypervisor &&
 311                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
 312                         tsb_index = MM_TSB_HUGE;
 313                         tsb_hash_shift = HPAGE_SHIFT;
 314                 }
 315         }
 316 #endif
 317
 318         tsb = mm->context.tsb_block[tsb_index].tsb;
 319         tsb += ((address >> tsb_hash_shift) &
 320                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 321         tag = (address >> 22UL);
 322         tsb_insert(tsb, tag, pte_val(pte));
 323
 324         spin_unlock_irqrestore(&mm->context.lock, flags);
 325 }
 326
 327 void flush_dcache_page(struct page *page)
 328 {
 329         struct address_space *mapping;
 330         int this_cpu;
 331
 332         if (tlb_type == hypervisor)
 333                 return;
 334
 335         /* Do not bother with the expensive D-cache flush if it
 336          * is merely the zero page.  The 'bigcore' testcase in GDB
 337          * causes this case to run millions of times.
 338          */
 339         if (page == ZERO_PAGE(0))
 340                 return;
 341
 342         this_cpu = get_cpu();
 343
 344         mapping = page_mapping(page);
 345         if (mapping && !mapping_mapped(mapping)) {
 346                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 347                 if (dirty) {
 348                         int dirty_cpu = dcache_dirty_cpu(page);
 349
 350                         if (dirty_cpu == this_cpu)
 351                                 goto out;
 352                         smp_flush_dcache_page_impl(page, dirty_cpu);
 353                 }
 354                 set_dcache_dirty(page, this_cpu);
 355         } else {
 356                 /* We could delay the flush for the !page_mapping
 357                  * case too.  But that case is for exec env/arg
 358                  * pages and those are %99 certainly going to get
 359                  * faulted into the tlb (and thus flushed) anyways.
 360                  */
 361                 flush_dcache_page_impl(page);
 362         }
 363
 364 out:
 365         put_cpu();
 366 }
 367
 368 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 369 {
 370         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 371         if (tlb_type == spitfire) {
 372                 unsigned long kaddr;
 373
 374                 /* This code only runs on Spitfire cpus so this is
 375                  * why we can assume _PAGE_PADDR_4U.
 376                  */
 377                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 378                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 379
 380                         if (kaddr >= PAGE_OFFSET)
 381                                 paddr = kaddr & mask;
 382                         else {
 383                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 384                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 385                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 386                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 387
 388                                 paddr = pte_val(*ptep) & mask;
 389                         }
 390                         __flush_icache_page(paddr);
 391                 }
 392         }
 393 }
 394
 395 void mmu_info(struct seq_file *m)
 396 {
 397         if (tlb_type == cheetah)
 398                 seq_printf(m, "MMU Type\t: Cheetah\n");
 399         else if (tlb_type == cheetah_plus)
 400                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 401         else if (tlb_type == spitfire)
 402                 seq_printf(m, "MMU Type\t: Spitfire\n");
 403         else if (tlb_type == hypervisor)
 404                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 405         else
 406                 seq_printf(m, "MMU Type\t: ???\n");
 407
 408 #ifdef CONFIG_DEBUG_DCFLUSH
 409         seq_printf(m, "DCPageFlushes\t: %d\n",
 410                    atomic_read(&dcpage_flushes));
 411 #ifdef CONFIG_SMP
 412         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 413                    atomic_read(&dcpage_flushes_xcall));
 414 #endif /* CONFIG_SMP */
 415 #endif /* CONFIG_DEBUG_DCFLUSH */
 416 }
 417
 418 struct linux_prom_translation {
 419         unsigned long virt;
 420         unsigned long size;
 421         unsigned long data;
 422 };
 423
 424 /* Exported for kernel TLB miss handling in ktlb.S */
 425 struct linux_prom_translation prom_trans[512] __read_mostly;
 426 unsigned int prom_trans_ents __read_mostly;
 427
 428 /* Exported for SMP bootup purposes. */
 429 unsigned long kern_locked_tte_data;
 430
 431 /* The obp translations are saved based on 8k pagesize, since obp can
 432  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 433  * HI_OBP_ADDRESS range are handled in ktlb.S.
 434  */
 435 static inline int in_obp_range(unsigned long vaddr)
 436 {
 437         return (vaddr >= LOW_OBP_ADDRESS &&
 438                 vaddr < HI_OBP_ADDRESS);
 439 }
 440
 441 static int cmp_ptrans(const void *a, const void *b)
 442 {
 443         const struct linux_prom_translation *x = a, *y = b;
 444
 445         if (x->virt > y->virt)
 446                 return 1;
 447         if (x->virt < y->virt)
 448                 return -1;
 449         return 0;
 450 }
 451
 452 /* Read OBP translations property into 'prom_trans[]'.  */
 453 static void __init read_obp_translations(void)
 454 {
 455         int n, node, ents, first, last, i;
 456
 457         node = prom_finddevice("/virtual-memory");
 458         n = prom_getproplen(node, "translations");
 459         if (unlikely(n == 0 || n == -1)) {
 460                 prom_printf("prom_mappings: Couldn't get size.\n");
 461                 prom_halt();
 462         }
 463         if (unlikely(n > sizeof(prom_trans))) {
 464                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 465                 prom_halt();
 466         }
 467
 468         if ((n = prom_getproperty(node, "translations",
 469                                   (char *)&prom_trans[0],
 470                                   sizeof(prom_trans))) == -1) {
 471                 prom_printf("prom_mappings: Couldn't get property.\n");
 472                 prom_halt();
 473         }
 474
 475         n = n / sizeof(struct linux_prom_translation);
 476
 477         ents = n;
 478
 479         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 480              cmp_ptrans, NULL);
 481
 482         /* Now kick out all the non-OBP entries.  */
 483         for (i = 0; i < ents; i++) {
 484                 if (in_obp_range(prom_trans[i].virt))
 485                         break;
 486         }
 487         first = i;
 488         for (; i < ents; i++) {
 489                 if (!in_obp_range(prom_trans[i].virt))
 490                         break;
 491         }
 492         last = i;
 493
 494         for (i = 0; i < (last - first); i++) {
 495                 struct linux_prom_translation *src = &prom_trans[i + first];
 496                 struct linux_prom_translation *dest = &prom_trans[i];
 497
 498                 *dest = *src;
 499         }
 500         for (; i < ents; i++) {
 501                 struct linux_prom_translation *dest = &prom_trans[i];
 502                 dest->virt = dest->size = dest->data = 0x0UL;
 503         }
 504
 505         prom_trans_ents = last - first;
 506
 507         if (tlb_type == spitfire) {
 508                 /* Clear diag TTE bits. */
 509                 for (i = 0; i < prom_trans_ents; i++)
 510                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 511         }
 512 }
 513
 514 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 515                                        unsigned long pte,
 516                                        unsigned long mmu)
 517 {
 518         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 519
 520         if (ret != 0) {
 521                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
 522                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 523                 prom_halt();
 524         }
 525 }
 526
 527 static unsigned long kern_large_tte(unsigned long paddr);
 528
 529 static void __init remap_kernel(void)
 530 {
 531         unsigned long phys_page, tte_vaddr, tte_data;
 532         int i, tlb_ent = sparc64_highest_locked_tlbent();
 533
 534         tte_vaddr = (unsigned long) KERNBASE;
 535         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 536         tte_data = kern_large_tte(phys_page);
 537
 538         kern_locked_tte_data = tte_data;
 539
 540         /* Now lock us into the TLBs via Hypervisor or OBP. */
 541         if (tlb_type == hypervisor) {
 542                 for (i = 0; i < num_kernel_image_mappings; i++) {
 543                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 544                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 545                         tte_vaddr += 0x400000;
 546                         tte_data += 0x400000;
 547                 }
 548         } else {
 549                 for (i = 0; i < num_kernel_image_mappings; i++) {
 550                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 551                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 552                         tte_vaddr += 0x400000;
 553                         tte_data += 0x400000;
 554                 }
 555                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 556         }
 557         if (tlb_type == cheetah_plus) {
 558                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 559                                             CTX_CHEETAH_PLUS_NUC);
 560                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 561                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 562         }
 563 }
 564
 565
 566 static void __init inherit_prom_mappings(void)
 567 {
 568         /* Now fixup OBP's idea about where we really are mapped. */
 569         printk("Remapping the kernel... ");
 570         remap_kernel();
 571         printk("done.\n");
 572 }
 573
 574 void prom_world(int enter)
 575 {
 576         if (!enter)
 577                 set_fs((mm_segment_t) { get_thread_current_ds() });
 578
 579         __asm__ __volatile__("flushw");
 580 }
 581
 582 void __flush_dcache_range(unsigned long start, unsigned long end)
 583 {
 584         unsigned long va;
 585
 586         if (tlb_type == spitfire) {
 587                 int n = 0;
 588
 589                 for (va = start; va < end; va += 32) {
 590                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 591                         if (++n >= 512)
 592                                 break;
 593                 }
 594         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 595                 start = __pa(start);
 596                 end = __pa(end);
 597                 for (va = start; va < end; va += 32)
 598                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 599                                              "membar #Sync"
 600                                              : /* no outputs */
 601                                              : "r" (va),
 602                                                "i" (ASI_DCACHE_INVALIDATE));
 603         }
 604 }
 605
 606 /* get_new_mmu_context() uses "cache + 1".  */
 607 DEFINE_SPINLOCK(ctx_alloc_lock);
 608 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 609 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 610 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 611 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 612
 613 /* Caller does TLB context flushing on local CPU if necessary.
 614  * The caller also ensures that CTX_VALID(mm->context) is false.
 615  *
 616  * We must be careful about boundary cases so that we never
 617  * let the user have CTX 0 (nucleus) or we ever use a CTX
 618  * version of zero (and thus NO_CONTEXT would not be caught
 619  * by version mis-match tests in mmu_context.h).
 620  *
 621  * Always invoked with interrupts disabled.
 622  */
 623 void get_new_mmu_context(struct mm_struct *mm)
 624 {
 625         unsigned long ctx, new_ctx;
 626         unsigned long orig_pgsz_bits;
 627         unsigned long flags;
 628         int new_version;
 629
 630         spin_lock_irqsave(&ctx_alloc_lock, flags);
 631         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 632         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 633         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 634         new_version = 0;
 635         if (new_ctx >= (1 << CTX_NR_BITS)) {
 636                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 637                 if (new_ctx >= ctx) {
 638                         int i;
 639                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 640                                 CTX_FIRST_VERSION;
 641                         if (new_ctx == 1)
 642                                 new_ctx = CTX_FIRST_VERSION;
 643
 644                         /* Don't call memset, for 16 entries that's just
 645                          * plain silly...
 646                          */
 647                         mmu_context_bmap[0] = 3;
 648                         mmu_context_bmap[1] = 0;
 649                         mmu_context_bmap[2] = 0;
 650                         mmu_context_bmap[3] = 0;
 651                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 652                                 mmu_context_bmap[i + 0] = 0;
 653                                 mmu_context_bmap[i + 1] = 0;
 654                                 mmu_context_bmap[i + 2] = 0;
 655                                 mmu_context_bmap[i + 3] = 0;
 656                         }
 657                         new_version = 1;
 658                         goto out;
 659                 }
 660         }
 661         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 662         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 663 out:
 664         tlb_context_cache = new_ctx;
 665         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 666         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
 667
 668         if (unlikely(new_version))
 669                 smp_new_mmu_context_version();
 670 }
 671
 672 static int numa_enabled = 1;
 673 static int numa_debug;
 674
 675 static int __init early_numa(char *p)
 676 {
 677         if (!p)
 678                 return 0;
 679
 680         if (strstr(p, "off"))
 681                 numa_enabled = 0;
 682
 683         if (strstr(p, "debug"))
 684                 numa_debug = 1;
 685
 686         return 0;
 687 }
 688 early_param("numa", early_numa);
 689
 690 #define numadbg(f, a...) \
 691 do {    if (numa_debug) \
 692                 printk(KERN_INFO f, ## a); \
 693 } while (0)
 694
 695 static void __init find_ramdisk(unsigned long phys_base)
 696 {
 697 #ifdef CONFIG_BLK_DEV_INITRD
 698         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 699                 unsigned long ramdisk_image;
 700
 701                 /* Older versions of the bootloader only supported a
 702                  * 32-bit physical address for the ramdisk image
 703                  * location, stored at sparc_ramdisk_image.  Newer
 704                  * SILO versions set sparc_ramdisk_image to zero and
 705                  * provide a full 64-bit physical address at
 706                  * sparc_ramdisk_image64.
 707                  */
 708                 ramdisk_image = sparc_ramdisk_image;
 709                 if (!ramdisk_image)
 710                         ramdisk_image = sparc_ramdisk_image64;
 711
 712                 /* Another bootloader quirk.  The bootloader normalizes
 713                  * the physical address to KERNBASE, so we have to
 714                  * factor that back out and add in the lowest valid
 715                  * physical page address to get the true physical address.
 716                  */
 717                 ramdisk_image -= KERNBASE;
 718                 ramdisk_image += phys_base;
 719
 720                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 721                         ramdisk_image, sparc_ramdisk_size);
 722
 723                 initrd_start = ramdisk_image;
 724                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 725
 726                 lmb_reserve(initrd_start, sparc_ramdisk_size);
 727
 728                 initrd_start += PAGE_OFFSET;
 729                 initrd_end += PAGE_OFFSET;
 730         }
 731 #endif
 732 }
 733
 734 struct node_mem_mask {
 735         unsigned long mask;
 736         unsigned long val;
 737         unsigned long bootmem_paddr;
 738 };
 739 static struct node_mem_mask node_masks[MAX_NUMNODES];
 740 static int num_node_masks;
 741
 742 int numa_cpu_lookup_table[NR_CPUS];
 743 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 744
 745 #ifdef CONFIG_NEED_MULTIPLE_NODES
 746
 747 struct mdesc_mblock {
 748         u64     base;
 749         u64     size;
 750         u64     offset; /* RA-to-PA */
 751 };
 752 static struct mdesc_mblock *mblocks;
 753 static int num_mblocks;
 754
 755 static unsigned long ra_to_pa(unsigned long addr)
 756 {
 757         int i;
 758
 759         for (i = 0; i < num_mblocks; i++) {
 760                 struct mdesc_mblock *m = &mblocks[i];
 761
 762                 if (addr >= m->base &&
 763                     addr < (m->base + m->size)) {
 764                         addr += m->offset;
 765                         break;
 766                 }
 767         }
 768         return addr;
 769 }
 770
 771 static int find_node(unsigned long addr)
 772 {
 773         int i;
 774
 775         addr = ra_to_pa(addr);
 776         for (i = 0; i < num_node_masks; i++) {
 777                 struct node_mem_mask *p = &node_masks[i];
 778
 779                 if ((addr & p->mask) == p->val)
 780                         return i;
 781         }
 782         return -1;
 783 }
 784
 785 static unsigned long nid_range(unsigned long start, unsigned long end,
 786                                int *nid)
 787 {
 788         *nid = find_node(start);
 789         start += PAGE_SIZE;
 790         while (start < end) {
 791                 int n = find_node(start);
 792
 793                 if (n != *nid)
 794                         break;
 795                 start += PAGE_SIZE;
 796         }
 797
 798         if (start > end)
 799                 start = end;
 800
 801         return start;
 802 }
 803 #else
 804 static unsigned long nid_range(unsigned long start, unsigned long end,
 805                                int *nid)
 806 {
 807         *nid = 0;
 808         return end;
 809 }
 810 #endif
 811
 812 /* This must be invoked after performing all of the necessary
 813  * add_active_range() calls for 'nid'.  We need to be able to get
 814  * correct data from get_pfn_range_for_nid().
 815  */
 816 static void __init allocate_node_data(int nid)
 817 {
 818         unsigned long paddr, num_pages, start_pfn, end_pfn;
 819         struct pglist_data *p;
 820
 821 #ifdef CONFIG_NEED_MULTIPLE_NODES
 822         paddr = lmb_alloc_nid(sizeof(struct pglist_data),
 823                               SMP_CACHE_BYTES, nid, nid_range);
 824         if (!paddr) {
 825                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 826                 prom_halt();
 827         }
 828         NODE_DATA(nid) = __va(paddr);
 829         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 830
 831         NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
 832 #endif
 833
 834         p = NODE_DATA(nid);
 835
 836         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 837         p->node_start_pfn = start_pfn;
 838         p->node_spanned_pages = end_pfn - start_pfn;
 839
 840         if (p->node_spanned_pages) {
 841                 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
 842
 843                 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
 844                                       nid_range);
 845                 if (!paddr) {
 846                         prom_printf("Cannot allocate bootmap for nid[%d]\n",
 847                                   nid);
 848                         prom_halt();
 849                 }
 850                 node_masks[nid].bootmem_paddr = paddr;
 851         }
 852 }
 853
 854 static void init_node_masks_nonnuma(void)
 855 {
 856         int i;
 857
 858         numadbg("Initializing tables for non-numa.\n");
 859
 860         node_masks[0].mask = node_masks[0].val = 0;
 861         num_node_masks = 1;
 862
 863         for (i = 0; i < NR_CPUS; i++)
 864                 numa_cpu_lookup_table[i] = 0;
 865
 866         numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
 867 }
 868
 869 #ifdef CONFIG_NEED_MULTIPLE_NODES
 870 struct pglist_data *node_data[MAX_NUMNODES];
 871
 872 EXPORT_SYMBOL(numa_cpu_lookup_table);
 873 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 874 EXPORT_SYMBOL(node_data);
 875
 876 struct mdesc_mlgroup {
 877         u64     node;
 878         u64     latency;
 879         u64     match;
 880         u64     mask;
 881 };
 882 static struct mdesc_mlgroup *mlgroups;
 883 static int num_mlgroups;
 884
 885 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 886                                    u32 cfg_handle)
 887 {
 888         u64 arc;
 889
 890         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 891                 u64 target = mdesc_arc_target(md, arc);
 892                 const u64 *val;
 893
 894                 val = mdesc_get_property(md, target,
 895                                          "cfg-handle", NULL);
 896                 if (val && *val == cfg_handle)
 897                         return 0;
 898         }
 899         return -ENODEV;
 900 }
 901
 902 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 903                                     u32 cfg_handle)
 904 {
 905         u64 arc, candidate, best_latency = ~(u64)0;
 906
 907         candidate = MDESC_NODE_NULL;
 908         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 909                 u64 target = mdesc_arc_target(md, arc);
 910                 const char *name = mdesc_node_name(md, target);
 911                 const u64 *val;
 912
 913                 if (strcmp(name, "pio-latency-group"))
 914                         continue;
 915
 916                 val = mdesc_get_property(md, target, "latency", NULL);
 917                 if (!val)
 918                         continue;
 919
 920                 if (*val < best_latency) {
 921                         candidate = target;
 922                         best_latency = *val;
 923                 }
 924         }
 925
 926         if (candidate == MDESC_NODE_NULL)
 927                 return -ENODEV;
 928
 929         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 930 }
 931
 932 int of_node_to_nid(struct device_node *dp)
 933 {
 934         const struct linux_prom64_registers *regs;
 935         struct mdesc_handle *md;
 936         u32 cfg_handle;
 937         int count, nid;
 938         u64 grp;
 939
 940         /* This is the right thing to do on currently supported
 941          * SUN4U NUMA platforms as well, as the PCI controller does
 942          * not sit behind any particular memory controller.
 943          */
 944         if (!mlgroups)
 945                 return -1;
 946
 947         regs = of_get_property(dp, "reg", NULL);
 948         if (!regs)
 949                 return -1;
 950
 951         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 952
 953         md = mdesc_grab();
 954
 955         count = 0;
 956         nid = -1;
 957         mdesc_for_each_node_by_name(md, grp, "group") {
 958                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
 959                         nid = count;
 960                         break;
 961                 }
 962                 count++;
 963         }
 964
 965         mdesc_release(md);
 966
 967         return nid;
 968 }
 969
 970 static void add_node_ranges(void)
 971 {
 972         int i;
 973
 974         for (i = 0; i < lmb.memory.cnt; i++) {
 975                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
 976                 unsigned long start, end;
 977
 978                 start = lmb.memory.region[i].base;
 979                 end = start + size;
 980                 while (start < end) {
 981                         unsigned long this_end;
 982                         int nid;
 983
 984                         this_end = nid_range(start, end, &nid);
 985
 986                         numadbg("Adding active range nid[%d] "
 987                                 "start[%lx] end[%lx]\n",
 988                                 nid, start, this_end);
 989
 990                         add_active_range(nid,
 991                                          start >> PAGE_SHIFT,
 992                                          this_end >> PAGE_SHIFT);
 993
 994                         start = this_end;
 995                 }
 996         }
 997 }
 998
 999 static int __init grab_mlgroups(struct mdesc_handle *md)
1000 {
1001         unsigned long paddr;
1002         int count = 0;
1003         u64 node;
1004
1005         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1006                 count++;
1007         if (!count)
1008                 return -ENOENT;
1009
1010         paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1011                           SMP_CACHE_BYTES);
1012         if (!paddr)
1013                 return -ENOMEM;
1014
1015         mlgroups = __va(paddr);
1016         num_mlgroups = count;
1017
1018         count = 0;
1019         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1020                 struct mdesc_mlgroup *m = &mlgroups[count++];
1021                 const u64 *val;
1022
1023                 m->node = node;
1024
1025                 val = mdesc_get_property(md, node, "latency", NULL);
1026                 m->latency = *val;
1027                 val = mdesc_get_property(md, node, "address-match", NULL);
1028                 m->match = *val;
1029                 val = mdesc_get_property(md, node, "address-mask", NULL);
1030                 m->mask = *val;
1031
1032                 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1033                         "match[%lx] mask[%lx]\n",
1034                         count - 1, m->node, m->latency, m->match, m->mask);
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int __init grab_mblocks(struct mdesc_handle *md)
1041 {
1042         unsigned long paddr;
1043         int count = 0;
1044         u64 node;
1045
1046         mdesc_for_each_node_by_name(md, node, "mblock")
1047                 count++;
1048         if (!count)
1049                 return -ENOENT;
1050
1051         paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1052                           SMP_CACHE_BYTES);
1053         if (!paddr)
1054                 return -ENOMEM;
1055
1056         mblocks = __va(paddr);
1057         num_mblocks = count;
1058
1059         count = 0;
1060         mdesc_for_each_node_by_name(md, node, "mblock") {
1061                 struct mdesc_mblock *m = &mblocks[count++];
1062                 const u64 *val;
1063
1064                 val = mdesc_get_property(md, node, "base", NULL);
1065                 m->base = *val;
1066                 val = mdesc_get_property(md, node, "size", NULL);
1067                 m->size = *val;
1068                 val = mdesc_get_property(md, node,
1069                                          "address-congruence-offset", NULL);
1070                 m->offset = *val;
1071
1072                 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1073                         count - 1, m->base, m->size, m->offset);
1074         }
1075
1076         return 0;
1077 }
1078
1079 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1080                                                u64 grp, cpumask_t *mask)
1081 {
1082         u64 arc;
1083
1084         cpus_clear(*mask);
1085
1086         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1087                 u64 target = mdesc_arc_target(md, arc);
1088                 const char *name = mdesc_node_name(md, target);
1089                 const u64 *id;
1090
1091                 if (strcmp(name, "cpu"))
1092                         continue;
1093                 id = mdesc_get_property(md, target, "id", NULL);
1094                 if (*id < NR_CPUS)
1095                         cpu_set(*id, *mask);
1096         }
1097 }
1098
1099 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1100 {
1101         int i;
1102
1103         for (i = 0; i < num_mlgroups; i++) {
1104                 struct mdesc_mlgroup *m = &mlgroups[i];
1105                 if (m->node == node)
1106                         return m;
1107         }
1108         return NULL;
1109 }
1110
1111 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1112                                       int index)
1113 {
1114         struct mdesc_mlgroup *candidate = NULL;
1115         u64 arc, best_latency = ~(u64)0;
1116         struct node_mem_mask *n;
1117
1118         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1119                 u64 target = mdesc_arc_target(md, arc);
1120                 struct mdesc_mlgroup *m = find_mlgroup(target);
1121                 if (!m)
1122                         continue;
1123                 if (m->latency < best_latency) {
1124                         candidate = m;
1125                         best_latency = m->latency;
1126                 }
1127         }
1128         if (!candidate)
1129                 return -ENOENT;
1130
1131         if (num_node_masks != index) {
1132                 printk(KERN_ERR "Inconsistent NUMA state, "
1133                        "index[%d] != num_node_masks[%d]\n",
1134                        index, num_node_masks);
1135                 return -EINVAL;
1136         }
1137
1138         n = &node_masks[num_node_masks++];
1139
1140         n->mask = candidate->mask;
1141         n->val = candidate->match;
1142
1143         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1144                 index, n->mask, n->val, candidate->latency);
1145
1146         return 0;
1147 }
1148
1149 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1150                                          int index)
1151 {
1152         cpumask_t mask;
1153         int cpu;
1154
1155         numa_parse_mdesc_group_cpus(md, grp, &mask);
1156
1157         for_each_cpu_mask(cpu, mask)
1158                 numa_cpu_lookup_table[cpu] = index;
1159         numa_cpumask_lookup_table[index] = mask;
1160
1161         if (numa_debug) {
1162                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1163                 for_each_cpu_mask(cpu, mask)
1164                         printk("%d ", cpu);
1165                 printk("]\n");
1166         }
1167
1168         return numa_attach_mlgroup(md, grp, index);
1169 }
1170
1171 static int __init numa_parse_mdesc(void)
1172 {
1173         struct mdesc_handle *md = mdesc_grab();
1174         int i, err, count;
1175         u64 node;
1176
1177         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1178         if (node == MDESC_NODE_NULL) {
1179                 mdesc_release(md);
1180                 return -ENOENT;
1181         }
1182
1183         err = grab_mblocks(md);
1184         if (err < 0)
1185                 goto out;
1186
1187         err = grab_mlgroups(md);
1188         if (err < 0)
1189                 goto out;
1190
1191         count = 0;
1192         mdesc_for_each_node_by_name(md, node, "group") {
1193                 err = numa_parse_mdesc_group(md, node, count);
1194                 if (err < 0)
1195                         break;
1196                 count++;
1197         }
1198
1199         add_node_ranges();
1200
1201         for (i = 0; i < num_node_masks; i++) {
1202                 allocate_node_data(i);
1203                 node_set_online(i);
1204         }
1205
1206         err = 0;
1207 out:
1208         mdesc_release(md);
1209         return err;
1210 }
1211
1212 static int __init numa_parse_jbus(void)
1213 {
1214         unsigned long cpu, index;
1215
1216         /* NUMA node id is encoded in bits 36 and higher, and there is
1217          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1218          */
1219         index = 0;
1220         for_each_present_cpu(cpu) {
1221                 numa_cpu_lookup_table[cpu] = index;
1222                 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1223                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1224                 node_masks[index].val = cpu << 36UL;
1225
1226                 index++;
1227         }
1228         num_node_masks = index;
1229
1230         add_node_ranges();
1231
1232         for (index = 0; index < num_node_masks; index++) {
1233                 allocate_node_data(index);
1234                 node_set_online(index);
1235         }
1236
1237         return 0;
1238 }
1239
1240 static int __init numa_parse_sun4u(void)
1241 {
1242         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1243                 unsigned long ver;
1244
1245                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1246                 if ((ver >> 32UL) == __JALAPENO_ID ||
1247                     (ver >> 32UL) == __SERRANO_ID)
1248                         return numa_parse_jbus();
1249         }
1250         return -1;
1251 }
1252
1253 static int __init bootmem_init_numa(void)
1254 {
1255         int err = -1;
1256
1257         numadbg("bootmem_init_numa()\n");
1258
1259         if (numa_enabled) {
1260                 if (tlb_type == hypervisor)
1261                         err = numa_parse_mdesc();
1262                 else
1263                         err = numa_parse_sun4u();
1264         }
1265         return err;
1266 }
1267
1268 #else
1269
1270 static int bootmem_init_numa(void)
1271 {
1272         return -1;
1273 }
1274
1275 #endif
1276
1277 static void __init bootmem_init_nonnuma(void)
1278 {
1279         unsigned long top_of_ram = lmb_end_of_DRAM();
1280         unsigned long total_ram = lmb_phys_mem_size();
1281         unsigned int i;
1282
1283         numadbg("bootmem_init_nonnuma()\n");
1284
1285         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1286                top_of_ram, total_ram);
1287         printk(KERN_INFO "Memory hole size: %ldMB\n",
1288                (top_of_ram - total_ram) >> 20);
1289
1290         init_node_masks_nonnuma();
1291
1292         for (i = 0; i < lmb.memory.cnt; i++) {
1293                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1294                 unsigned long start_pfn, end_pfn;
1295
1296                 if (!size)
1297                         continue;
1298
1299                 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1300                 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1301                 add_active_range(0, start_pfn, end_pfn);
1302         }
1303
1304         allocate_node_data(0);
1305
1306         node_set_online(0);
1307 }
1308
1309 static void __init reserve_range_in_node(int nid, unsigned long start,
1310                                          unsigned long end)
1311 {
1312         numadbg("    reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1313                 nid, start, end);
1314         while (start < end) {
1315                 unsigned long this_end;
1316                 int n;
1317
1318                 this_end = nid_range(start, end, &n);
1319                 if (n == nid) {
1320                         numadbg("      MATCH reserving range [%lx:%lx]\n",
1321                                 start, this_end);
1322                         reserve_bootmem_node(NODE_DATA(nid), start,
1323                                              (this_end - start), BOOTMEM_DEFAULT);
1324                 } else
1325                         numadbg("      NO MATCH, advancing start to %lx\n",
1326                                 this_end);
1327
1328                 start = this_end;
1329         }
1330 }
1331
1332 static void __init trim_reserved_in_node(int nid)
1333 {
1334         int i;
1335
1336         numadbg("  trim_reserved_in_node(%d)\n", nid);
1337
1338         for (i = 0; i < lmb.reserved.cnt; i++) {
1339                 unsigned long start = lmb.reserved.region[i].base;
1340                 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1341                 unsigned long end = start + size;
1342
1343                 reserve_range_in_node(nid, start, end);
1344         }
1345 }
1346
1347 static void __init bootmem_init_one_node(int nid)
1348 {
1349         struct pglist_data *p;
1350
1351         numadbg("bootmem_init_one_node(%d)\n", nid);
1352
1353         p = NODE_DATA(nid);
1354
1355         if (p->node_spanned_pages) {
1356                 unsigned long paddr = node_masks[nid].bootmem_paddr;
1357                 unsigned long end_pfn;
1358
1359                 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1360
1361                 numadbg("  init_bootmem_node(%d, %lx, %lx, %lx)\n",
1362                         nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1363
1364                 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1365                                   p->node_start_pfn, end_pfn);
1366
1367                 numadbg("  free_bootmem_with_active_regions(%d, %lx)\n",
1368                         nid, end_pfn);
1369                 free_bootmem_with_active_regions(nid, end_pfn);
1370
1371                 trim_reserved_in_node(nid);
1372
1373                 numadbg("  sparse_memory_present_with_active_regions(%d)\n",
1374                         nid);
1375                 sparse_memory_present_with_active_regions(nid);
1376         }
1377 }
1378
1379 static unsigned long __init bootmem_init(unsigned long phys_base)
1380 {
1381         unsigned long end_pfn;
1382         int nid;
1383
1384         end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1385         max_pfn = max_low_pfn = end_pfn;
1386         min_low_pfn = (phys_base >> PAGE_SHIFT);
1387
1388         if (bootmem_init_numa() < 0)
1389                 bootmem_init_nonnuma();
1390
1391         /* XXX cpu notifier XXX */
1392
1393         for_each_online_node(nid)
1394                 bootmem_init_one_node(nid);
1395
1396         sparse_init();
1397
1398         return end_pfn;
1399 }
1400
1401 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1402 static int pall_ents __initdata;
1403
1404 #ifdef CONFIG_DEBUG_PAGEALLOC
1405 static unsigned long __ref kernel_map_range(unsigned long pstart,
1406                                             unsigned long pend, pgprot_t prot)
1407 {
1408         unsigned long vstart = PAGE_OFFSET + pstart;
1409         unsigned long vend = PAGE_OFFSET + pend;
1410         unsigned long alloc_bytes = 0UL;
1411
1412         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1413                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1414                             vstart, vend);
1415                 prom_halt();
1416         }
1417
1418         while (vstart < vend) {
1419                 unsigned long this_end, paddr = __pa(vstart);
1420                 pgd_t *pgd = pgd_offset_k(vstart);
1421                 pud_t *pud;
1422                 pmd_t *pmd;
1423                 pte_t *pte;
1424
1425                 pud = pud_offset(pgd, vstart);
1426                 if (pud_none(*pud)) {
1427                         pmd_t *new;
1428
1429                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1430                         alloc_bytes += PAGE_SIZE;
1431                         pud_populate(&init_mm, pud, new);
1432                 }
1433
1434                 pmd = pmd_offset(pud, vstart);
1435                 if (!pmd_present(*pmd)) {
1436                         pte_t *new;
1437
1438                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1439                         alloc_bytes += PAGE_SIZE;
1440                         pmd_populate_kernel(&init_mm, pmd, new);
1441                 }
1442
1443                 pte = pte_offset_kernel(pmd, vstart);
1444                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1445                 if (this_end > vend)
1446                         this_end = vend;
1447
1448                 while (vstart < this_end) {
1449                         pte_val(*pte) = (paddr | pgprot_val(prot));
1450
1451                         vstart += PAGE_SIZE;
1452                         paddr += PAGE_SIZE;
1453                         pte++;
1454                 }
1455         }
1456
1457         return alloc_bytes;
1458 }
1459
1460 extern unsigned int kvmap_linear_patch[1];
1461 #endif /* CONFIG_DEBUG_PAGEALLOC */
1462
1463 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1464 {
1465         const unsigned long shift_256MB = 28;
1466         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1467         const unsigned long size_256MB = (1UL << shift_256MB);
1468
1469         while (start < end) {
1470                 long remains;
1471
1472                 remains = end - start;
1473                 if (remains < size_256MB)
1474                         break;
1475
1476                 if (start & mask_256MB) {
1477                         start = (start + size_256MB) & ~mask_256MB;
1478                         continue;
1479                 }
1480
1481                 while (remains >= size_256MB) {
1482                         unsigned long index = start >> shift_256MB;
1483
1484                         __set_bit(index, kpte_linear_bitmap);
1485
1486                         start += size_256MB;
1487                         remains -= size_256MB;
1488                 }
1489         }
1490 }
1491
1492 static void __init init_kpte_bitmap(void)
1493 {
1494         unsigned long i;
1495
1496         for (i = 0; i < pall_ents; i++) {
1497                 unsigned long phys_start, phys_end;
1498
1499                 phys_start = pall[i].phys_addr;
1500                 phys_end = phys_start + pall[i].reg_size;
1501
1502                 mark_kpte_bitmap(phys_start, phys_end);
1503         }
1504 }
1505
1506 static void __init kernel_physical_mapping_init(void)
1507 {
1508 #ifdef CONFIG_DEBUG_PAGEALLOC
1509         unsigned long i, mem_alloced = 0UL;
1510
1511         for (i = 0; i < pall_ents; i++) {
1512                 unsigned long phys_start, phys_end;
1513
1514                 phys_start = pall[i].phys_addr;
1515                 phys_end = phys_start + pall[i].reg_size;
1516
1517                 mem_alloced += kernel_map_range(phys_start, phys_end,
1518                                                 PAGE_KERNEL);
1519         }
1520
1521         printk("Allocated %ld bytes for kernel page tables.\n",
1522                mem_alloced);
1523
1524         kvmap_linear_patch[0] = 0x01000000; /* nop */
1525         flushi(&kvmap_linear_patch[0]);
1526
1527         __flush_tlb_all();
1528 #endif
1529 }
1530
1531 #ifdef CONFIG_DEBUG_PAGEALLOC
1532 void kernel_map_pages(struct page *page, int numpages, int enable)
1533 {
1534         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1535         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1536
1537         kernel_map_range(phys_start, phys_end,
1538                          (enable ? PAGE_KERNEL : __pgprot(0)));
1539
1540         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1541                                PAGE_OFFSET + phys_end);
1542
1543         /* we should perform an IPI and flush all tlbs,
1544          * but that can deadlock->flush only current cpu.
1545          */
1546         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1547                                  PAGE_OFFSET + phys_end);
1548 }
1549 #endif
1550
1551 unsigned long __init find_ecache_flush_span(unsigned long size)
1552 {
1553         int i;
1554
1555         for (i = 0; i < pavail_ents; i++) {
1556                 if (pavail[i].reg_size >= size)
1557                         return pavail[i].phys_addr;
1558         }
1559
1560         return ~0UL;
1561 }
1562
1563 static void __init tsb_phys_patch(void)
1564 {
1565         struct tsb_ldquad_phys_patch_entry *pquad;
1566         struct tsb_phys_patch_entry *p;
1567
1568         pquad = &__tsb_ldquad_phys_patch;
1569         while (pquad < &__tsb_ldquad_phys_patch_end) {
1570                 unsigned long addr = pquad->addr;
1571
1572                 if (tlb_type == hypervisor)
1573                         *(unsigned int *) addr = pquad->sun4v_insn;
1574                 else
1575                         *(unsigned int *) addr = pquad->sun4u_insn;
1576                 wmb();
1577                 __asm__ __volatile__("flush     %0"
1578                                      : /* no outputs */
1579                                      : "r" (addr));
1580
1581                 pquad++;
1582         }
1583
1584         p = &__tsb_phys_patch;
1585         while (p < &__tsb_phys_patch_end) {
1586                 unsigned long addr = p->addr;
1587
1588                 *(unsigned int *) addr = p->insn;
1589                 wmb();
1590                 __asm__ __volatile__("flush     %0"
1591                                      : /* no outputs */
1592                                      : "r" (addr));
1593
1594                 p++;
1595         }
1596 }
1597
1598 /* Don't mark as init, we give this to the Hypervisor.  */
1599 #ifndef CONFIG_DEBUG_PAGEALLOC
1600 #define NUM_KTSB_DESCR  2
1601 #else
1602 #define NUM_KTSB_DESCR  1
1603 #endif
1604 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1605 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1606
1607 static void __init sun4v_ktsb_init(void)
1608 {
1609         unsigned long ktsb_pa;
1610
1611         /* First KTSB for PAGE_SIZE mappings.  */
1612         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1613
1614         switch (PAGE_SIZE) {
1615         case 8 * 1024:
1616         default:
1617                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1618                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1619                 break;
1620
1621         case 64 * 1024:
1622                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1623                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1624                 break;
1625
1626         case 512 * 1024:
1627                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1628                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1629                 break;
1630
1631         case 4 * 1024 * 1024:
1632                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1633                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1634                 break;
1635         };
1636
1637         ktsb_descr[0].assoc = 1;
1638         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1639         ktsb_descr[0].ctx_idx = 0;
1640         ktsb_descr[0].tsb_base = ktsb_pa;
1641         ktsb_descr[0].resv = 0;
1642
1643 #ifndef CONFIG_DEBUG_PAGEALLOC
1644         /* Second KTSB for 4MB/256MB mappings.  */
1645         ktsb_pa = (kern_base +
1646                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1647
1648         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1649         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1650                                    HV_PGSZ_MASK_256MB);
1651         ktsb_descr[1].assoc = 1;
1652         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1653         ktsb_descr[1].ctx_idx = 0;
1654         ktsb_descr[1].tsb_base = ktsb_pa;
1655         ktsb_descr[1].resv = 0;
1656 #endif
1657 }
1658
1659 void __cpuinit sun4v_ktsb_register(void)
1660 {
1661         unsigned long pa, ret;
1662
1663         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1664
1665         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1666         if (ret != 0) {
1667                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1668                             "errors with %lx\n", pa, ret);
1669                 prom_halt();
1670         }
1671 }
1672
1673 /* paging_init() sets up the page tables */
1674
1675 static unsigned long last_valid_pfn;
1676 pgd_t swapper_pg_dir[2048];
1677
1678 static void sun4u_pgprot_init(void);
1679 static void sun4v_pgprot_init(void);
1680
1681 /* Dummy function */
1682 void __init setup_per_cpu_areas(void)
1683 {
1684 }
1685
1686 void __init paging_init(void)
1687 {
1688         unsigned long end_pfn, shift, phys_base;
1689         unsigned long real_end, i;
1690
1691         /* These build time checkes make sure that the dcache_dirty_cpu()
1692          * page->flags usage will work.
1693          *
1694          * When a page gets marked as dcache-dirty, we store the
1695          * cpu number starting at bit 32 in the page->flags.  Also,
1696          * functions like clear_dcache_dirty_cpu use the cpu mask
1697          * in 13-bit signed-immediate instruction fields.
1698          */
1699
1700         /*
1701          * Page flags must not reach into upper 32 bits that are used
1702          * for the cpu number
1703          */
1704         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1705
1706         /*
1707          * The bit fields placed in the high range must not reach below
1708          * the 32 bit boundary. Otherwise we cannot place the cpu field
1709          * at the 32 bit boundary.
1710          */
1711         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1712                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1713
1714         BUILD_BUG_ON(NR_CPUS > 4096);
1715
1716         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1717         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1718
1719         /* Invalidate both kernel TSBs.  */
1720         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1721 #ifndef CONFIG_DEBUG_PAGEALLOC
1722         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1723 #endif
1724
1725         if (tlb_type == hypervisor)
1726                 sun4v_pgprot_init();
1727         else
1728                 sun4u_pgprot_init();
1729
1730         if (tlb_type == cheetah_plus ||
1731             tlb_type == hypervisor)
1732                 tsb_phys_patch();
1733
1734         if (tlb_type == hypervisor) {
1735                 sun4v_patch_tlb_handlers();
1736                 sun4v_ktsb_init();
1737         }
1738
1739         lmb_init();
1740
1741         /* Find available physical memory...
1742          *
1743          * Read it twice in order to work around a bug in openfirmware.
1744          * The call to grab this table itself can cause openfirmware to
1745          * allocate memory, which in turn can take away some space from
1746          * the list of available memory.  Reading it twice makes sure
1747          * we really do get the final value.
1748          */
1749         read_obp_translations();
1750         read_obp_memory("reg", &pall[0], &pall_ents);
1751         read_obp_memory("available", &pavail[0], &pavail_ents);
1752         read_obp_memory("available", &pavail[0], &pavail_ents);
1753
1754         phys_base = 0xffffffffffffffffUL;
1755         for (i = 0; i < pavail_ents; i++) {
1756                 phys_base = min(phys_base, pavail[i].phys_addr);
1757                 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1758         }
1759
1760         lmb_reserve(kern_base, kern_size);
1761
1762         find_ramdisk(phys_base);
1763
1764         lmb_enforce_memory_limit(cmdline_memory_size);
1765
1766         lmb_analyze();
1767         lmb_dump_all();
1768
1769         set_bit(0, mmu_context_bmap);
1770
1771         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1772
1773         real_end = (unsigned long)_end;
1774         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1775         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1776                num_kernel_image_mappings);
1777
1778         /* Set kernel pgd to upper alias so physical page computations
1779          * work.
1780          */
1781         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1782
1783         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1784
1785         /* Now can init the kernel/bad page tables. */
1786         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1787                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1788
1789         inherit_prom_mappings();
1790
1791         init_kpte_bitmap();
1792
1793         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1794         setup_tba();
1795
1796         __flush_tlb_all();
1797
1798         if (tlb_type == hypervisor)
1799                 sun4v_ktsb_register();
1800
1801         /* We must setup the per-cpu areas before we pull in the
1802          * PROM and the MDESC.  The code there fills in cpu and
1803          * other information into per-cpu data structures.
1804          */
1805         real_setup_per_cpu_areas();
1806
1807         prom_build_devicetree();
1808
1809         if (tlb_type == hypervisor)
1810                 sun4v_mdesc_init();
1811
1812         /* Once the OF device tree and MDESC have been setup, we know
1813          * the list of possible cpus.  Therefore we can allocate the
1814          * IRQ stacks.
1815          */
1816         for_each_possible_cpu(i) {
1817                 /* XXX Use node local allocations... XXX */
1818                 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1819                 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1820         }
1821
1822         /* Setup bootmem... */
1823         last_valid_pfn = end_pfn = bootmem_init(phys_base);
1824
1825 #ifndef CONFIG_NEED_MULTIPLE_NODES
1826         max_mapnr = last_valid_pfn;
1827 #endif
1828         kernel_physical_mapping_init();
1829
1830         {
1831                 unsigned long max_zone_pfns[MAX_NR_ZONES];
1832
1833                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1834
1835                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1836
1837                 free_area_init_nodes(max_zone_pfns);
1838         }
1839
1840         printk("Booting Linux...\n");
1841 }
1842
1843 int __init page_in_phys_avail(unsigned long paddr)
1844 {
1845         int i;
1846
1847         paddr &= PAGE_MASK;
1848
1849         for (i = 0; i < pavail_ents; i++) {
1850                 unsigned long start, end;
1851
1852                 start = pavail[i].phys_addr;
1853                 end = start + pavail[i].reg_size;
1854
1855                 if (paddr >= start && paddr < end)
1856                         return 1;
1857         }
1858         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1859                 return 1;
1860 #ifdef CONFIG_BLK_DEV_INITRD
1861         if (paddr >= __pa(initrd_start) &&
1862             paddr < __pa(PAGE_ALIGN(initrd_end)))
1863                 return 1;
1864 #endif
1865
1866         return 0;
1867 }
1868
1869 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1870 static int pavail_rescan_ents __initdata;
1871
1872 /* Certain OBP calls, such as fetching "available" properties, can
1873  * claim physical memory.  So, along with initializing the valid
1874  * address bitmap, what we do here is refetch the physical available
1875  * memory list again, and make sure it provides at least as much
1876  * memory as 'pavail' does.
1877  */
1878 static void __init setup_valid_addr_bitmap_from_pavail(void)
1879 {
1880         int i;
1881
1882         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1883
1884         for (i = 0; i < pavail_ents; i++) {
1885                 unsigned long old_start, old_end;
1886
1887                 old_start = pavail[i].phys_addr;
1888                 old_end = old_start + pavail[i].reg_size;
1889                 while (old_start < old_end) {
1890                         int n;
1891
1892                         for (n = 0; n < pavail_rescan_ents; n++) {
1893                                 unsigned long new_start, new_end;
1894
1895                                 new_start = pavail_rescan[n].phys_addr;
1896                                 new_end = new_start +
1897                                         pavail_rescan[n].reg_size;
1898
1899                                 if (new_start <= old_start &&
1900                                     new_end >= (old_start + PAGE_SIZE)) {
1901                                         set_bit(old_start >> 22,
1902                                                 sparc64_valid_addr_bitmap);
1903                                         goto do_next_page;
1904                                 }
1905                         }
1906
1907                         prom_printf("mem_init: Lost memory in pavail\n");
1908                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1909                                     pavail[i].phys_addr,
1910                                     pavail[i].reg_size);
1911                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1912                                     pavail_rescan[i].phys_addr,
1913                                     pavail_rescan[i].reg_size);
1914                         prom_printf("mem_init: Cannot continue, aborting.\n");
1915                         prom_halt();
1916
1917                 do_next_page:
1918                         old_start += PAGE_SIZE;
1919                 }
1920         }
1921 }
1922
1923 void __init mem_init(void)
1924 {
1925         unsigned long codepages, datapages, initpages;
1926         unsigned long addr, last;
1927         int i;
1928
1929         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1930         i += 1;
1931         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1932         if (sparc64_valid_addr_bitmap == NULL) {
1933                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1934                 prom_halt();
1935         }
1936         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1937
1938         addr = PAGE_OFFSET + kern_base;
1939         last = PAGE_ALIGN(kern_size) + addr;
1940         while (addr < last) {
1941                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1942                 addr += PAGE_SIZE;
1943         }
1944
1945         setup_valid_addr_bitmap_from_pavail();
1946
1947         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1948
1949 #ifdef CONFIG_NEED_MULTIPLE_NODES
1950         for_each_online_node(i) {
1951                 if (NODE_DATA(i)->node_spanned_pages != 0) {
1952                         totalram_pages +=
1953                                 free_all_bootmem_node(NODE_DATA(i));
1954                 }
1955         }
1956 #else
1957         totalram_pages = free_all_bootmem();
1958 #endif
1959
1960         /* We subtract one to account for the mem_map_zero page
1961          * allocated below.
1962          */
1963         totalram_pages -= 1;
1964         num_physpages = totalram_pages;
1965
1966         /*
1967          * Set up the zero page, mark it reserved, so that page count
1968          * is not manipulated when freeing the page from user ptes.
1969          */
1970         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1971         if (mem_map_zero == NULL) {
1972                 prom_printf("paging_init: Cannot alloc zero page.\n");
1973                 prom_halt();
1974         }
1975         SetPageReserved(mem_map_zero);
1976
1977         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1978         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1979         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1980         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1981         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1982         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1983
1984         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1985                nr_free_pages() << (PAGE_SHIFT-10),
1986                codepages << (PAGE_SHIFT-10),
1987                datapages << (PAGE_SHIFT-10),
1988                initpages << (PAGE_SHIFT-10),
1989                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1990
1991         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1992                 cheetah_ecache_flush_init();
1993 }
1994
1995 void free_initmem(void)
1996 {
1997         unsigned long addr, initend;
1998         int do_free = 1;
1999
2000         /* If the physical memory maps were trimmed by kernel command
2001          * line options, don't even try freeing this initmem stuff up.
2002          * The kernel image could have been in the trimmed out region
2003          * and if so the freeing below will free invalid page structs.
2004          */
2005         if (cmdline_memory_size)
2006                 do_free = 0;
2007
2008         /*
2009          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2010          */
2011         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2012         initend = (unsigned long)(__init_end) & PAGE_MASK;
2013         for (; addr < initend; addr += PAGE_SIZE) {
2014                 unsigned long page;
2015                 struct page *p;
2016
2017                 page = (addr +
2018                         ((unsigned long) __va(kern_base)) -
2019                         ((unsigned long) KERNBASE));
2020                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2021
2022                 if (do_free) {
2023                         p = virt_to_page(page);
2024
2025                         ClearPageReserved(p);
2026                         init_page_count(p);
2027                         __free_page(p);
2028                         num_physpages++;
2029                         totalram_pages++;
2030                 }
2031         }
2032 }
2033
2034 #ifdef CONFIG_BLK_DEV_INITRD
2035 void free_initrd_mem(unsigned long start, unsigned long end)
2036 {
2037         if (start < end)
2038                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2039         for (; start < end; start += PAGE_SIZE) {
2040                 struct page *p = virt_to_page(start);
2041
2042                 ClearPageReserved(p);
2043                 init_page_count(p);
2044                 __free_page(p);
2045                 num_physpages++;
2046                 totalram_pages++;
2047         }
2048 }
2049 #endif
2050
2051 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2052 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2053 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2054 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2055 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2056 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2057
2058 pgprot_t PAGE_KERNEL __read_mostly;
2059 EXPORT_SYMBOL(PAGE_KERNEL);
2060
2061 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2062 pgprot_t PAGE_COPY __read_mostly;
2063
2064 pgprot_t PAGE_SHARED __read_mostly;
2065 EXPORT_SYMBOL(PAGE_SHARED);
2066
2067 pgprot_t PAGE_EXEC __read_mostly;
2068 unsigned long pg_iobits __read_mostly;
2069
2070 unsigned long _PAGE_IE __read_mostly;
2071 EXPORT_SYMBOL(_PAGE_IE);
2072
2073 unsigned long _PAGE_E __read_mostly;
2074 EXPORT_SYMBOL(_PAGE_E);
2075
2076 unsigned long _PAGE_CACHE __read_mostly;
2077 EXPORT_SYMBOL(_PAGE_CACHE);
2078
2079 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2080
2081 #define VMEMMAP_CHUNK_SHIFT     22
2082 #define VMEMMAP_CHUNK           (1UL << VMEMMAP_CHUNK_SHIFT)
2083 #define VMEMMAP_CHUNK_MASK      ~(VMEMMAP_CHUNK - 1UL)
2084 #define VMEMMAP_ALIGN(x)        (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2085
2086 #define VMEMMAP_SIZE    ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2087                           sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2088 unsigned long vmemmap_table[VMEMMAP_SIZE];
2089
2090 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2091 {
2092         unsigned long vstart = (unsigned long) start;
2093         unsigned long vend = (unsigned long) (start + nr);
2094         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2095         unsigned long phys_end = (vend - VMEMMAP_BASE);
2096         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2097         unsigned long end = VMEMMAP_ALIGN(phys_end);
2098         unsigned long pte_base;
2099
2100         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2101                     _PAGE_CP_4U | _PAGE_CV_4U |
2102                     _PAGE_P_4U | _PAGE_W_4U);
2103         if (tlb_type == hypervisor)
2104                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2105                             _PAGE_CP_4V | _PAGE_CV_4V |
2106                             _PAGE_P_4V | _PAGE_W_4V);
2107
2108         for (; addr < end; addr += VMEMMAP_CHUNK) {
2109                 unsigned long *vmem_pp =
2110                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2111                 void *block;
2112
2113                 if (!(*vmem_pp & _PAGE_VALID)) {
2114                         block = vmemmap_alloc_block(1UL << 22, node);
2115                         if (!block)
2116                                 return -ENOMEM;
2117
2118                         *vmem_pp = pte_base | __pa(block);
2119
2120                         printk(KERN_INFO "[%p-%p] page_structs=%lu "
2121                                "node=%d entry=%lu/%lu\n", start, block, nr,
2122                                node,
2123                                addr >> VMEMMAP_CHUNK_SHIFT,
2124                                VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2125                 }
2126         }
2127         return 0;
2128 }
2129 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2130
2131 static void prot_init_common(unsigned long page_none,
2132                              unsigned long page_shared,
2133                              unsigned long page_copy,
2134                              unsigned long page_readonly,
2135                              unsigned long page_exec_bit)
2136 {
2137         PAGE_COPY = __pgprot(page_copy);
2138         PAGE_SHARED = __pgprot(page_shared);
2139
2140         protection_map[0x0] = __pgprot(page_none);
2141         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2142         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2143         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2144         protection_map[0x4] = __pgprot(page_readonly);
2145         protection_map[0x5] = __pgprot(page_readonly);
2146         protection_map[0x6] = __pgprot(page_copy);
2147         protection_map[0x7] = __pgprot(page_copy);
2148         protection_map[0x8] = __pgprot(page_none);
2149         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2150         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2151         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2152         protection_map[0xc] = __pgprot(page_readonly);
2153         protection_map[0xd] = __pgprot(page_readonly);
2154         protection_map[0xe] = __pgprot(page_shared);
2155         protection_map[0xf] = __pgprot(page_shared);
2156 }
2157
2158 static void __init sun4u_pgprot_init(void)
2159 {
2160         unsigned long page_none, page_shared, page_copy, page_readonly;
2161         unsigned long page_exec_bit;
2162
2163         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2164                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2165                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2166                                 _PAGE_EXEC_4U);
2167         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2168                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2169                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2170                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2171         PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2172
2173         _PAGE_IE = _PAGE_IE_4U;
2174         _PAGE_E = _PAGE_E_4U;
2175         _PAGE_CACHE = _PAGE_CACHE_4U;
2176
2177         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2178                      __ACCESS_BITS_4U | _PAGE_E_4U);
2179
2180 #ifdef CONFIG_DEBUG_PAGEALLOC
2181         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2182                 0xfffff80000000000;
2183 #else
2184         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2185                 0xfffff80000000000;
2186 #endif
2187         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2188                                    _PAGE_P_4U | _PAGE_W_4U);
2189
2190         /* XXX Should use 256MB on Panther. XXX */
2191         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2192
2193         _PAGE_SZBITS = _PAGE_SZBITS_4U;
2194         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2195                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2196                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2197
2198
2199         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2200         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2201                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2202         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2203                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2204         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2205                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2206
2207         page_exec_bit = _PAGE_EXEC_4U;
2208
2209         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2210                          page_exec_bit);
2211 }
2212
2213 static void __init sun4v_pgprot_init(void)
2214 {
2215         unsigned long page_none, page_shared, page_copy, page_readonly;
2216         unsigned long page_exec_bit;
2217
2218         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2219                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2220                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2221                                 _PAGE_EXEC_4V);
2222         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2223         PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2224
2225         _PAGE_IE = _PAGE_IE_4V;
2226         _PAGE_E = _PAGE_E_4V;
2227         _PAGE_CACHE = _PAGE_CACHE_4V;
2228
2229 #ifdef CONFIG_DEBUG_PAGEALLOC
2230         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2231                 0xfffff80000000000;
2232 #else
2233         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2234                 0xfffff80000000000;
2235 #endif
2236         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2237                                    _PAGE_P_4V | _PAGE_W_4V);
2238
2239 #ifdef CONFIG_DEBUG_PAGEALLOC
2240         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2241                 0xfffff80000000000;
2242 #else
2243         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2244                 0xfffff80000000000;
2245 #endif
2246         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2247                                    _PAGE_P_4V | _PAGE_W_4V);
2248
2249         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2250                      __ACCESS_BITS_4V | _PAGE_E_4V);
2251
2252         _PAGE_SZBITS = _PAGE_SZBITS_4V;
2253         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2254                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2255                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2256                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2257
2258         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2259         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2260                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2261         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2262                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2263         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2264                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2265
2266         page_exec_bit = _PAGE_EXEC_4V;
2267
2268         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2269                          page_exec_bit);
2270 }
2271
2272 unsigned long pte_sz_bits(unsigned long sz)
2273 {
2274         if (tlb_type == hypervisor) {
2275                 switch (sz) {
2276                 case 8 * 1024:
2277                 default:
2278                         return _PAGE_SZ8K_4V;
2279                 case 64 * 1024:
2280                         return _PAGE_SZ64K_4V;
2281                 case 512 * 1024:
2282                         return _PAGE_SZ512K_4V;
2283                 case 4 * 1024 * 1024:
2284                         return _PAGE_SZ4MB_4V;
2285                 };
2286         } else {
2287                 switch (sz) {
2288                 case 8 * 1024:
2289                 default:
2290                         return _PAGE_SZ8K_4U;
2291                 case 64 * 1024:
2292                         return _PAGE_SZ64K_4U;
2293                 case 512 * 1024:
2294                         return _PAGE_SZ512K_4U;
2295                 case 4 * 1024 * 1024:
2296                         return _PAGE_SZ4MB_4U;
2297                 };
2298         }
2299 }
2300
2301 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2302 {
2303         pte_t pte;
2304
2305         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2306         pte_val(pte) |= (((unsigned long)space) << 32);
2307         pte_val(pte) |= pte_sz_bits(page_size);
2308
2309         return pte;
2310 }
2311
2312 static unsigned long kern_large_tte(unsigned long paddr)
2313 {
2314         unsigned long val;
2315
2316         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2317                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2318                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2319         if (tlb_type == hypervisor)
2320                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2321                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2322                        _PAGE_EXEC_4V | _PAGE_W_4V);
2323
2324         return val | paddr;
2325 }
2326
2327 /* If not locked, zap it. */
2328 void __flush_tlb_all(void)
2329 {
2330         unsigned long pstate;
2331         int i;
2332
2333         __asm__ __volatile__("flushw\n\t"
2334                              "rdpr      %%pstate, %0\n\t"
2335                              "wrpr      %0, %1, %%pstate"
2336                              : "=r" (pstate)
2337                              : "i" (PSTATE_IE));
2338         if (tlb_type == hypervisor) {
2339                 sun4v_mmu_demap_all();
2340         } else if (tlb_type == spitfire) {
2341                 for (i = 0; i < 64; i++) {
2342                         /* Spitfire Errata #32 workaround */
2343                         /* NOTE: Always runs on spitfire, so no
2344                          *       cheetah+ page size encodings.
2345                          */
2346                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2347                                              "flush     %%g6"
2348                                              : /* No outputs */
2349                                              : "r" (0),
2350                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2351
2352                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2353                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2354                                                      "membar #Sync"
2355                                                      : /* no outputs */
2356                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2357                                 spitfire_put_dtlb_data(i, 0x0UL);
2358                         }
2359
2360                         /* Spitfire Errata #32 workaround */
2361                         /* NOTE: Always runs on spitfire, so no
2362                          *       cheetah+ page size encodings.
2363                          */
2364                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2365                                              "flush     %%g6"
2366                                              : /* No outputs */
2367                                              : "r" (0),
2368                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2369
2370                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2371                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2372                                                      "membar #Sync"
2373                                                      : /* no outputs */
2374                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2375                                 spitfire_put_itlb_data(i, 0x0UL);
2376                         }
2377                 }
2378         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2379                 cheetah_flush_dtlb_all();
2380                 cheetah_flush_itlb_all();
2381         }
2382         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2383                              : : "r" (pstate));
2384 }