arch/sparc64/kernel/smp.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/lmb.h>
  24
  25 #include <asm/head.h>
  26 #include <asm/ptrace.h>
  27 #include <asm/atomic.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/cpudata.h>
  31 #include <asm/hvtramp.h>
  32 #include <asm/io.h>
  33 #include <asm/timer.h>
  34
  35 #include <asm/irq.h>
  36 #include <asm/irq_regs.h>
  37 #include <asm/page.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/oplib.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/sections.h>
  44 #include <asm/prom.h>
  45 #include <asm/mdesc.h>
  46 #include <asm/ldc.h>
  47 #include <asm/hypervisor.h>
  48
  49 int sparc64_multi_core __read_mostly;
  50
  51 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
  52 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  53 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  54 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  55         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  56
  57 EXPORT_SYMBOL(cpu_possible_map);
  58 EXPORT_SYMBOL(cpu_online_map);
  59 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  60 EXPORT_SYMBOL(cpu_core_map);
  61
  62 static cpumask_t smp_commenced_mask;
  63
  64 void smp_info(struct seq_file *m)
  65 {
  66         int i;
  67
  68         seq_printf(m, "State:\n");
  69         for_each_online_cpu(i)
  70                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  71 }
  72
  73 void smp_bogo(struct seq_file *m)
  74 {
  75         int i;
  76
  77         for_each_online_cpu(i)
  78                 seq_printf(m,
  79                            "Cpu%dClkTck\t: %016lx\n",
  80                            i, cpu_data(i).clock_tick);
  81 }
  82
  83 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
  84
  85 extern void setup_sparc64_timer(void);
  86
  87 static volatile unsigned long callin_flag = 0;
  88
  89 void __cpuinit smp_callin(void)
  90 {
  91         int cpuid = hard_smp_processor_id();
  92
  93         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  94
  95         if (tlb_type == hypervisor)
  96                 sun4v_ktsb_register();
  97
  98         __flush_tlb_all();
  99
 100         setup_sparc64_timer();
 101
 102         if (cheetah_pcache_forced_on)
 103                 cheetah_enable_pcache();
 104
 105         local_irq_enable();
 106
 107         callin_flag = 1;
 108         __asm__ __volatile__("membar #Sync\n\t"
 109                              "flush  %%g6" : : : "memory");
 110
 111         /* Clear this or we will die instantly when we
 112          * schedule back to this idler...
 113          */
 114         current_thread_info()->new_child = 0;
 115
 116         /* Attach to the address space of init_task. */
 117         atomic_inc(&init_mm.mm_count);
 118         current->active_mm = &init_mm;
 119
 120         while (!cpu_isset(cpuid, smp_commenced_mask))
 121                 rmb();
 122
 123         spin_lock(&call_lock);
 124         cpu_set(cpuid, cpu_online_map);
 125         spin_unlock(&call_lock);
 126
 127         /* idle thread is expected to have preempt disabled */
 128         preempt_disable();
 129 }
 130
 131 void cpu_panic(void)
 132 {
 133         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 134         panic("SMP bolixed\n");
 135 }
 136
 137 /* This tick register synchronization scheme is taken entirely from
 138  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 139  *
 140  * The only change I've made is to rework it so that the master
 141  * initiates the synchonization instead of the slave. -DaveM
 142  */
 143
 144 #define MASTER  0
 145 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 146
 147 #define NUM_ROUNDS      64      /* magic value */
 148 #define NUM_ITERS       5       /* likewise */
 149
 150 static DEFINE_SPINLOCK(itc_sync_lock);
 151 static unsigned long go[SLAVE + 1];
 152
 153 #define DEBUG_TICK_SYNC 0
 154
 155 static inline long get_delta (long *rt, long *master)
 156 {
 157         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 158         unsigned long tcenter, t0, t1, tm;
 159         unsigned long i;
 160
 161         for (i = 0; i < NUM_ITERS; i++) {
 162                 t0 = tick_ops->get_tick();
 163                 go[MASTER] = 1;
 164                 membar_storeload();
 165                 while (!(tm = go[SLAVE]))
 166                         rmb();
 167                 go[SLAVE] = 0;
 168                 wmb();
 169                 t1 = tick_ops->get_tick();
 170
 171                 if (t1 - t0 < best_t1 - best_t0)
 172                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 173         }
 174
 175         *rt = best_t1 - best_t0;
 176         *master = best_tm - best_t0;
 177
 178         /* average best_t0 and best_t1 without overflow: */
 179         tcenter = (best_t0/2 + best_t1/2);
 180         if (best_t0 % 2 + best_t1 % 2 == 2)
 181                 tcenter++;
 182         return tcenter - best_tm;
 183 }
 184
 185 void smp_synchronize_tick_client(void)
 186 {
 187         long i, delta, adj, adjust_latency = 0, done = 0;
 188         unsigned long flags, rt, master_time_stamp, bound;
 189 #if DEBUG_TICK_SYNC
 190         struct {
 191                 long rt;        /* roundtrip time */
 192                 long master;    /* master's timestamp */
 193                 long diff;      /* difference between midpoint and master's timestamp */
 194                 long lat;       /* estimate of itc adjustment latency */
 195         } t[NUM_ROUNDS];
 196 #endif
 197
 198         go[MASTER] = 1;
 199
 200         while (go[MASTER])
 201                 rmb();
 202
 203         local_irq_save(flags);
 204         {
 205                 for (i = 0; i < NUM_ROUNDS; i++) {
 206                         delta = get_delta(&rt, &master_time_stamp);
 207                         if (delta == 0) {
 208                                 done = 1;       /* let's lock on to this... */
 209                                 bound = rt;
 210                         }
 211
 212                         if (!done) {
 213                                 if (i > 0) {
 214                                         adjust_latency += -delta;
 215                                         adj = -delta + adjust_latency/4;
 216                                 } else
 217                                         adj = -delta;
 218
 219                                 tick_ops->add_tick(adj);
 220                         }
 221 #if DEBUG_TICK_SYNC
 222                         t[i].rt = rt;
 223                         t[i].master = master_time_stamp;
 224                         t[i].diff = delta;
 225                         t[i].lat = adjust_latency/4;
 226 #endif
 227                 }
 228         }
 229         local_irq_restore(flags);
 230
 231 #if DEBUG_TICK_SYNC
 232         for (i = 0; i < NUM_ROUNDS; i++)
 233                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 234                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 235 #endif
 236
 237         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 238                "(last diff %ld cycles, maxerr %lu cycles)\n",
 239                smp_processor_id(), delta, rt);
 240 }
 241
 242 static void smp_start_sync_tick_client(int cpu);
 243
 244 static void smp_synchronize_one_tick(int cpu)
 245 {
 246         unsigned long flags, i;
 247
 248         go[MASTER] = 0;
 249
 250         smp_start_sync_tick_client(cpu);
 251
 252         /* wait for client to be ready */
 253         while (!go[MASTER])
 254                 rmb();
 255
 256         /* now let the client proceed into his loop */
 257         go[MASTER] = 0;
 258         membar_storeload();
 259
 260         spin_lock_irqsave(&itc_sync_lock, flags);
 261         {
 262                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 263                         while (!go[MASTER])
 264                                 rmb();
 265                         go[MASTER] = 0;
 266                         wmb();
 267                         go[SLAVE] = tick_ops->get_tick();
 268                         membar_storeload();
 269                 }
 270         }
 271         spin_unlock_irqrestore(&itc_sync_lock, flags);
 272 }
 273
 274 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 275 /* XXX Put this in some common place. XXX */
 276 static unsigned long kimage_addr_to_ra(void *p)
 277 {
 278         unsigned long val = (unsigned long) p;
 279
 280         return kern_base + (val - KERNBASE);
 281 }
 282
 283 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
 284 {
 285         extern unsigned long sparc64_ttable_tl0;
 286         extern unsigned long kern_locked_tte_data;
 287         struct hvtramp_descr *hdesc;
 288         unsigned long trampoline_ra;
 289         struct trap_per_cpu *tb;
 290         u64 tte_vaddr, tte_data;
 291         unsigned long hv_err;
 292         int i;
 293
 294         hdesc = kzalloc(sizeof(*hdesc) +
 295                         (sizeof(struct hvtramp_mapping) *
 296                          num_kernel_image_mappings - 1),
 297                         GFP_KERNEL);
 298         if (!hdesc) {
 299                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 300                        "hvtramp_descr.\n");
 301                 return;
 302         }
 303
 304         hdesc->cpu = cpu;
 305         hdesc->num_mappings = num_kernel_image_mappings;
 306
 307         tb = &trap_block[cpu];
 308         tb->hdesc = hdesc;
 309
 310         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 311         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 312
 313         hdesc->thread_reg = thread_reg;
 314
 315         tte_vaddr = (unsigned long) KERNBASE;
 316         tte_data = kern_locked_tte_data;
 317
 318         for (i = 0; i < hdesc->num_mappings; i++) {
 319                 hdesc->maps[i].vaddr = tte_vaddr;
 320                 hdesc->maps[i].tte   = tte_data;
 321                 tte_vaddr += 0x400000;
 322                 tte_data  += 0x400000;
 323         }
 324
 325         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 326
 327         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 328                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 329                                  __pa(hdesc));
 330         if (hv_err)
 331                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 332                        "gives error %lu\n", hv_err);
 333 }
 334 #endif
 335
 336 extern unsigned long sparc64_cpu_startup;
 337
 338 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 339  * 32-bits (I think) so to be safe we have it read the pointer
 340  * contained here so we work on >4GB machines. -DaveM
 341  */
 342 static struct thread_info *cpu_new_thread = NULL;
 343
 344 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 345 {
 346         struct trap_per_cpu *tb = &trap_block[cpu];
 347         unsigned long entry =
 348                 (unsigned long)(&sparc64_cpu_startup);
 349         unsigned long cookie =
 350                 (unsigned long)(&cpu_new_thread);
 351         struct task_struct *p;
 352         int timeout, ret;
 353
 354         p = fork_idle(cpu);
 355         if (IS_ERR(p))
 356                 return PTR_ERR(p);
 357         callin_flag = 0;
 358         cpu_new_thread = task_thread_info(p);
 359
 360         if (tlb_type == hypervisor) {
 361 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 362                 if (ldom_domaining_enabled)
 363                         ldom_startcpu_cpuid(cpu,
 364                                             (unsigned long) cpu_new_thread);
 365                 else
 366 #endif
 367                         prom_startcpu_cpuid(cpu, entry, cookie);
 368         } else {
 369                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 370
 371                 prom_startcpu(dp->node, entry, cookie);
 372         }
 373
 374         for (timeout = 0; timeout < 50000; timeout++) {
 375                 if (callin_flag)
 376                         break;
 377                 udelay(100);
 378         }
 379
 380         if (callin_flag) {
 381                 ret = 0;
 382         } else {
 383                 printk("Processor %d is stuck.\n", cpu);
 384                 ret = -ENODEV;
 385         }
 386         cpu_new_thread = NULL;
 387
 388         if (tb->hdesc) {
 389                 kfree(tb->hdesc);
 390                 tb->hdesc = NULL;
 391         }
 392
 393         return ret;
 394 }
 395
 396 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 397 {
 398         u64 result, target;
 399         int stuck, tmp;
 400
 401         if (this_is_starfire) {
 402                 /* map to real upaid */
 403                 cpu = (((cpu & 0x3c) << 1) |
 404                         ((cpu & 0x40) >> 4) |
 405                         (cpu & 0x3));
 406         }
 407
 408         target = (cpu << 14) | 0x70;
 409 again:
 410         /* Ok, this is the real Spitfire Errata #54.
 411          * One must read back from a UDB internal register
 412          * after writes to the UDB interrupt dispatch, but
 413          * before the membar Sync for that write.
 414          * So we use the high UDB control register (ASI 0x7f,
 415          * ADDR 0x20) for the dummy read. -DaveM
 416          */
 417         tmp = 0x40;
 418         __asm__ __volatile__(
 419         "wrpr   %1, %2, %%pstate\n\t"
 420         "stxa   %4, [%0] %3\n\t"
 421         "stxa   %5, [%0+%8] %3\n\t"
 422         "add    %0, %8, %0\n\t"
 423         "stxa   %6, [%0+%8] %3\n\t"
 424         "membar #Sync\n\t"
 425         "stxa   %%g0, [%7] %3\n\t"
 426         "membar #Sync\n\t"
 427         "mov    0x20, %%g1\n\t"
 428         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 429         "membar #Sync"
 430         : "=r" (tmp)
 431         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 432           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 433           "r" (0x10), "0" (tmp)
 434         : "g1");
 435
 436         /* NOTE: PSTATE_IE is still clear. */
 437         stuck = 100000;
 438         do {
 439                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 440                         : "=r" (result)
 441                         : "i" (ASI_INTR_DISPATCH_STAT));
 442                 if (result == 0) {
 443                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 444                                              : : "r" (pstate));
 445                         return;
 446                 }
 447                 stuck -= 1;
 448                 if (stuck == 0)
 449                         break;
 450         } while (result & 0x1);
 451         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 452                              : : "r" (pstate));
 453         if (stuck == 0) {
 454                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 455                        smp_processor_id(), result);
 456         } else {
 457                 udelay(2);
 458                 goto again;
 459         }
 460 }
 461
 462 static inline void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 463 {
 464         u64 pstate;
 465         int i;
 466
 467         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 468         for_each_cpu_mask_nr(i, *mask)
 469                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 470 }
 471
 472 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 473  * packet, but we have no use for that.  However we do take advantage of
 474  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 475  */
 476 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask_p)
 477 {
 478         u64 pstate, ver, busy_mask;
 479         int nack_busy_id, is_jbus, need_more;
 480         cpumask_t mask;
 481
 482         if (cpus_empty(*mask_p))
 483                 return;
 484
 485         mask = *mask_p;
 486
 487         /* Unfortunately, someone at Sun had the brilliant idea to make the
 488          * busy/nack fields hard-coded by ITID number for this Ultra-III
 489          * derivative processor.
 490          */
 491         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 492         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 493                    (ver >> 32) == __SERRANO_ID);
 494
 495         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 496
 497 retry:
 498         need_more = 0;
 499         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 500                              : : "r" (pstate), "i" (PSTATE_IE));
 501
 502         /* Setup the dispatch data registers. */
 503         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 504                              "stxa      %1, [%4] %6\n\t"
 505                              "stxa      %2, [%5] %6\n\t"
 506                              "membar    #Sync\n\t"
 507                              : /* no outputs */
 508                              : "r" (data0), "r" (data1), "r" (data2),
 509                                "r" (0x40), "r" (0x50), "r" (0x60),
 510                                "i" (ASI_INTR_W));
 511
 512         nack_busy_id = 0;
 513         busy_mask = 0;
 514         {
 515                 int i;
 516
 517                 for_each_cpu_mask_nr(i, mask) {
 518                         u64 target = (i << 14) | 0x70;
 519
 520                         if (is_jbus) {
 521                                 busy_mask |= (0x1UL << (i * 2));
 522                         } else {
 523                                 target |= (nack_busy_id << 24);
 524                                 busy_mask |= (0x1UL <<
 525                                               (nack_busy_id * 2));
 526                         }
 527                         __asm__ __volatile__(
 528                                 "stxa   %%g0, [%0] %1\n\t"
 529                                 "membar #Sync\n\t"
 530                                 : /* no outputs */
 531                                 : "r" (target), "i" (ASI_INTR_W));
 532                         nack_busy_id++;
 533                         if (nack_busy_id == 32) {
 534                                 need_more = 1;
 535                                 break;
 536                         }
 537                 }
 538         }
 539
 540         /* Now, poll for completion. */
 541         {
 542                 u64 dispatch_stat, nack_mask;
 543                 long stuck;
 544
 545                 stuck = 100000 * nack_busy_id;
 546                 nack_mask = busy_mask << 1;
 547                 do {
 548                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 549                                              : "=r" (dispatch_stat)
 550                                              : "i" (ASI_INTR_DISPATCH_STAT));
 551                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 552                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 553                                                      : : "r" (pstate));
 554                                 if (unlikely(need_more)) {
 555                                         int i, cnt = 0;
 556                                         for_each_cpu_mask_nr(i, mask) {
 557                                                 cpu_clear(i, mask);
 558                                                 cnt++;
 559                                                 if (cnt == 32)
 560                                                         break;
 561                                         }
 562                                         goto retry;
 563                                 }
 564                                 return;
 565                         }
 566                         if (!--stuck)
 567                                 break;
 568                 } while (dispatch_stat & busy_mask);
 569
 570                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 571                                      : : "r" (pstate));
 572
 573                 if (dispatch_stat & busy_mask) {
 574                         /* Busy bits will not clear, continue instead
 575                          * of freezing up on this cpu.
 576                          */
 577                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 578                                smp_processor_id(), dispatch_stat);
 579                 } else {
 580                         int i, this_busy_nack = 0;
 581
 582                         /* Delay some random time with interrupts enabled
 583                          * to prevent deadlock.
 584                          */
 585                         udelay(2 * nack_busy_id);
 586
 587                         /* Clear out the mask bits for cpus which did not
 588                          * NACK us.
 589                          */
 590                         for_each_cpu_mask_nr(i, mask) {
 591                                 u64 check_mask;
 592
 593                                 if (is_jbus)
 594                                         check_mask = (0x2UL << (2*i));
 595                                 else
 596                                         check_mask = (0x2UL <<
 597                                                       this_busy_nack);
 598                                 if ((dispatch_stat & check_mask) == 0)
 599                                         cpu_clear(i, mask);
 600                                 this_busy_nack += 2;
 601                                 if (this_busy_nack == 64)
 602                                         break;
 603                         }
 604
 605                         goto retry;
 606                 }
 607         }
 608 }
 609
 610 /* Multi-cpu list version.  */
 611 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 612 {
 613         int cnt, retries, this_cpu, prev_sent, i;
 614         unsigned long flags, status;
 615         cpumask_t error_mask;
 616         struct trap_per_cpu *tb;
 617         u16 *cpu_list;
 618         u64 *mondo;
 619
 620         if (cpus_empty(*mask))
 621                 return;
 622
 623         /* We have to do this whole thing with interrupts fully disabled.
 624          * Otherwise if we send an xcall from interrupt context it will
 625          * corrupt both our mondo block and cpu list state.
 626          *
 627          * One consequence of this is that we cannot use timeout mechanisms
 628          * that depend upon interrupts being delivered locally.  So, for
 629          * example, we cannot sample jiffies and expect it to advance.
 630          *
 631          * Fortunately, udelay() uses %stick/%tick so we can use that.
 632          */
 633         local_irq_save(flags);
 634
 635         this_cpu = smp_processor_id();
 636         tb = &trap_block[this_cpu];
 637
 638         mondo = __va(tb->cpu_mondo_block_pa);
 639         mondo[0] = data0;
 640         mondo[1] = data1;
 641         mondo[2] = data2;
 642         wmb();
 643
 644         cpu_list = __va(tb->cpu_list_pa);
 645
 646         /* Setup the initial cpu list.  */
 647         cnt = 0;
 648         for_each_cpu_mask_nr(i, *mask)
 649                 cpu_list[cnt++] = i;
 650
 651         cpus_clear(error_mask);
 652         retries = 0;
 653         prev_sent = 0;
 654         do {
 655                 int forward_progress, n_sent;
 656
 657                 status = sun4v_cpu_mondo_send(cnt,
 658                                               tb->cpu_list_pa,
 659                                               tb->cpu_mondo_block_pa);
 660
 661                 /* HV_EOK means all cpus received the xcall, we're done.  */
 662                 if (likely(status == HV_EOK))
 663                         break;
 664
 665                 /* First, see if we made any forward progress.
 666                  *
 667                  * The hypervisor indicates successful sends by setting
 668                  * cpu list entries to the value 0xffff.
 669                  */
 670                 n_sent = 0;
 671                 for (i = 0; i < cnt; i++) {
 672                         if (likely(cpu_list[i] == 0xffff))
 673                                 n_sent++;
 674                 }
 675
 676                 forward_progress = 0;
 677                 if (n_sent > prev_sent)
 678                         forward_progress = 1;
 679
 680                 prev_sent = n_sent;
 681
 682                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 683                  * in the list are in error state.  Use the cpu_state()
 684                  * hypervisor call to find out which cpus are in error state.
 685                  */
 686                 if (unlikely(status == HV_ECPUERROR)) {
 687                         for (i = 0; i < cnt; i++) {
 688                                 long err;
 689                                 u16 cpu;
 690
 691                                 cpu = cpu_list[i];
 692                                 if (cpu == 0xffff)
 693                                         continue;
 694
 695                                 err = sun4v_cpu_state(cpu);
 696                                 if (err >= 0 &&
 697                                     err == HV_CPU_STATE_ERROR) {
 698                                         cpu_list[i] = 0xffff;
 699                                         cpu_set(cpu, error_mask);
 700                                 }
 701                         }
 702                 } else if (unlikely(status != HV_EWOULDBLOCK))
 703                         goto fatal_mondo_error;
 704
 705                 /* Don't bother rewriting the CPU list, just leave the
 706                  * 0xffff and non-0xffff entries in there and the
 707                  * hypervisor will do the right thing.
 708                  *
 709                  * Only advance timeout state if we didn't make any
 710                  * forward progress.
 711                  */
 712                 if (unlikely(!forward_progress)) {
 713                         if (unlikely(++retries > 10000))
 714                                 goto fatal_mondo_timeout;
 715
 716                         /* Delay a little bit to let other cpus catch up
 717                          * on their cpu mondo queue work.
 718                          */
 719                         udelay(2 * cnt);
 720                 }
 721         } while (1);
 722
 723         local_irq_restore(flags);
 724
 725         if (unlikely(!cpus_empty(error_mask)))
 726                 goto fatal_mondo_cpu_error;
 727
 728         return;
 729
 730 fatal_mondo_cpu_error:
 731         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 732                "were in error state\n",
 733                this_cpu);
 734         printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
 735         for_each_cpu_mask_nr(i, error_mask)
 736                 printk("%d ", i);
 737         printk("]\n");
 738         return;
 739
 740 fatal_mondo_timeout:
 741         local_irq_restore(flags);
 742         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 743                " progress after %d retries.\n",
 744                this_cpu, retries);
 745         goto dump_cpu_list_and_out;
 746
 747 fatal_mondo_error:
 748         local_irq_restore(flags);
 749         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 750                this_cpu, status);
 751         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 752                "mondo_block_pa(%lx)\n",
 753                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 754
 755 dump_cpu_list_and_out:
 756         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 757         for (i = 0; i < cnt; i++)
 758                 printk("%u ", cpu_list[i]);
 759         printk("]\n");
 760 }
 761
 762 static void (*xcall_deliver)(u64, u64, u64, const cpumask_t *);
 763
 764 /* Send cross call to all processors mentioned in MASK_P
 765  * except self.  Really, there are only two cases currently,
 766  * "&cpu_online_map" and "&mm->cpu_vm_mask".
 767  */
 768 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask_p)
 769 {
 770         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 771         int this_cpu = get_cpu();
 772         cpumask_t mask;
 773
 774         mask = *mask_p;
 775         if (mask_p != &cpu_online_map)
 776                 cpus_and(mask, mask, cpu_online_map);
 777         cpu_clear(this_cpu, mask);
 778
 779         xcall_deliver(data0, data1, data2, &mask);
 780         /* NOTE: Caller runs local copy on master. */
 781
 782         put_cpu();
 783 }
 784
 785 extern unsigned long xcall_sync_tick;
 786
 787 static void smp_start_sync_tick_client(int cpu)
 788 {
 789         xcall_deliver((u64) &xcall_sync_tick, 0, 0,
 790                       &cpumask_of_cpu(cpu));
 791 }
 792
 793 extern unsigned long xcall_call_function;
 794
 795 void arch_send_call_function_ipi(cpumask_t mask)
 796 {
 797         xcall_deliver((u64) &xcall_call_function, 0, 0, &mask);
 798 }
 799
 800 extern unsigned long xcall_call_function_single;
 801
 802 void arch_send_call_function_single_ipi(int cpu)
 803 {
 804         xcall_deliver((u64) &xcall_call_function_single, 0, 0,
 805                       &cpumask_of_cpu(cpu));
 806 }
 807
 808 /* Send cross call to all processors except self. */
 809 #define smp_cross_call(func, ctx, data1, data2) \
 810         smp_cross_call_masked(func, ctx, data1, data2, &cpu_online_map)
 811
 812 void smp_call_function_client(int irq, struct pt_regs *regs)
 813 {
 814         clear_softint(1 << irq);
 815         generic_smp_call_function_interrupt();
 816 }
 817
 818 void smp_call_function_single_client(int irq, struct pt_regs *regs)
 819 {
 820         clear_softint(1 << irq);
 821         generic_smp_call_function_single_interrupt();
 822 }
 823
 824 static void tsb_sync(void *info)
 825 {
 826         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 827         struct mm_struct *mm = info;
 828
 829         /* It is not valid to test "currrent->active_mm == mm" here.
 830          *
 831          * The value of "current" is not changed atomically with
 832          * switch_mm().  But that's OK, we just need to check the
 833          * current cpu's trap block PGD physical address.
 834          */
 835         if (tp->pgd_paddr == __pa(mm->pgd))
 836                 tsb_context_switch(mm);
 837 }
 838
 839 void smp_tsb_sync(struct mm_struct *mm)
 840 {
 841         smp_call_function_mask(mm->cpu_vm_mask, tsb_sync, mm, 1);
 842 }
 843
 844 extern unsigned long xcall_flush_tlb_mm;
 845 extern unsigned long xcall_flush_tlb_pending;
 846 extern unsigned long xcall_flush_tlb_kernel_range;
 847 #ifdef CONFIG_MAGIC_SYSRQ
 848 extern unsigned long xcall_fetch_glob_regs;
 849 #endif
 850 extern unsigned long xcall_receive_signal;
 851 extern unsigned long xcall_new_mmu_context_version;
 852 #ifdef CONFIG_KGDB
 853 extern unsigned long xcall_kgdb_capture;
 854 #endif
 855
 856 #ifdef DCACHE_ALIASING_POSSIBLE
 857 extern unsigned long xcall_flush_dcache_page_cheetah;
 858 #endif
 859 extern unsigned long xcall_flush_dcache_page_spitfire;
 860
 861 #ifdef CONFIG_DEBUG_DCFLUSH
 862 extern atomic_t dcpage_flushes;
 863 extern atomic_t dcpage_flushes_xcall;
 864 #endif
 865
 866 static inline void __local_flush_dcache_page(struct page *page)
 867 {
 868 #ifdef DCACHE_ALIASING_POSSIBLE
 869         __flush_dcache_page(page_address(page),
 870                             ((tlb_type == spitfire) &&
 871                              page_mapping(page) != NULL));
 872 #else
 873         if (page_mapping(page) != NULL &&
 874             tlb_type == spitfire)
 875                 __flush_icache_page(__pa(page_address(page)));
 876 #endif
 877 }
 878
 879 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 880 {
 881         cpumask_t mask = cpumask_of_cpu(cpu);
 882         int this_cpu;
 883
 884         if (tlb_type == hypervisor)
 885                 return;
 886
 887 #ifdef CONFIG_DEBUG_DCFLUSH
 888         atomic_inc(&dcpage_flushes);
 889 #endif
 890
 891         this_cpu = get_cpu();
 892
 893         if (cpu == this_cpu) {
 894                 __local_flush_dcache_page(page);
 895         } else if (cpu_online(cpu)) {
 896                 void *pg_addr = page_address(page);
 897                 u64 data0 = 0;
 898
 899                 if (tlb_type == spitfire) {
 900                         data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 901                         if (page_mapping(page) != NULL)
 902                                 data0 |= ((u64)1 << 32);
 903                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 904 #ifdef DCACHE_ALIASING_POSSIBLE
 905                         data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 906 #endif
 907                 }
 908                 if (data0) {
 909                         xcall_deliver(data0, __pa(pg_addr),
 910                                       (u64) pg_addr, &mask);
 911 #ifdef CONFIG_DEBUG_DCFLUSH
 912                         atomic_inc(&dcpage_flushes_xcall);
 913 #endif
 914                 }
 915         }
 916
 917         put_cpu();
 918 }
 919
 920 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 921 {
 922         cpumask_t mask = cpu_online_map;
 923         void *pg_addr;
 924         int this_cpu;
 925         u64 data0;
 926
 927         if (tlb_type == hypervisor)
 928                 return;
 929
 930         this_cpu = get_cpu();
 931
 932         cpu_clear(this_cpu, mask);
 933
 934 #ifdef CONFIG_DEBUG_DCFLUSH
 935         atomic_inc(&dcpage_flushes);
 936 #endif
 937         if (cpus_empty(mask))
 938                 goto flush_self;
 939         data0 = 0;
 940         pg_addr = page_address(page);
 941         if (tlb_type == spitfire) {
 942                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 943                 if (page_mapping(page) != NULL)
 944                         data0 |= ((u64)1 << 32);
 945         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 946 #ifdef DCACHE_ALIASING_POSSIBLE
 947                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 948 #endif
 949         }
 950         if (data0) {
 951                 xcall_deliver(data0, __pa(pg_addr),
 952                               (u64) pg_addr, &mask);
 953 #ifdef CONFIG_DEBUG_DCFLUSH
 954                 atomic_inc(&dcpage_flushes_xcall);
 955 #endif
 956         }
 957  flush_self:
 958         __local_flush_dcache_page(page);
 959
 960         put_cpu();
 961 }
 962
 963 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 964 {
 965         struct mm_struct *mm;
 966         unsigned long flags;
 967
 968         clear_softint(1 << irq);
 969
 970         /* See if we need to allocate a new TLB context because
 971          * the version of the one we are using is now out of date.
 972          */
 973         mm = current->active_mm;
 974         if (unlikely(!mm || (mm == &init_mm)))
 975                 return;
 976
 977         spin_lock_irqsave(&mm->context.lock, flags);
 978
 979         if (unlikely(!CTX_VALID(mm->context)))
 980                 get_new_mmu_context(mm);
 981
 982         spin_unlock_irqrestore(&mm->context.lock, flags);
 983
 984         load_secondary_context(mm);
 985         __flush_tlb_mm(CTX_HWBITS(mm->context),
 986                        SECONDARY_CONTEXT);
 987 }
 988
 989 void smp_new_mmu_context_version(void)
 990 {
 991         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
 992 }
 993
 994 #ifdef CONFIG_KGDB
 995 void kgdb_roundup_cpus(unsigned long flags)
 996 {
 997         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
 998 }
 999 #endif
1000
1001 #ifdef CONFIG_MAGIC_SYSRQ
1002 void smp_fetch_global_regs(void)
1003 {
1004         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1005 }
1006 #endif
1007
1008 /* We know that the window frames of the user have been flushed
1009  * to the stack before we get here because all callers of us
1010  * are flush_tlb_*() routines, and these run after flush_cache_*()
1011  * which performs the flushw.
1012  *
1013  * The SMP TLB coherency scheme we use works as follows:
1014  *
1015  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1016  *    space has (potentially) executed on, this is the heuristic
1017  *    we use to avoid doing cross calls.
1018  *
1019  *    Also, for flushing from kswapd and also for clones, we
1020  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1021  *
1022  * 2) TLB context numbers are shared globally across all processors
1023  *    in the system, this allows us to play several games to avoid
1024  *    cross calls.
1025  *
1026  *    One invariant is that when a cpu switches to a process, and
1027  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1028  *    current cpu's bit set, that tlb context is flushed locally.
1029  *
1030  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1031  *    cross calls when we want to flush the currently running process's
1032  *    tlb state.  This is done by clearing all cpu bits except the current
1033  *    processor's in current->active_mm->cpu_vm_mask and performing the
1034  *    flush locally only.  This will force any subsequent cpus which run
1035  *    this task to flush the context from the local tlb if the process
1036  *    migrates to another cpu (again).
1037  *
1038  * 3) For shared address spaces (threads) and swapping we bite the
1039  *    bullet for most cases and perform the cross call (but only to
1040  *    the cpus listed in cpu_vm_mask).
1041  *
1042  *    The performance gain from "optimizing" away the cross call for threads is
1043  *    questionable (in theory the big win for threads is the massive sharing of
1044  *    address space state across processors).
1045  */
1046
1047 /* This currently is only used by the hugetlb arch pre-fault
1048  * hook on UltraSPARC-III+ and later when changing the pagesize
1049  * bits of the context register for an address space.
1050  */
1051 void smp_flush_tlb_mm(struct mm_struct *mm)
1052 {
1053         u32 ctx = CTX_HWBITS(mm->context);
1054         int cpu = get_cpu();
1055
1056         if (atomic_read(&mm->mm_users) == 1) {
1057                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1058                 goto local_flush_and_out;
1059         }
1060
1061         smp_cross_call_masked(&xcall_flush_tlb_mm,
1062                               ctx, 0, 0,
1063                               &mm->cpu_vm_mask);
1064
1065 local_flush_and_out:
1066         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1067
1068         put_cpu();
1069 }
1070
1071 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1072 {
1073         u32 ctx = CTX_HWBITS(mm->context);
1074         int cpu = get_cpu();
1075
1076         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1077                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1078         else
1079                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1080                                       ctx, nr, (unsigned long) vaddrs,
1081                                       &mm->cpu_vm_mask);
1082
1083         __flush_tlb_pending(ctx, nr, vaddrs);
1084
1085         put_cpu();
1086 }
1087
1088 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1089 {
1090         start &= PAGE_MASK;
1091         end    = PAGE_ALIGN(end);
1092         if (start != end) {
1093                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1094                                0, start, end);
1095
1096                 __flush_tlb_kernel_range(start, end);
1097         }
1098 }
1099
1100 /* CPU capture. */
1101 /* #define CAPTURE_DEBUG */
1102 extern unsigned long xcall_capture;
1103
1104 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1105 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1106 static unsigned long penguins_are_doing_time;
1107
1108 void smp_capture(void)
1109 {
1110         int result = atomic_add_ret(1, &smp_capture_depth);
1111
1112         if (result == 1) {
1113                 int ncpus = num_online_cpus();
1114
1115 #ifdef CAPTURE_DEBUG
1116                 printk("CPU[%d]: Sending penguins to jail...",
1117                        smp_processor_id());
1118 #endif
1119                 penguins_are_doing_time = 1;
1120                 membar_storestore_loadstore();
1121                 atomic_inc(&smp_capture_registry);
1122                 smp_cross_call(&xcall_capture, 0, 0, 0);
1123                 while (atomic_read(&smp_capture_registry) != ncpus)
1124                         rmb();
1125 #ifdef CAPTURE_DEBUG
1126                 printk("done\n");
1127 #endif
1128         }
1129 }
1130
1131 void smp_release(void)
1132 {
1133         if (atomic_dec_and_test(&smp_capture_depth)) {
1134 #ifdef CAPTURE_DEBUG
1135                 printk("CPU[%d]: Giving pardon to "
1136                        "imprisoned penguins\n",
1137                        smp_processor_id());
1138 #endif
1139                 penguins_are_doing_time = 0;
1140                 membar_storeload_storestore();
1141                 atomic_dec(&smp_capture_registry);
1142         }
1143 }
1144
1145 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1146  * can service tlb flush xcalls...
1147  */
1148 extern void prom_world(int);
1149
1150 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1151 {
1152         clear_softint(1 << irq);
1153
1154         preempt_disable();
1155
1156         __asm__ __volatile__("flushw");
1157         prom_world(1);
1158         atomic_inc(&smp_capture_registry);
1159         membar_storeload_storestore();
1160         while (penguins_are_doing_time)
1161                 rmb();
1162         atomic_dec(&smp_capture_registry);
1163         prom_world(0);
1164
1165         preempt_enable();
1166 }
1167
1168 /* /proc/profile writes can call this, don't __init it please. */
1169 int setup_profiling_timer(unsigned int multiplier)
1170 {
1171         return -EINVAL;
1172 }
1173
1174 void __init smp_prepare_cpus(unsigned int max_cpus)
1175 {
1176 }
1177
1178 void __devinit smp_prepare_boot_cpu(void)
1179 {
1180 }
1181
1182 void __init smp_setup_processor_id(void)
1183 {
1184         if (tlb_type == spitfire)
1185                 xcall_deliver = spitfire_xcall_deliver;
1186         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1187                 xcall_deliver = cheetah_xcall_deliver;
1188         else
1189                 xcall_deliver = hypervisor_xcall_deliver;
1190 }
1191
1192 void __devinit smp_fill_in_sib_core_maps(void)
1193 {
1194         unsigned int i;
1195
1196         for_each_present_cpu(i) {
1197                 unsigned int j;
1198
1199                 cpus_clear(cpu_core_map[i]);
1200                 if (cpu_data(i).core_id == 0) {
1201                         cpu_set(i, cpu_core_map[i]);
1202                         continue;
1203                 }
1204
1205                 for_each_present_cpu(j) {
1206                         if (cpu_data(i).core_id ==
1207                             cpu_data(j).core_id)
1208                                 cpu_set(j, cpu_core_map[i]);
1209                 }
1210         }
1211
1212         for_each_present_cpu(i) {
1213                 unsigned int j;
1214
1215                 cpus_clear(per_cpu(cpu_sibling_map, i));
1216                 if (cpu_data(i).proc_id == -1) {
1217                         cpu_set(i, per_cpu(cpu_sibling_map, i));
1218                         continue;
1219                 }
1220
1221                 for_each_present_cpu(j) {
1222                         if (cpu_data(i).proc_id ==
1223                             cpu_data(j).proc_id)
1224                                 cpu_set(j, per_cpu(cpu_sibling_map, i));
1225                 }
1226         }
1227 }
1228
1229 int __cpuinit __cpu_up(unsigned int cpu)
1230 {
1231         int ret = smp_boot_one_cpu(cpu);
1232
1233         if (!ret) {
1234                 cpu_set(cpu, smp_commenced_mask);
1235                 while (!cpu_isset(cpu, cpu_online_map))
1236                         mb();
1237                 if (!cpu_isset(cpu, cpu_online_map)) {
1238                         ret = -ENODEV;
1239                 } else {
1240                         /* On SUN4V, writes to %tick and %stick are
1241                          * not allowed.
1242                          */
1243                         if (tlb_type != hypervisor)
1244                                 smp_synchronize_one_tick(cpu);
1245                 }
1246         }
1247         return ret;
1248 }
1249
1250 #ifdef CONFIG_HOTPLUG_CPU
1251 void cpu_play_dead(void)
1252 {
1253         int cpu = smp_processor_id();
1254         unsigned long pstate;
1255
1256         idle_task_exit();
1257
1258         if (tlb_type == hypervisor) {
1259                 struct trap_per_cpu *tb = &trap_block[cpu];
1260
1261                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1262                                 tb->cpu_mondo_pa, 0);
1263                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1264                                 tb->dev_mondo_pa, 0);
1265                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1266                                 tb->resum_mondo_pa, 0);
1267                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1268                                 tb->nonresum_mondo_pa, 0);
1269         }
1270
1271         cpu_clear(cpu, smp_commenced_mask);
1272         membar_safe("#Sync");
1273
1274         local_irq_disable();
1275
1276         __asm__ __volatile__(
1277                 "rdpr   %%pstate, %0\n\t"
1278                 "wrpr   %0, %1, %%pstate"
1279                 : "=r" (pstate)
1280                 : "i" (PSTATE_IE));
1281
1282         while (1)
1283                 barrier();
1284 }
1285
1286 int __cpu_disable(void)
1287 {
1288         int cpu = smp_processor_id();
1289         cpuinfo_sparc *c;
1290         int i;
1291
1292         for_each_cpu_mask(i, cpu_core_map[cpu])
1293                 cpu_clear(cpu, cpu_core_map[i]);
1294         cpus_clear(cpu_core_map[cpu]);
1295
1296         for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
1297                 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
1298         cpus_clear(per_cpu(cpu_sibling_map, cpu));
1299
1300         c = &cpu_data(cpu);
1301
1302         c->core_id = 0;
1303         c->proc_id = -1;
1304
1305         spin_lock(&call_lock);
1306         cpu_clear(cpu, cpu_online_map);
1307         spin_unlock(&call_lock);
1308
1309         smp_wmb();
1310
1311         /* Make sure no interrupts point to this cpu.  */
1312         fixup_irqs();
1313
1314         local_irq_enable();
1315         mdelay(1);
1316         local_irq_disable();
1317
1318         return 0;
1319 }
1320
1321 void __cpu_die(unsigned int cpu)
1322 {
1323         int i;
1324
1325         for (i = 0; i < 100; i++) {
1326                 smp_rmb();
1327                 if (!cpu_isset(cpu, smp_commenced_mask))
1328                         break;
1329                 msleep(100);
1330         }
1331         if (cpu_isset(cpu, smp_commenced_mask)) {
1332                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1333         } else {
1334 #if defined(CONFIG_SUN_LDOMS)
1335                 unsigned long hv_err;
1336                 int limit = 100;
1337
1338                 do {
1339                         hv_err = sun4v_cpu_stop(cpu);
1340                         if (hv_err == HV_EOK) {
1341                                 cpu_clear(cpu, cpu_present_map);
1342                                 break;
1343                         }
1344                 } while (--limit > 0);
1345                 if (limit <= 0) {
1346                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1347                                hv_err);
1348                 }
1349 #endif
1350         }
1351 }
1352 #endif
1353
1354 void __init smp_cpus_done(unsigned int max_cpus)
1355 {
1356 }
1357
1358 void smp_send_reschedule(int cpu)
1359 {
1360         xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1361                       &cpumask_of_cpu(cpu));
1362 }
1363
1364 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1365 {
1366         clear_softint(1 << irq);
1367 }
1368
1369 /* This is a nop because we capture all other cpus
1370  * anyways when making the PROM active.
1371  */
1372 void smp_send_stop(void)
1373 {
1374 }
1375
1376 unsigned long __per_cpu_base __read_mostly;
1377 unsigned long __per_cpu_shift __read_mostly;
1378
1379 EXPORT_SYMBOL(__per_cpu_base);
1380 EXPORT_SYMBOL(__per_cpu_shift);
1381
1382 void __init real_setup_per_cpu_areas(void)
1383 {
1384         unsigned long paddr, goal, size, i;
1385         char *ptr;
1386
1387         /* Copy section for each CPU (we discard the original) */
1388         goal = PERCPU_ENOUGH_ROOM;
1389
1390         __per_cpu_shift = PAGE_SHIFT;
1391         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1392                 __per_cpu_shift++;
1393
1394         paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1395         if (!paddr) {
1396                 prom_printf("Cannot allocate per-cpu memory.\n");
1397                 prom_halt();
1398         }
1399
1400         ptr = __va(paddr);
1401         __per_cpu_base = ptr - __per_cpu_start;
1402
1403         for (i = 0; i < NR_CPUS; i++, ptr += size)
1404                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1405
1406         /* Setup %g5 for the boot cpu.  */
1407         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1408 }