arch/sparc64/kernel/smp.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/lmb.h>
  24
  25 #include <asm/head.h>
  26 #include <asm/ptrace.h>
  27 #include <asm/atomic.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/cpudata.h>
  31 #include <asm/hvtramp.h>
  32 #include <asm/io.h>
  33 #include <asm/timer.h>
  34
  35 #include <asm/irq.h>
  36 #include <asm/irq_regs.h>
  37 #include <asm/page.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/oplib.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/sections.h>
  44 #include <asm/prom.h>
  45 #include <asm/mdesc.h>
  46 #include <asm/ldc.h>
  47 #include <asm/hypervisor.h>
  48
  49 int sparc64_multi_core __read_mostly;
  50
  51 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
  52 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  53 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  54 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  55         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  56
  57 EXPORT_SYMBOL(cpu_possible_map);
  58 EXPORT_SYMBOL(cpu_online_map);
  59 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  60 EXPORT_SYMBOL(cpu_core_map);
  61
  62 static cpumask_t smp_commenced_mask;
  63
  64 void smp_info(struct seq_file *m)
  65 {
  66         int i;
  67
  68         seq_printf(m, "State:\n");
  69         for_each_online_cpu(i)
  70                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  71 }
  72
  73 void smp_bogo(struct seq_file *m)
  74 {
  75         int i;
  76
  77         for_each_online_cpu(i)
  78                 seq_printf(m,
  79                            "Cpu%dClkTck\t: %016lx\n",
  80                            i, cpu_data(i).clock_tick);
  81 }
  82
  83 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
  84
  85 extern void setup_sparc64_timer(void);
  86
  87 static volatile unsigned long callin_flag = 0;
  88
  89 void __cpuinit smp_callin(void)
  90 {
  91         int cpuid = hard_smp_processor_id();
  92
  93         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  94
  95         if (tlb_type == hypervisor)
  96                 sun4v_ktsb_register();
  97
  98         __flush_tlb_all();
  99
 100         setup_sparc64_timer();
 101
 102         if (cheetah_pcache_forced_on)
 103                 cheetah_enable_pcache();
 104
 105         local_irq_enable();
 106
 107         callin_flag = 1;
 108         __asm__ __volatile__("membar #Sync\n\t"
 109                              "flush  %%g6" : : : "memory");
 110
 111         /* Clear this or we will die instantly when we
 112          * schedule back to this idler...
 113          */
 114         current_thread_info()->new_child = 0;
 115
 116         /* Attach to the address space of init_task. */
 117         atomic_inc(&init_mm.mm_count);
 118         current->active_mm = &init_mm;
 119
 120         while (!cpu_isset(cpuid, smp_commenced_mask))
 121                 rmb();
 122
 123         spin_lock(&call_lock);
 124         cpu_set(cpuid, cpu_online_map);
 125         spin_unlock(&call_lock);
 126
 127         /* idle thread is expected to have preempt disabled */
 128         preempt_disable();
 129 }
 130
 131 void cpu_panic(void)
 132 {
 133         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 134         panic("SMP bolixed\n");
 135 }
 136
 137 /* This tick register synchronization scheme is taken entirely from
 138  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 139  *
 140  * The only change I've made is to rework it so that the master
 141  * initiates the synchonization instead of the slave. -DaveM
 142  */
 143
 144 #define MASTER  0
 145 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 146
 147 #define NUM_ROUNDS      64      /* magic value */
 148 #define NUM_ITERS       5       /* likewise */
 149
 150 static DEFINE_SPINLOCK(itc_sync_lock);
 151 static unsigned long go[SLAVE + 1];
 152
 153 #define DEBUG_TICK_SYNC 0
 154
 155 static inline long get_delta (long *rt, long *master)
 156 {
 157         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 158         unsigned long tcenter, t0, t1, tm;
 159         unsigned long i;
 160
 161         for (i = 0; i < NUM_ITERS; i++) {
 162                 t0 = tick_ops->get_tick();
 163                 go[MASTER] = 1;
 164                 membar_storeload();
 165                 while (!(tm = go[SLAVE]))
 166                         rmb();
 167                 go[SLAVE] = 0;
 168                 wmb();
 169                 t1 = tick_ops->get_tick();
 170
 171                 if (t1 - t0 < best_t1 - best_t0)
 172                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 173         }
 174
 175         *rt = best_t1 - best_t0;
 176         *master = best_tm - best_t0;
 177
 178         /* average best_t0 and best_t1 without overflow: */
 179         tcenter = (best_t0/2 + best_t1/2);
 180         if (best_t0 % 2 + best_t1 % 2 == 2)
 181                 tcenter++;
 182         return tcenter - best_tm;
 183 }
 184
 185 void smp_synchronize_tick_client(void)
 186 {
 187         long i, delta, adj, adjust_latency = 0, done = 0;
 188         unsigned long flags, rt, master_time_stamp, bound;
 189 #if DEBUG_TICK_SYNC
 190         struct {
 191                 long rt;        /* roundtrip time */
 192                 long master;    /* master's timestamp */
 193                 long diff;      /* difference between midpoint and master's timestamp */
 194                 long lat;       /* estimate of itc adjustment latency */
 195         } t[NUM_ROUNDS];
 196 #endif
 197
 198         go[MASTER] = 1;
 199
 200         while (go[MASTER])
 201                 rmb();
 202
 203         local_irq_save(flags);
 204         {
 205                 for (i = 0; i < NUM_ROUNDS; i++) {
 206                         delta = get_delta(&rt, &master_time_stamp);
 207                         if (delta == 0) {
 208                                 done = 1;       /* let's lock on to this... */
 209                                 bound = rt;
 210                         }
 211
 212                         if (!done) {
 213                                 if (i > 0) {
 214                                         adjust_latency += -delta;
 215                                         adj = -delta + adjust_latency/4;
 216                                 } else
 217                                         adj = -delta;
 218
 219                                 tick_ops->add_tick(adj);
 220                         }
 221 #if DEBUG_TICK_SYNC
 222                         t[i].rt = rt;
 223                         t[i].master = master_time_stamp;
 224                         t[i].diff = delta;
 225                         t[i].lat = adjust_latency/4;
 226 #endif
 227                 }
 228         }
 229         local_irq_restore(flags);
 230
 231 #if DEBUG_TICK_SYNC
 232         for (i = 0; i < NUM_ROUNDS; i++)
 233                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 234                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 235 #endif
 236
 237         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 238                "(last diff %ld cycles, maxerr %lu cycles)\n",
 239                smp_processor_id(), delta, rt);
 240 }
 241
 242 static void smp_start_sync_tick_client(int cpu);
 243
 244 static void smp_synchronize_one_tick(int cpu)
 245 {
 246         unsigned long flags, i;
 247
 248         go[MASTER] = 0;
 249
 250         smp_start_sync_tick_client(cpu);
 251
 252         /* wait for client to be ready */
 253         while (!go[MASTER])
 254                 rmb();
 255
 256         /* now let the client proceed into his loop */
 257         go[MASTER] = 0;
 258         membar_storeload();
 259
 260         spin_lock_irqsave(&itc_sync_lock, flags);
 261         {
 262                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 263                         while (!go[MASTER])
 264                                 rmb();
 265                         go[MASTER] = 0;
 266                         wmb();
 267                         go[SLAVE] = tick_ops->get_tick();
 268                         membar_storeload();
 269                 }
 270         }
 271         spin_unlock_irqrestore(&itc_sync_lock, flags);
 272 }
 273
 274 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 275 /* XXX Put this in some common place. XXX */
 276 static unsigned long kimage_addr_to_ra(void *p)
 277 {
 278         unsigned long val = (unsigned long) p;
 279
 280         return kern_base + (val - KERNBASE);
 281 }
 282
 283 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
 284 {
 285         extern unsigned long sparc64_ttable_tl0;
 286         extern unsigned long kern_locked_tte_data;
 287         struct hvtramp_descr *hdesc;
 288         unsigned long trampoline_ra;
 289         struct trap_per_cpu *tb;
 290         u64 tte_vaddr, tte_data;
 291         unsigned long hv_err;
 292         int i;
 293
 294         hdesc = kzalloc(sizeof(*hdesc) +
 295                         (sizeof(struct hvtramp_mapping) *
 296                          num_kernel_image_mappings - 1),
 297                         GFP_KERNEL);
 298         if (!hdesc) {
 299                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 300                        "hvtramp_descr.\n");
 301                 return;
 302         }
 303
 304         hdesc->cpu = cpu;
 305         hdesc->num_mappings = num_kernel_image_mappings;
 306
 307         tb = &trap_block[cpu];
 308         tb->hdesc = hdesc;
 309
 310         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 311         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 312
 313         hdesc->thread_reg = thread_reg;
 314
 315         tte_vaddr = (unsigned long) KERNBASE;
 316         tte_data = kern_locked_tte_data;
 317
 318         for (i = 0; i < hdesc->num_mappings; i++) {
 319                 hdesc->maps[i].vaddr = tte_vaddr;
 320                 hdesc->maps[i].tte   = tte_data;
 321                 tte_vaddr += 0x400000;
 322                 tte_data  += 0x400000;
 323         }
 324
 325         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 326
 327         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 328                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 329                                  __pa(hdesc));
 330         if (hv_err)
 331                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 332                        "gives error %lu\n", hv_err);
 333 }
 334 #endif
 335
 336 extern unsigned long sparc64_cpu_startup;
 337
 338 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 339  * 32-bits (I think) so to be safe we have it read the pointer
 340  * contained here so we work on >4GB machines. -DaveM
 341  */
 342 static struct thread_info *cpu_new_thread = NULL;
 343
 344 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 345 {
 346         struct trap_per_cpu *tb = &trap_block[cpu];
 347         unsigned long entry =
 348                 (unsigned long)(&sparc64_cpu_startup);
 349         unsigned long cookie =
 350                 (unsigned long)(&cpu_new_thread);
 351         struct task_struct *p;
 352         int timeout, ret;
 353
 354         p = fork_idle(cpu);
 355         if (IS_ERR(p))
 356                 return PTR_ERR(p);
 357         callin_flag = 0;
 358         cpu_new_thread = task_thread_info(p);
 359
 360         if (tlb_type == hypervisor) {
 361 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 362                 if (ldom_domaining_enabled)
 363                         ldom_startcpu_cpuid(cpu,
 364                                             (unsigned long) cpu_new_thread);
 365                 else
 366 #endif
 367                         prom_startcpu_cpuid(cpu, entry, cookie);
 368         } else {
 369                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 370
 371                 prom_startcpu(dp->node, entry, cookie);
 372         }
 373
 374         for (timeout = 0; timeout < 50000; timeout++) {
 375                 if (callin_flag)
 376                         break;
 377                 udelay(100);
 378         }
 379
 380         if (callin_flag) {
 381                 ret = 0;
 382         } else {
 383                 printk("Processor %d is stuck.\n", cpu);
 384                 ret = -ENODEV;
 385         }
 386         cpu_new_thread = NULL;
 387
 388         if (tb->hdesc) {
 389                 kfree(tb->hdesc);
 390                 tb->hdesc = NULL;
 391         }
 392
 393         return ret;
 394 }
 395
 396 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 397 {
 398         u64 result, target;
 399         int stuck, tmp;
 400
 401         if (this_is_starfire) {
 402                 /* map to real upaid */
 403                 cpu = (((cpu & 0x3c) << 1) |
 404                         ((cpu & 0x40) >> 4) |
 405                         (cpu & 0x3));
 406         }
 407
 408         target = (cpu << 14) | 0x70;
 409 again:
 410         /* Ok, this is the real Spitfire Errata #54.
 411          * One must read back from a UDB internal register
 412          * after writes to the UDB interrupt dispatch, but
 413          * before the membar Sync for that write.
 414          * So we use the high UDB control register (ASI 0x7f,
 415          * ADDR 0x20) for the dummy read. -DaveM
 416          */
 417         tmp = 0x40;
 418         __asm__ __volatile__(
 419         "wrpr   %1, %2, %%pstate\n\t"
 420         "stxa   %4, [%0] %3\n\t"
 421         "stxa   %5, [%0+%8] %3\n\t"
 422         "add    %0, %8, %0\n\t"
 423         "stxa   %6, [%0+%8] %3\n\t"
 424         "membar #Sync\n\t"
 425         "stxa   %%g0, [%7] %3\n\t"
 426         "membar #Sync\n\t"
 427         "mov    0x20, %%g1\n\t"
 428         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 429         "membar #Sync"
 430         : "=r" (tmp)
 431         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 432           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 433           "r" (0x10), "0" (tmp)
 434         : "g1");
 435
 436         /* NOTE: PSTATE_IE is still clear. */
 437         stuck = 100000;
 438         do {
 439                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 440                         : "=r" (result)
 441                         : "i" (ASI_INTR_DISPATCH_STAT));
 442                 if (result == 0) {
 443                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 444                                              : : "r" (pstate));
 445                         return;
 446                 }
 447                 stuck -= 1;
 448                 if (stuck == 0)
 449                         break;
 450         } while (result & 0x1);
 451         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 452                              : : "r" (pstate));
 453         if (stuck == 0) {
 454                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 455                        smp_processor_id(), result);
 456         } else {
 457                 udelay(2);
 458                 goto again;
 459         }
 460 }
 461
 462 static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 463 {
 464         u64 *mondo, data0, data1, data2;
 465         u16 *cpu_list;
 466         u64 pstate;
 467         int i;
 468
 469         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 470         cpu_list = __va(tb->cpu_list_pa);
 471         mondo = __va(tb->cpu_mondo_block_pa);
 472         data0 = mondo[0];
 473         data1 = mondo[1];
 474         data2 = mondo[2];
 475         for (i = 0; i < cnt; i++)
 476                 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
 477 }
 478
 479 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 480  * packet, but we have no use for that.  However we do take advantage of
 481  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 482  */
 483 static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 484 {
 485         int nack_busy_id, is_jbus, need_more;
 486         u64 *mondo, pstate, ver, busy_mask;
 487         u16 *cpu_list;
 488
 489         cpu_list = __va(tb->cpu_list_pa);
 490         mondo = __va(tb->cpu_mondo_block_pa);
 491
 492         /* Unfortunately, someone at Sun had the brilliant idea to make the
 493          * busy/nack fields hard-coded by ITID number for this Ultra-III
 494          * derivative processor.
 495          */
 496         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 497         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 498                    (ver >> 32) == __SERRANO_ID);
 499
 500         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 501
 502 retry:
 503         need_more = 0;
 504         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 505                              : : "r" (pstate), "i" (PSTATE_IE));
 506
 507         /* Setup the dispatch data registers. */
 508         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 509                              "stxa      %1, [%4] %6\n\t"
 510                              "stxa      %2, [%5] %6\n\t"
 511                              "membar    #Sync\n\t"
 512                              : /* no outputs */
 513                              : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
 514                                "r" (0x40), "r" (0x50), "r" (0x60),
 515                                "i" (ASI_INTR_W));
 516
 517         nack_busy_id = 0;
 518         busy_mask = 0;
 519         {
 520                 int i;
 521
 522                 for (i = 0; i < cnt; i++) {
 523                         u64 target, nr;
 524
 525                         nr = cpu_list[i];
 526                         if (nr == 0xffff)
 527                                 continue;
 528
 529                         target = (nr << 14) | 0x70;
 530                         if (is_jbus) {
 531                                 busy_mask |= (0x1UL << (nr * 2));
 532                         } else {
 533                                 target |= (nack_busy_id << 24);
 534                                 busy_mask |= (0x1UL <<
 535                                               (nack_busy_id * 2));
 536                         }
 537                         __asm__ __volatile__(
 538                                 "stxa   %%g0, [%0] %1\n\t"
 539                                 "membar #Sync\n\t"
 540                                 : /* no outputs */
 541                                 : "r" (target), "i" (ASI_INTR_W));
 542                         nack_busy_id++;
 543                         if (nack_busy_id == 32) {
 544                                 need_more = 1;
 545                                 break;
 546                         }
 547                 }
 548         }
 549
 550         /* Now, poll for completion. */
 551         {
 552                 u64 dispatch_stat, nack_mask;
 553                 long stuck;
 554
 555                 stuck = 100000 * nack_busy_id;
 556                 nack_mask = busy_mask << 1;
 557                 do {
 558                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 559                                              : "=r" (dispatch_stat)
 560                                              : "i" (ASI_INTR_DISPATCH_STAT));
 561                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 562                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 563                                                      : : "r" (pstate));
 564                                 if (unlikely(need_more)) {
 565                                         int i, this_cnt = 0;
 566                                         for (i = 0; i < cnt; i++) {
 567                                                 if (cpu_list[i] == 0xffff)
 568                                                         continue;
 569                                                 cpu_list[i] = 0xffff;
 570                                                 this_cnt++;
 571                                                 if (this_cnt == 32)
 572                                                         break;
 573                                         }
 574                                         goto retry;
 575                                 }
 576                                 return;
 577                         }
 578                         if (!--stuck)
 579                                 break;
 580                 } while (dispatch_stat & busy_mask);
 581
 582                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 583                                      : : "r" (pstate));
 584
 585                 if (dispatch_stat & busy_mask) {
 586                         /* Busy bits will not clear, continue instead
 587                          * of freezing up on this cpu.
 588                          */
 589                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 590                                smp_processor_id(), dispatch_stat);
 591                 } else {
 592                         int i, this_busy_nack = 0;
 593
 594                         /* Delay some random time with interrupts enabled
 595                          * to prevent deadlock.
 596                          */
 597                         udelay(2 * nack_busy_id);
 598
 599                         /* Clear out the mask bits for cpus which did not
 600                          * NACK us.
 601                          */
 602                         for (i = 0; i < cnt; i++) {
 603                                 u64 check_mask, nr;
 604
 605                                 nr = cpu_list[i];
 606                                 if (nr == 0xffff)
 607                                         continue;
 608
 609                                 if (is_jbus)
 610                                         check_mask = (0x2UL << (2*nr));
 611                                 else
 612                                         check_mask = (0x2UL <<
 613                                                       this_busy_nack);
 614                                 if ((dispatch_stat & check_mask) == 0)
 615                                         cpu_list[i] = 0xffff;
 616                                 this_busy_nack += 2;
 617                                 if (this_busy_nack == 64)
 618                                         break;
 619                         }
 620
 621                         goto retry;
 622                 }
 623         }
 624 }
 625
 626 /* Multi-cpu list version.  */
 627 static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 628 {
 629         int retries, this_cpu, prev_sent, i;
 630         unsigned long status;
 631         cpumask_t error_mask;
 632         u16 *cpu_list;
 633
 634         this_cpu = smp_processor_id();
 635
 636         cpu_list = __va(tb->cpu_list_pa);
 637
 638         cpus_clear(error_mask);
 639         retries = 0;
 640         prev_sent = 0;
 641         do {
 642                 int forward_progress, n_sent;
 643
 644                 status = sun4v_cpu_mondo_send(cnt,
 645                                               tb->cpu_list_pa,
 646                                               tb->cpu_mondo_block_pa);
 647
 648                 /* HV_EOK means all cpus received the xcall, we're done.  */
 649                 if (likely(status == HV_EOK))
 650                         break;
 651
 652                 /* First, see if we made any forward progress.
 653                  *
 654                  * The hypervisor indicates successful sends by setting
 655                  * cpu list entries to the value 0xffff.
 656                  */
 657                 n_sent = 0;
 658                 for (i = 0; i < cnt; i++) {
 659                         if (likely(cpu_list[i] == 0xffff))
 660                                 n_sent++;
 661                 }
 662
 663                 forward_progress = 0;
 664                 if (n_sent > prev_sent)
 665                         forward_progress = 1;
 666
 667                 prev_sent = n_sent;
 668
 669                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 670                  * in the list are in error state.  Use the cpu_state()
 671                  * hypervisor call to find out which cpus are in error state.
 672                  */
 673                 if (unlikely(status == HV_ECPUERROR)) {
 674                         for (i = 0; i < cnt; i++) {
 675                                 long err;
 676                                 u16 cpu;
 677
 678                                 cpu = cpu_list[i];
 679                                 if (cpu == 0xffff)
 680                                         continue;
 681
 682                                 err = sun4v_cpu_state(cpu);
 683                                 if (err >= 0 &&
 684                                     err == HV_CPU_STATE_ERROR) {
 685                                         cpu_list[i] = 0xffff;
 686                                         cpu_set(cpu, error_mask);
 687                                 }
 688                         }
 689                 } else if (unlikely(status != HV_EWOULDBLOCK))
 690                         goto fatal_mondo_error;
 691
 692                 /* Don't bother rewriting the CPU list, just leave the
 693                  * 0xffff and non-0xffff entries in there and the
 694                  * hypervisor will do the right thing.
 695                  *
 696                  * Only advance timeout state if we didn't make any
 697                  * forward progress.
 698                  */
 699                 if (unlikely(!forward_progress)) {
 700                         if (unlikely(++retries > 10000))
 701                                 goto fatal_mondo_timeout;
 702
 703                         /* Delay a little bit to let other cpus catch up
 704                          * on their cpu mondo queue work.
 705                          */
 706                         udelay(2 * cnt);
 707                 }
 708         } while (1);
 709
 710         if (unlikely(!cpus_empty(error_mask)))
 711                 goto fatal_mondo_cpu_error;
 712
 713         return;
 714
 715 fatal_mondo_cpu_error:
 716         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 717                "were in error state\n",
 718                this_cpu);
 719         printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
 720         for_each_cpu_mask_nr(i, error_mask)
 721                 printk("%d ", i);
 722         printk("]\n");
 723         return;
 724
 725 fatal_mondo_timeout:
 726         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 727                " progress after %d retries.\n",
 728                this_cpu, retries);
 729         goto dump_cpu_list_and_out;
 730
 731 fatal_mondo_error:
 732         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 733                this_cpu, status);
 734         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 735                "mondo_block_pa(%lx)\n",
 736                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 737
 738 dump_cpu_list_and_out:
 739         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 740         for (i = 0; i < cnt; i++)
 741                 printk("%u ", cpu_list[i]);
 742         printk("]\n");
 743 }
 744
 745 static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
 746
 747 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 748 {
 749         struct trap_per_cpu *tb;
 750         int this_cpu, i, cnt;
 751         unsigned long flags;
 752         u16 *cpu_list;
 753         u64 *mondo;
 754
 755         /* We have to do this whole thing with interrupts fully disabled.
 756          * Otherwise if we send an xcall from interrupt context it will
 757          * corrupt both our mondo block and cpu list state.
 758          *
 759          * One consequence of this is that we cannot use timeout mechanisms
 760          * that depend upon interrupts being delivered locally.  So, for
 761          * example, we cannot sample jiffies and expect it to advance.
 762          *
 763          * Fortunately, udelay() uses %stick/%tick so we can use that.
 764          */
 765         local_irq_save(flags);
 766
 767         this_cpu = smp_processor_id();
 768         tb = &trap_block[this_cpu];
 769
 770         mondo = __va(tb->cpu_mondo_block_pa);
 771         mondo[0] = data0;
 772         mondo[1] = data1;
 773         mondo[2] = data2;
 774         wmb();
 775
 776         cpu_list = __va(tb->cpu_list_pa);
 777
 778         /* Setup the initial cpu list.  */
 779         cnt = 0;
 780         for_each_cpu_mask_nr(i, *mask) {
 781                 if (i == this_cpu || !cpu_online(i))
 782                         continue;
 783                 cpu_list[cnt++] = i;
 784         }
 785
 786         if (cnt)
 787                 xcall_deliver_impl(tb, cnt);
 788
 789         local_irq_restore(flags);
 790 }
 791
 792 /* Send cross call to all processors mentioned in MASK_P
 793  * except self.  Really, there are only two cases currently,
 794  * "&cpu_online_map" and "&mm->cpu_vm_mask".
 795  */
 796 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask_p)
 797 {
 798         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 799         int this_cpu = get_cpu();
 800         cpumask_t mask;
 801
 802         mask = *mask_p;
 803         if (mask_p != &cpu_online_map)
 804                 cpus_and(mask, mask, cpu_online_map);
 805         cpu_clear(this_cpu, mask);
 806
 807         xcall_deliver(data0, data1, data2, &mask);
 808         /* NOTE: Caller runs local copy on master. */
 809
 810         put_cpu();
 811 }
 812
 813 extern unsigned long xcall_sync_tick;
 814
 815 static void smp_start_sync_tick_client(int cpu)
 816 {
 817         xcall_deliver((u64) &xcall_sync_tick, 0, 0,
 818                       &cpumask_of_cpu(cpu));
 819 }
 820
 821 extern unsigned long xcall_call_function;
 822
 823 void arch_send_call_function_ipi(cpumask_t mask)
 824 {
 825         xcall_deliver((u64) &xcall_call_function, 0, 0, &mask);
 826 }
 827
 828 extern unsigned long xcall_call_function_single;
 829
 830 void arch_send_call_function_single_ipi(int cpu)
 831 {
 832         xcall_deliver((u64) &xcall_call_function_single, 0, 0,
 833                       &cpumask_of_cpu(cpu));
 834 }
 835
 836 /* Send cross call to all processors except self. */
 837 #define smp_cross_call(func, ctx, data1, data2) \
 838         smp_cross_call_masked(func, ctx, data1, data2, &cpu_online_map)
 839
 840 void smp_call_function_client(int irq, struct pt_regs *regs)
 841 {
 842         clear_softint(1 << irq);
 843         generic_smp_call_function_interrupt();
 844 }
 845
 846 void smp_call_function_single_client(int irq, struct pt_regs *regs)
 847 {
 848         clear_softint(1 << irq);
 849         generic_smp_call_function_single_interrupt();
 850 }
 851
 852 static void tsb_sync(void *info)
 853 {
 854         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 855         struct mm_struct *mm = info;
 856
 857         /* It is not valid to test "currrent->active_mm == mm" here.
 858          *
 859          * The value of "current" is not changed atomically with
 860          * switch_mm().  But that's OK, we just need to check the
 861          * current cpu's trap block PGD physical address.
 862          */
 863         if (tp->pgd_paddr == __pa(mm->pgd))
 864                 tsb_context_switch(mm);
 865 }
 866
 867 void smp_tsb_sync(struct mm_struct *mm)
 868 {
 869         smp_call_function_mask(mm->cpu_vm_mask, tsb_sync, mm, 1);
 870 }
 871
 872 extern unsigned long xcall_flush_tlb_mm;
 873 extern unsigned long xcall_flush_tlb_pending;
 874 extern unsigned long xcall_flush_tlb_kernel_range;
 875 #ifdef CONFIG_MAGIC_SYSRQ
 876 extern unsigned long xcall_fetch_glob_regs;
 877 #endif
 878 extern unsigned long xcall_receive_signal;
 879 extern unsigned long xcall_new_mmu_context_version;
 880 #ifdef CONFIG_KGDB
 881 extern unsigned long xcall_kgdb_capture;
 882 #endif
 883
 884 #ifdef DCACHE_ALIASING_POSSIBLE
 885 extern unsigned long xcall_flush_dcache_page_cheetah;
 886 #endif
 887 extern unsigned long xcall_flush_dcache_page_spitfire;
 888
 889 #ifdef CONFIG_DEBUG_DCFLUSH
 890 extern atomic_t dcpage_flushes;
 891 extern atomic_t dcpage_flushes_xcall;
 892 #endif
 893
 894 static inline void __local_flush_dcache_page(struct page *page)
 895 {
 896 #ifdef DCACHE_ALIASING_POSSIBLE
 897         __flush_dcache_page(page_address(page),
 898                             ((tlb_type == spitfire) &&
 899                              page_mapping(page) != NULL));
 900 #else
 901         if (page_mapping(page) != NULL &&
 902             tlb_type == spitfire)
 903                 __flush_icache_page(__pa(page_address(page)));
 904 #endif
 905 }
 906
 907 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 908 {
 909         cpumask_t mask = cpumask_of_cpu(cpu);
 910         int this_cpu;
 911
 912         if (tlb_type == hypervisor)
 913                 return;
 914
 915 #ifdef CONFIG_DEBUG_DCFLUSH
 916         atomic_inc(&dcpage_flushes);
 917 #endif
 918
 919         this_cpu = get_cpu();
 920
 921         if (cpu == this_cpu) {
 922                 __local_flush_dcache_page(page);
 923         } else if (cpu_online(cpu)) {
 924                 void *pg_addr = page_address(page);
 925                 u64 data0 = 0;
 926
 927                 if (tlb_type == spitfire) {
 928                         data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 929                         if (page_mapping(page) != NULL)
 930                                 data0 |= ((u64)1 << 32);
 931                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 932 #ifdef DCACHE_ALIASING_POSSIBLE
 933                         data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 934 #endif
 935                 }
 936                 if (data0) {
 937                         xcall_deliver(data0, __pa(pg_addr),
 938                                       (u64) pg_addr, &mask);
 939 #ifdef CONFIG_DEBUG_DCFLUSH
 940                         atomic_inc(&dcpage_flushes_xcall);
 941 #endif
 942                 }
 943         }
 944
 945         put_cpu();
 946 }
 947
 948 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 949 {
 950         cpumask_t mask = cpu_online_map;
 951         void *pg_addr;
 952         int this_cpu;
 953         u64 data0;
 954
 955         if (tlb_type == hypervisor)
 956                 return;
 957
 958         this_cpu = get_cpu();
 959
 960         cpu_clear(this_cpu, mask);
 961
 962 #ifdef CONFIG_DEBUG_DCFLUSH
 963         atomic_inc(&dcpage_flushes);
 964 #endif
 965         if (cpus_empty(mask))
 966                 goto flush_self;
 967         data0 = 0;
 968         pg_addr = page_address(page);
 969         if (tlb_type == spitfire) {
 970                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 971                 if (page_mapping(page) != NULL)
 972                         data0 |= ((u64)1 << 32);
 973         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 974 #ifdef DCACHE_ALIASING_POSSIBLE
 975                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 976 #endif
 977         }
 978         if (data0) {
 979                 xcall_deliver(data0, __pa(pg_addr),
 980                               (u64) pg_addr, &mask);
 981 #ifdef CONFIG_DEBUG_DCFLUSH
 982                 atomic_inc(&dcpage_flushes_xcall);
 983 #endif
 984         }
 985  flush_self:
 986         __local_flush_dcache_page(page);
 987
 988         put_cpu();
 989 }
 990
 991 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 992 {
 993         struct mm_struct *mm;
 994         unsigned long flags;
 995
 996         clear_softint(1 << irq);
 997
 998         /* See if we need to allocate a new TLB context because
 999          * the version of the one we are using is now out of date.
1000          */
1001         mm = current->active_mm;
1002         if (unlikely(!mm || (mm == &init_mm)))
1003                 return;
1004
1005         spin_lock_irqsave(&mm->context.lock, flags);
1006
1007         if (unlikely(!CTX_VALID(mm->context)))
1008                 get_new_mmu_context(mm);
1009
1010         spin_unlock_irqrestore(&mm->context.lock, flags);
1011
1012         load_secondary_context(mm);
1013         __flush_tlb_mm(CTX_HWBITS(mm->context),
1014                        SECONDARY_CONTEXT);
1015 }
1016
1017 void smp_new_mmu_context_version(void)
1018 {
1019         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1020 }
1021
1022 #ifdef CONFIG_KGDB
1023 void kgdb_roundup_cpus(unsigned long flags)
1024 {
1025         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1026 }
1027 #endif
1028
1029 #ifdef CONFIG_MAGIC_SYSRQ
1030 void smp_fetch_global_regs(void)
1031 {
1032         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1033 }
1034 #endif
1035
1036 /* We know that the window frames of the user have been flushed
1037  * to the stack before we get here because all callers of us
1038  * are flush_tlb_*() routines, and these run after flush_cache_*()
1039  * which performs the flushw.
1040  *
1041  * The SMP TLB coherency scheme we use works as follows:
1042  *
1043  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1044  *    space has (potentially) executed on, this is the heuristic
1045  *    we use to avoid doing cross calls.
1046  *
1047  *    Also, for flushing from kswapd and also for clones, we
1048  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1049  *
1050  * 2) TLB context numbers are shared globally across all processors
1051  *    in the system, this allows us to play several games to avoid
1052  *    cross calls.
1053  *
1054  *    One invariant is that when a cpu switches to a process, and
1055  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1056  *    current cpu's bit set, that tlb context is flushed locally.
1057  *
1058  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1059  *    cross calls when we want to flush the currently running process's
1060  *    tlb state.  This is done by clearing all cpu bits except the current
1061  *    processor's in current->active_mm->cpu_vm_mask and performing the
1062  *    flush locally only.  This will force any subsequent cpus which run
1063  *    this task to flush the context from the local tlb if the process
1064  *    migrates to another cpu (again).
1065  *
1066  * 3) For shared address spaces (threads) and swapping we bite the
1067  *    bullet for most cases and perform the cross call (but only to
1068  *    the cpus listed in cpu_vm_mask).
1069  *
1070  *    The performance gain from "optimizing" away the cross call for threads is
1071  *    questionable (in theory the big win for threads is the massive sharing of
1072  *    address space state across processors).
1073  */
1074
1075 /* This currently is only used by the hugetlb arch pre-fault
1076  * hook on UltraSPARC-III+ and later when changing the pagesize
1077  * bits of the context register for an address space.
1078  */
1079 void smp_flush_tlb_mm(struct mm_struct *mm)
1080 {
1081         u32 ctx = CTX_HWBITS(mm->context);
1082         int cpu = get_cpu();
1083
1084         if (atomic_read(&mm->mm_users) == 1) {
1085                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1086                 goto local_flush_and_out;
1087         }
1088
1089         smp_cross_call_masked(&xcall_flush_tlb_mm,
1090                               ctx, 0, 0,
1091                               &mm->cpu_vm_mask);
1092
1093 local_flush_and_out:
1094         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1095
1096         put_cpu();
1097 }
1098
1099 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1100 {
1101         u32 ctx = CTX_HWBITS(mm->context);
1102         int cpu = get_cpu();
1103
1104         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1105                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1106         else
1107                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1108                                       ctx, nr, (unsigned long) vaddrs,
1109                                       &mm->cpu_vm_mask);
1110
1111         __flush_tlb_pending(ctx, nr, vaddrs);
1112
1113         put_cpu();
1114 }
1115
1116 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1117 {
1118         start &= PAGE_MASK;
1119         end    = PAGE_ALIGN(end);
1120         if (start != end) {
1121                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1122                                0, start, end);
1123
1124                 __flush_tlb_kernel_range(start, end);
1125         }
1126 }
1127
1128 /* CPU capture. */
1129 /* #define CAPTURE_DEBUG */
1130 extern unsigned long xcall_capture;
1131
1132 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1133 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1134 static unsigned long penguins_are_doing_time;
1135
1136 void smp_capture(void)
1137 {
1138         int result = atomic_add_ret(1, &smp_capture_depth);
1139
1140         if (result == 1) {
1141                 int ncpus = num_online_cpus();
1142
1143 #ifdef CAPTURE_DEBUG
1144                 printk("CPU[%d]: Sending penguins to jail...",
1145                        smp_processor_id());
1146 #endif
1147                 penguins_are_doing_time = 1;
1148                 membar_storestore_loadstore();
1149                 atomic_inc(&smp_capture_registry);
1150                 smp_cross_call(&xcall_capture, 0, 0, 0);
1151                 while (atomic_read(&smp_capture_registry) != ncpus)
1152                         rmb();
1153 #ifdef CAPTURE_DEBUG
1154                 printk("done\n");
1155 #endif
1156         }
1157 }
1158
1159 void smp_release(void)
1160 {
1161         if (atomic_dec_and_test(&smp_capture_depth)) {
1162 #ifdef CAPTURE_DEBUG
1163                 printk("CPU[%d]: Giving pardon to "
1164                        "imprisoned penguins\n",
1165                        smp_processor_id());
1166 #endif
1167                 penguins_are_doing_time = 0;
1168                 membar_storeload_storestore();
1169                 atomic_dec(&smp_capture_registry);
1170         }
1171 }
1172
1173 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1174  * can service tlb flush xcalls...
1175  */
1176 extern void prom_world(int);
1177
1178 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1179 {
1180         clear_softint(1 << irq);
1181
1182         preempt_disable();
1183
1184         __asm__ __volatile__("flushw");
1185         prom_world(1);
1186         atomic_inc(&smp_capture_registry);
1187         membar_storeload_storestore();
1188         while (penguins_are_doing_time)
1189                 rmb();
1190         atomic_dec(&smp_capture_registry);
1191         prom_world(0);
1192
1193         preempt_enable();
1194 }
1195
1196 /* /proc/profile writes can call this, don't __init it please. */
1197 int setup_profiling_timer(unsigned int multiplier)
1198 {
1199         return -EINVAL;
1200 }
1201
1202 void __init smp_prepare_cpus(unsigned int max_cpus)
1203 {
1204 }
1205
1206 void __devinit smp_prepare_boot_cpu(void)
1207 {
1208 }
1209
1210 void __init smp_setup_processor_id(void)
1211 {
1212         if (tlb_type == spitfire)
1213                 xcall_deliver_impl = spitfire_xcall_deliver;
1214         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1215                 xcall_deliver_impl = cheetah_xcall_deliver;
1216         else
1217                 xcall_deliver_impl = hypervisor_xcall_deliver;
1218 }
1219
1220 void __devinit smp_fill_in_sib_core_maps(void)
1221 {
1222         unsigned int i;
1223
1224         for_each_present_cpu(i) {
1225                 unsigned int j;
1226
1227                 cpus_clear(cpu_core_map[i]);
1228                 if (cpu_data(i).core_id == 0) {
1229                         cpu_set(i, cpu_core_map[i]);
1230                         continue;
1231                 }
1232
1233                 for_each_present_cpu(j) {
1234                         if (cpu_data(i).core_id ==
1235                             cpu_data(j).core_id)
1236                                 cpu_set(j, cpu_core_map[i]);
1237                 }
1238         }
1239
1240         for_each_present_cpu(i) {
1241                 unsigned int j;
1242
1243                 cpus_clear(per_cpu(cpu_sibling_map, i));
1244                 if (cpu_data(i).proc_id == -1) {
1245                         cpu_set(i, per_cpu(cpu_sibling_map, i));
1246                         continue;
1247                 }
1248
1249                 for_each_present_cpu(j) {
1250                         if (cpu_data(i).proc_id ==
1251                             cpu_data(j).proc_id)
1252                                 cpu_set(j, per_cpu(cpu_sibling_map, i));
1253                 }
1254         }
1255 }
1256
1257 int __cpuinit __cpu_up(unsigned int cpu)
1258 {
1259         int ret = smp_boot_one_cpu(cpu);
1260
1261         if (!ret) {
1262                 cpu_set(cpu, smp_commenced_mask);
1263                 while (!cpu_isset(cpu, cpu_online_map))
1264                         mb();
1265                 if (!cpu_isset(cpu, cpu_online_map)) {
1266                         ret = -ENODEV;
1267                 } else {
1268                         /* On SUN4V, writes to %tick and %stick are
1269                          * not allowed.
1270                          */
1271                         if (tlb_type != hypervisor)
1272                                 smp_synchronize_one_tick(cpu);
1273                 }
1274         }
1275         return ret;
1276 }
1277
1278 #ifdef CONFIG_HOTPLUG_CPU
1279 void cpu_play_dead(void)
1280 {
1281         int cpu = smp_processor_id();
1282         unsigned long pstate;
1283
1284         idle_task_exit();
1285
1286         if (tlb_type == hypervisor) {
1287                 struct trap_per_cpu *tb = &trap_block[cpu];
1288
1289                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1290                                 tb->cpu_mondo_pa, 0);
1291                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1292                                 tb->dev_mondo_pa, 0);
1293                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1294                                 tb->resum_mondo_pa, 0);
1295                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1296                                 tb->nonresum_mondo_pa, 0);
1297         }
1298
1299         cpu_clear(cpu, smp_commenced_mask);
1300         membar_safe("#Sync");
1301
1302         local_irq_disable();
1303
1304         __asm__ __volatile__(
1305                 "rdpr   %%pstate, %0\n\t"
1306                 "wrpr   %0, %1, %%pstate"
1307                 : "=r" (pstate)
1308                 : "i" (PSTATE_IE));
1309
1310         while (1)
1311                 barrier();
1312 }
1313
1314 int __cpu_disable(void)
1315 {
1316         int cpu = smp_processor_id();
1317         cpuinfo_sparc *c;
1318         int i;
1319
1320         for_each_cpu_mask(i, cpu_core_map[cpu])
1321                 cpu_clear(cpu, cpu_core_map[i]);
1322         cpus_clear(cpu_core_map[cpu]);
1323
1324         for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
1325                 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
1326         cpus_clear(per_cpu(cpu_sibling_map, cpu));
1327
1328         c = &cpu_data(cpu);
1329
1330         c->core_id = 0;
1331         c->proc_id = -1;
1332
1333         spin_lock(&call_lock);
1334         cpu_clear(cpu, cpu_online_map);
1335         spin_unlock(&call_lock);
1336
1337         smp_wmb();
1338
1339         /* Make sure no interrupts point to this cpu.  */
1340         fixup_irqs();
1341
1342         local_irq_enable();
1343         mdelay(1);
1344         local_irq_disable();
1345
1346         return 0;
1347 }
1348
1349 void __cpu_die(unsigned int cpu)
1350 {
1351         int i;
1352
1353         for (i = 0; i < 100; i++) {
1354                 smp_rmb();
1355                 if (!cpu_isset(cpu, smp_commenced_mask))
1356                         break;
1357                 msleep(100);
1358         }
1359         if (cpu_isset(cpu, smp_commenced_mask)) {
1360                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1361         } else {
1362 #if defined(CONFIG_SUN_LDOMS)
1363                 unsigned long hv_err;
1364                 int limit = 100;
1365
1366                 do {
1367                         hv_err = sun4v_cpu_stop(cpu);
1368                         if (hv_err == HV_EOK) {
1369                                 cpu_clear(cpu, cpu_present_map);
1370                                 break;
1371                         }
1372                 } while (--limit > 0);
1373                 if (limit <= 0) {
1374                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1375                                hv_err);
1376                 }
1377 #endif
1378         }
1379 }
1380 #endif
1381
1382 void __init smp_cpus_done(unsigned int max_cpus)
1383 {
1384 }
1385
1386 void smp_send_reschedule(int cpu)
1387 {
1388         xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1389                       &cpumask_of_cpu(cpu));
1390 }
1391
1392 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1393 {
1394         clear_softint(1 << irq);
1395 }
1396
1397 /* This is a nop because we capture all other cpus
1398  * anyways when making the PROM active.
1399  */
1400 void smp_send_stop(void)
1401 {
1402 }
1403
1404 unsigned long __per_cpu_base __read_mostly;
1405 unsigned long __per_cpu_shift __read_mostly;
1406
1407 EXPORT_SYMBOL(__per_cpu_base);
1408 EXPORT_SYMBOL(__per_cpu_shift);
1409
1410 void __init real_setup_per_cpu_areas(void)
1411 {
1412         unsigned long paddr, goal, size, i;
1413         char *ptr;
1414
1415         /* Copy section for each CPU (we discard the original) */
1416         goal = PERCPU_ENOUGH_ROOM;
1417
1418         __per_cpu_shift = PAGE_SHIFT;
1419         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1420                 __per_cpu_shift++;
1421
1422         paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1423         if (!paddr) {
1424                 prom_printf("Cannot allocate per-cpu memory.\n");
1425                 prom_halt();
1426         }
1427
1428         ptr = __va(paddr);
1429         __per_cpu_base = ptr - __per_cpu_start;
1430
1431         for (i = 0; i < NR_CPUS; i++, ptr += size)
1432                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1433
1434         /* Setup %g5 for the boot cpu.  */
1435         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1436 }