1 /* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
2 * head.S: Initial boot code for the Sparc64 port of Linux.
4 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
10 #include <linux/config.h>
11 #include <linux/version.h>
12 #include <linux/errno.h>
13 #include <asm/thread_info.h>
15 #include <asm/pstate.h>
16 #include <asm/ptrace.h>
17 #include <asm/spitfire.h>
19 #include <asm/pgtable.h>
20 #include <asm/errno.h>
21 #include <asm/signal.h>
22 #include <asm/processor.h>
27 #include <asm/ttable.h>
30 /* This section from from _start to sparc64_boot_end should fit into
31 * 0x0000.0000.0040.4000 to 0x0000.0000.0040.8000 and will be sharing space
32 * with bootup_user_stack, which is from 0x0000.0000.0040.4000 to
33 * 0x0000.0000.0040.6000 and empty_bad_page, which is from
34 * 0x0000.0000.0040.6000 to 0x0000.0000.0040.8000.
38 .globl start, _start, stext, _stext
46 flushw /* Flush register file. */
48 /* This stuff has to be in sync with SILO and other potential boot loaders
49 * Fields should be kept upward compatible and whenever any change is made,
50 * HdrS version should be incremented.
52 .global root_flags, ram_flags, root_dev
53 .global sparc_ramdisk_image, sparc_ramdisk_size
54 .global sparc_ramdisk_image64
57 .word LINUX_VERSION_CODE
61 * 0x0300 : Supports being located at other than 0x4000
62 * 0x0202 : Supports kernel params string
63 * 0x0201 : Supports reboot_command
65 .half 0x0301 /* HdrS version */
79 sparc_ramdisk_image64:
83 /* PROM cif handler code address is in %o4. */
88 be,pn %xcc, sparc64_boot_after_remap
91 /* We need to remap the kernel. Use position independant
92 * code to remap us to KERNBASE.
94 * SILO can invoke us with 32-bit address masking enabled,
95 * so make sure that's clear.
98 andn %g1, PSTATE_AM, %g1
99 wrpr %g1, 0x0, %pstate
102 .globl prom_finddev_name, prom_chosen_path
103 .globl prom_getprop_name, prom_mmu_name
104 .globl prom_callmethod_name, prom_translate_name
105 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
106 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
107 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
116 prom_callmethod_name:
125 prom_mmu_ihandle_cache:
129 prom_boot_mapping_mode:
132 prom_boot_mapping_phys_high:
134 prom_boot_mapping_phys_low:
138 mov (1b - prom_finddev_name), %l1
139 mov (1b - prom_chosen_path), %l2
140 mov (1b - prom_boot_mapped_pc), %l3
145 sub %sp, (192 + 128), %sp
147 /* chosen_node = prom_finddevice("/chosen") */
148 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
150 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
151 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
152 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
153 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
155 add %sp, (2047 + 128), %o0 ! argument array
157 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
159 mov (1b - prom_getprop_name), %l1
160 mov (1b - prom_mmu_name), %l2
161 mov (1b - prom_mmu_ihandle_cache), %l5
166 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
167 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
169 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
171 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
172 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
173 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
174 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
176 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
177 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
179 add %sp, (2047 + 128), %o0 ! argument array
181 mov (1b - prom_callmethod_name), %l1
182 mov (1b - prom_translate_name), %l2
185 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
187 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
189 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
191 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
192 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
193 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
196 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
197 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
198 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
199 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
200 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
201 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
203 add %sp, (2047 + 128), %o0 ! argument array
205 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
206 mov (1b - prom_boot_mapping_mode), %l4
209 mov (1b - prom_boot_mapping_phys_high), %l4
211 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
213 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
216 /* Leave service as-is, "call-method" */
218 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
220 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
221 mov (1b - prom_map_name), %l3
223 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
224 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
226 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
227 sethi %hi(8 * 1024 * 1024), %l3
228 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
229 sethi %hi(KERNBASE), %l3
230 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
231 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
232 mov (1b - prom_boot_mapping_phys_low), %l3
235 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
237 add %sp, (2047 + 128), %o0 ! argument array
239 add %sp, (192 + 128), %sp
241 sparc64_boot_after_remap:
242 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
243 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
244 ba,pt %xcc, spitfire_boot
248 /* Preserve OBP chosen DCU and DCR register settings. */
249 ba,pt %xcc, cheetah_generic_boot
253 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
256 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
257 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
259 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
260 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
263 cheetah_generic_boot:
264 mov TSB_EXTENSION_P, %g3
265 stxa %g0, [%g3] ASI_DMMU
266 stxa %g0, [%g3] ASI_IMMU
269 mov TSB_EXTENSION_S, %g3
270 stxa %g0, [%g3] ASI_DMMU
273 mov TSB_EXTENSION_N, %g3
274 stxa %g0, [%g3] ASI_DMMU
275 stxa %g0, [%g3] ASI_IMMU
278 ba,a,pt %xcc, jump_to_sun4u_init
281 /* Typically PROM has already enabled both MMU's and both on-chip
282 * caches, but we do it here anyway just to be paranoid.
284 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
285 stxa %g1, [%g0] ASI_LSU_CONTROL
290 * Make sure we are in privileged mode, have address masking,
291 * using the ordinary globals and have enabled floating
294 * Again, typically PROM has left %pil at 13 or similar, and
295 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
297 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
306 mov PRIMARY_CONTEXT, %g7
307 stxa %g0, [%g7] ASI_DMMU
310 mov SECONDARY_CONTEXT, %g7
311 stxa %g0, [%g7] ASI_DMMU
314 BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
316 ba,pt %xcc, spitfire_tlb_fixup
320 mov 2, %g2 /* Set TLB type to cheetah+. */
321 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
323 mov 1, %g2 /* Set TLB type to cheetah. */
325 1: sethi %hi(tlb_type), %g1
326 stw %g2, [%g1 + %lo(tlb_type)]
328 /* Patch copy/page operations to cheetah optimized versions. */
329 call cheetah_patch_copyops
331 call cheetah_patch_copy_page
333 call cheetah_patch_cachetlbops
336 ba,pt %xcc, tlb_fixup_done
340 /* Set TLB type to spitfire. */
342 sethi %hi(tlb_type), %g1
343 stw %g2, [%g1 + %lo(tlb_type)]
346 sethi %hi(init_thread_union), %g6
347 or %g6, %lo(init_thread_union), %g6
348 ldx [%g6 + TI_TASK], %g4
354 sllx %g1, THREAD_SHIFT, %g1
355 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
359 /* Set per-cpu pointer initially to zero, this makes
360 * the boot-cpu use the in-kernel-image per-cpu areas
361 * before setup_per_cpu_area() is invoked.
369 sethi %hi(__bss_start), %o0
370 or %o0, %lo(__bss_start), %o0
372 or %o1, %lo(_end), %o1
376 mov %l6, %o1 ! OpenPROM stack
378 mov %l7, %o0 ! OpenPROM cif handler
385 /* This is meant to allow the sharing of this code between
386 * boot processor invocation (via setup_tba() below) and
387 * secondary processor startup (via trampoline.S). The
388 * former does use this code, the latter does not yet due
389 * to some complexities. That should be fixed up at some
392 .globl setup_trap_table
396 /* Force interrupts to be disabled. Transferring over to
397 * the Linux trap table is a very delicate operation.
398 * Until we are actually on the Linux trap table, we cannot
399 * get the PAGE_OFFSET linear mappings translated. We need
400 * that mapping to be setup in order to initialize the firmware
403 * So there is this window of time, from the return from
404 * prom_set_trap_table() until inherit_prom_mappings_post()
405 * (in arch/sparc64/mm/init.c) completes, during which no
406 * firmware address space accesses can be made.
409 andn %o1, PSTATE_IE, %o1
410 wrpr %o1, 0x0, %pstate
413 /* Ok, now make the final valid firmware call to jump over
414 * to the Linux trap table.
416 call prom_set_trap_table
417 sethi %hi(sparc64_ttable_tl0), %o0
419 /* Start using proper page size encodings in ctx register. */
420 sethi %hi(sparc64_kern_pri_context), %g3
421 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
422 mov PRIMARY_CONTEXT, %g1
423 stxa %g2, [%g1] ASI_DMMU
426 /* The Linux trap handlers expect various trap global registers
427 * to be setup with some fixed values. So here we set these
428 * up very carefully. These globals are:
430 * Alternate Globals (PSTATE_AG):
432 * %g6 --> current_thread_info()
434 * MMU Globals (PSTATE_MG):
437 * %g2 --> ((_PAGE_VALID | _PAGE_SZ4MB |
438 * _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
439 * ^ 0xfffff80000000000)
440 * (this %g2 value is used for computing the PAGE_OFFSET kernel
441 * TLB entries quickly, the virtual address of the fault XOR'd
442 * with this %g2 value is the PTE to load into the TLB)
443 * %g3 --> VPTE_BASE_CHEETAH or VPTE_BASE_SPITFIRE
445 * Interrupt Globals (PSTATE_IG, setup by init_irqwork_curcpu()):
447 * %g6 --> __irq_work[smp_processor_id()]
452 wrpr %o1, PSTATE_AG, %pstate
455 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
456 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
457 wrpr %o1, PSTATE_MG, %pstate
459 stxa %g0, [%g1] ASI_DMMU
461 stxa %g0, [%g1] ASI_IMMU
464 sethi %uhi(KERN_HIGHBITS), %g2
465 or %g2, %ulo(KERN_HIGHBITS), %g2
467 or %g2, KERN_LOWBITS, %g2
469 BRANCH_IF_ANY_CHEETAH(g3,g7,8f)
474 sethi %uhi(VPTE_BASE_CHEETAH), %g3
475 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
480 sethi %uhi(VPTE_BASE_SPITFIRE), %g3
481 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
489 /* Kill PROM timer */
490 sethi %hi(0x80000000), %o2
492 wr %o2, 0, %tick_cmpr
494 BRANCH_IF_ANY_CHEETAH(o2,o3,1f)
499 /* Disable STICK_INT interrupts. */
501 sethi %hi(0x80000000), %o2
506 wrpr %g0, %g0, %wstate
507 wrpr %o1, 0x0, %pstate
509 call init_irqwork_curcpu
512 /* Now we can turn interrupts back on. */
514 or %o1, PSTATE_IE, %o1
522 setup_tba: /* i0 = is_starfire */
525 /* The boot processor is the only cpu which invokes this
526 * routine, the other cpus set things up via trampoline.S.
527 * So save the OBP trap table address here.
530 sethi %hi(prom_tba), %o1
531 or %o1, %lo(prom_tba), %o1
534 call setup_trap_table
541 * The following skips make sure the trap table in ttable.S is aligned
542 * on a 32K boundary as required by the v9 specs for TBA register.
545 .skip 0x2000 + _start - sparc64_boot_end
546 bootup_user_stack_end:
550 /* This is just a hack to fool make depend config.h discovering
551 strategy: As the .S files below need config.h, but
552 make depend does not find it for them, we include config.h
563 #include "winfixup.S"
566 /* This is just anal retentiveness on my part... */
571 .globl prom_tba, tlb_type
573 tlb_type: .word 0 /* Must NOT end up in BSS */
574 .section ".fixup",#alloc,#execinstr
576 .globl __ret_efault, __retl_efault
579 restore %g0, -EFAULT, %o0