arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/slab.h>
  14 #include <linux/vmalloc.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/kdebug.h>
  22
  23 #include <asm/bitext.h>
  24 #include <asm/page.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/io.h>
  28 #include <asm/vaddrs.h>
  29 #include <asm/traps.h>
  30 #include <asm/smp.h>
  31 #include <asm/mbus.h>
  32 #include <asm/cache.h>
  33 #include <asm/oplib.h>
  34 #include <asm/sbus.h>
  35 #include <asm/asi.h>
  36 #include <asm/msi.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/io-unit.h>
  39 #include <asm/cacheflush.h>
  40 #include <asm/tlbflush.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49
  50 #include <asm/btfixup.h>
  51
  52 enum mbus_module srmmu_modtype;
  53 unsigned int hwbug_bitmask;
  54 int vac_cache_size;
  55 int vac_line_size;
  56
  57 extern struct resource sparc_iomap;
  58
  59 extern unsigned long last_valid_pfn;
  60
  61 extern unsigned long page_kernel;
  62
  63 pgd_t *srmmu_swapper_pg_dir;
  64
  65 #ifdef CONFIG_SMP
  66 #define FLUSH_BEGIN(mm)
  67 #define FLUSH_END
  68 #else
  69 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  70 #define FLUSH_END       }
  71 #endif
  72
  73 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  74 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  75
  76 int flush_page_for_dma_global = 1;
  77
  78 #ifdef CONFIG_SMP
  79 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  80 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  81 #endif
  82
  83 char *srmmu_name;
  84
  85 ctxd_t *srmmu_ctx_table_phys;
  86 ctxd_t *srmmu_context_table;
  87
  88 int viking_mxcc_present;
  89 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  90
  91 int is_hypersparc;
  92
  93 /*
  94  * In general all page table modifications should use the V8 atomic
  95  * swap instruction.  This insures the mmu and the cpu are in sync
  96  * with respect to ref/mod bits in the page tables.
  97  */
  98 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
  99 {
 100         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 101         return value;
 102 }
 103
 104 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 105 {
 106         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 107 }
 108
 109 /* The very generic SRMMU page table operations. */
 110 static inline int srmmu_device_memory(unsigned long x)
 111 {
 112         return ((x & 0xF0000000) != 0);
 113 }
 114
 115 int srmmu_cache_pagetables;
 116
 117 /* these will be initialized in srmmu_nocache_calcsize() */
 118 unsigned long srmmu_nocache_size;
 119 unsigned long srmmu_nocache_end;
 120
 121 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 122 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 123
 124 /* The context table is a nocache user with the biggest alignment needs. */
 125 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 126
 127 void *srmmu_nocache_pool;
 128 void *srmmu_nocache_bitmap;
 129 static struct bit_map srmmu_nocache_map;
 130
 131 static unsigned long srmmu_pte_pfn(pte_t pte)
 132 {
 133         if (srmmu_device_memory(pte_val(pte))) {
 134                 /* Just return something that will cause
 135                  * pfn_valid() to return false.  This makes
 136                  * copy_one_pte() to just directly copy to
 137                  * PTE over.
 138                  */
 139                 return ~0UL;
 140         }
 141         return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
 142 }
 143
 144 static struct page *srmmu_pmd_page(pmd_t pmd)
 145 {
 146
 147         if (srmmu_device_memory(pmd_val(pmd)))
 148                 BUG();
 149         return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
 150 }
 151
 152 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 153 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 154
 155
 156 static inline int srmmu_pte_none(pte_t pte)
 157 { return !(pte_val(pte) & 0xFFFFFFF); }
 158
 159 static inline int srmmu_pte_present(pte_t pte)
 160 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 161
 162 static inline void srmmu_pte_clear(pte_t *ptep)
 163 { srmmu_set_pte(ptep, __pte(0)); }
 164
 165 static inline int srmmu_pmd_none(pmd_t pmd)
 166 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 167
 168 static inline int srmmu_pmd_bad(pmd_t pmd)
 169 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 170
 171 static inline int srmmu_pmd_present(pmd_t pmd)
 172 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 173
 174 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
 175         int i;
 176         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
 177                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
 178 }
 179
 180 static inline int srmmu_pgd_none(pgd_t pgd)
 181 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 182
 183 static inline int srmmu_pgd_bad(pgd_t pgd)
 184 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 185
 186 static inline int srmmu_pgd_present(pgd_t pgd)
 187 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 188
 189 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 190 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 191
 192 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 193 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 194
 195 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 196 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 197
 198 static inline pte_t srmmu_pte_mkold(pte_t pte)
 199 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 200
 201 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 202 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 203
 204 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 205 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 206
 207 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 208 { return __pte(pte_val(pte) | SRMMU_REF);}
 209
 210 /*
 211  * Conversion functions: convert a page and protection to a page entry,
 212  * and a page entry and page directory to the page they refer to.
 213  */
 214 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 215 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 216
 217 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 218 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 219
 220 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 221 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 222
 223 /* XXX should we hyper_flush_whole_icache here - Anton */
 224 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 225 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 226
 227 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 228 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 229
 230 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 231 {
 232         unsigned long ptp;      /* Physical address, shifted right by 4 */
 233         int i;
 234
 235         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 236         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 237                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 238                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 239         }
 240 }
 241
 242 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 243 {
 244         unsigned long ptp;      /* Physical address, shifted right by 4 */
 245         int i;
 246
 247         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 248         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 249                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 250                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 251         }
 252 }
 253
 254 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 255 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 256
 257 /* to find an entry in a top-level page table... */
 258 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 259 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 260
 261 /* Find an entry in the second-level page table.. */
 262 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 263 {
 264         return (pmd_t *) srmmu_pgd_page(*dir) +
 265             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 266 }
 267
 268 /* Find an entry in the third-level page table.. */
 269 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 270 {
 271         void *pte;
 272
 273         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 274         return (pte_t *) pte +
 275             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 276 }
 277
 278 static unsigned long srmmu_swp_type(swp_entry_t entry)
 279 {
 280         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 281 }
 282
 283 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 284 {
 285         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 286 }
 287
 288 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 289 {
 290         return (swp_entry_t) {
 291                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 292                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 293 }
 294
 295 /*
 296  * size: bytes to allocate in the nocache area.
 297  * align: bytes, number to align at.
 298  * Returns the virtual address of the allocated area.
 299  */
 300 static unsigned long __srmmu_get_nocache(int size, int align)
 301 {
 302         int offset;
 303
 304         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 305                 printk("Size 0x%x too small for nocache request\n", size);
 306                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 307         }
 308         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 309                 printk("Size 0x%x unaligned int nocache request\n", size);
 310                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 311         }
 312         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 313
 314         offset = bit_map_string_get(&srmmu_nocache_map,
 315                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 316                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 317         if (offset == -1) {
 318                 printk("srmmu: out of nocache %d: %d/%d\n",
 319                     size, (int) srmmu_nocache_size,
 320                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 321                 return 0;
 322         }
 323
 324         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 325 }
 326
 327 unsigned inline long srmmu_get_nocache(int size, int align)
 328 {
 329         unsigned long tmp;
 330
 331         tmp = __srmmu_get_nocache(size, align);
 332
 333         if (tmp)
 334                 memset((void *)tmp, 0, size);
 335
 336         return tmp;
 337 }
 338
 339 void srmmu_free_nocache(unsigned long vaddr, int size)
 340 {
 341         int offset;
 342
 343         if (vaddr < SRMMU_NOCACHE_VADDR) {
 344                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 345                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 346                 BUG();
 347         }
 348         if (vaddr+size > srmmu_nocache_end) {
 349                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 350                     vaddr, srmmu_nocache_end);
 351                 BUG();
 352         }
 353         if (size & (size-1)) {
 354                 printk("Size 0x%x is not a power of 2\n", size);
 355                 BUG();
 356         }
 357         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 358                 printk("Size 0x%x is too small\n", size);
 359                 BUG();
 360         }
 361         if (vaddr & (size-1)) {
 362                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 363                 BUG();
 364         }
 365
 366         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 367         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 368
 369         bit_map_clear(&srmmu_nocache_map, offset, size);
 370 }
 371
 372 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);
 373
 374 extern unsigned long probe_memory(void);        /* in fault.c */
 375
 376 /*
 377  * Reserve nocache dynamically proportionally to the amount of
 378  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 379  */
 380 void srmmu_nocache_calcsize(void)
 381 {
 382         unsigned long sysmemavail = probe_memory() / 1024;
 383         int srmmu_nocache_npages;
 384
 385         srmmu_nocache_npages =
 386                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 387
 388  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 389         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 390         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 391                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 392
 393         /* anything above 1280 blows up */
 394         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 395                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 396
 397         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 398         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 399 }
 400
 401 void __init srmmu_nocache_init(void)
 402 {
 403         unsigned int bitmap_bits;
 404         pgd_t *pgd;
 405         pmd_t *pmd;
 406         pte_t *pte;
 407         unsigned long paddr, vaddr;
 408         unsigned long pteval;
 409
 410         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 411
 412         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 413                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 414         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 415
 416         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 417         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 418
 419         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 420         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 421         init_mm.pgd = srmmu_swapper_pg_dir;
 422
 423         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 424
 425         paddr = __pa((unsigned long)srmmu_nocache_pool);
 426         vaddr = SRMMU_NOCACHE_VADDR;
 427
 428         while (vaddr < srmmu_nocache_end) {
 429                 pgd = pgd_offset_k(vaddr);
 430                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 431                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 432
 433                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 434
 435                 if (srmmu_cache_pagetables)
 436                         pteval |= SRMMU_CACHE;
 437
 438                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 439
 440                 vaddr += PAGE_SIZE;
 441                 paddr += PAGE_SIZE;
 442         }
 443
 444         flush_cache_all();
 445         flush_tlb_all();
 446 }
 447
 448 static inline pgd_t *srmmu_get_pgd_fast(void)
 449 {
 450         pgd_t *pgd = NULL;
 451
 452         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 453         if (pgd) {
 454                 pgd_t *init = pgd_offset_k(0);
 455                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 456                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 457                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 458         }
 459
 460         return pgd;
 461 }
 462
 463 static void srmmu_free_pgd_fast(pgd_t *pgd)
 464 {
 465         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 466 }
 467
 468 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 469 {
 470         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 471 }
 472
 473 static void srmmu_pmd_free(pmd_t * pmd)
 474 {
 475         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 476 }
 477
 478 /*
 479  * Hardware needs alignment to 256 only, but we align to whole page size
 480  * to reduce fragmentation problems due to the buddy principle.
 481  * XXX Provide actual fragmentation statistics in /proc.
 482  *
 483  * Alignments up to the page size are the same for physical and virtual
 484  * addresses of the nocache area.
 485  */
 486 static pte_t *
 487 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 488 {
 489         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 490 }
 491
 492 static struct page *
 493 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 494 {
 495         unsigned long pte;
 496
 497         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 498                 return NULL;
 499         return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 500 }
 501
 502 static void srmmu_free_pte_fast(pte_t *pte)
 503 {
 504         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 505 }
 506
 507 static void srmmu_pte_free(struct page *pte)
 508 {
 509         unsigned long p;
 510
 511         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 512         if (p == 0)
 513                 BUG();
 514         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 515         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 516         srmmu_free_nocache(p, PTE_SIZE);
 517 }
 518
 519 /*
 520  */
 521 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 522 {
 523         struct ctx_list *ctxp;
 524
 525         ctxp = ctx_free.next;
 526         if(ctxp != &ctx_free) {
 527                 remove_from_ctx_list(ctxp);
 528                 add_to_used_ctxlist(ctxp);
 529                 mm->context = ctxp->ctx_number;
 530                 ctxp->ctx_mm = mm;
 531                 return;
 532         }
 533         ctxp = ctx_used.next;
 534         if(ctxp->ctx_mm == old_mm)
 535                 ctxp = ctxp->next;
 536         if(ctxp == &ctx_used)
 537                 panic("out of mmu contexts");
 538         flush_cache_mm(ctxp->ctx_mm);
 539         flush_tlb_mm(ctxp->ctx_mm);
 540         remove_from_ctx_list(ctxp);
 541         add_to_used_ctxlist(ctxp);
 542         ctxp->ctx_mm->context = NO_CONTEXT;
 543         ctxp->ctx_mm = mm;
 544         mm->context = ctxp->ctx_number;
 545 }
 546
 547 static inline void free_context(int context)
 548 {
 549         struct ctx_list *ctx_old;
 550
 551         ctx_old = ctx_list_pool + context;
 552         remove_from_ctx_list(ctx_old);
 553         add_to_free_ctxlist(ctx_old);
 554 }
 555
 556
 557 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 558     struct task_struct *tsk, int cpu)
 559 {
 560         if(mm->context == NO_CONTEXT) {
 561                 spin_lock(&srmmu_context_spinlock);
 562                 alloc_context(old_mm, mm);
 563                 spin_unlock(&srmmu_context_spinlock);
 564                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 565         }
 566
 567         if (is_hypersparc)
 568                 hyper_flush_whole_icache();
 569
 570         srmmu_set_context(mm->context);
 571 }
 572
 573 /* Low level IO area allocation on the SRMMU. */
 574 static inline void srmmu_mapioaddr(unsigned long physaddr,
 575     unsigned long virt_addr, int bus_type)
 576 {
 577         pgd_t *pgdp;
 578         pmd_t *pmdp;
 579         pte_t *ptep;
 580         unsigned long tmp;
 581
 582         physaddr &= PAGE_MASK;
 583         pgdp = pgd_offset_k(virt_addr);
 584         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 585         ptep = srmmu_pte_offset(pmdp, virt_addr);
 586         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 587
 588         /*
 589          * I need to test whether this is consistent over all
 590          * sun4m's.  The bus_type represents the upper 4 bits of
 591          * 36-bit physical address on the I/O space lines...
 592          */
 593         tmp |= (bus_type << 28);
 594         tmp |= SRMMU_PRIV;
 595         __flush_page_to_ram(virt_addr);
 596         srmmu_set_pte(ptep, __pte(tmp));
 597 }
 598
 599 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 600     unsigned long xva, unsigned int len)
 601 {
 602         while (len != 0) {
 603                 len -= PAGE_SIZE;
 604                 srmmu_mapioaddr(xpa, xva, bus);
 605                 xva += PAGE_SIZE;
 606                 xpa += PAGE_SIZE;
 607         }
 608         flush_tlb_all();
 609 }
 610
 611 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 612 {
 613         pgd_t *pgdp;
 614         pmd_t *pmdp;
 615         pte_t *ptep;
 616
 617         pgdp = pgd_offset_k(virt_addr);
 618         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 619         ptep = srmmu_pte_offset(pmdp, virt_addr);
 620
 621         /* No need to flush uncacheable page. */
 622         srmmu_pte_clear(ptep);
 623 }
 624
 625 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 626 {
 627         while (len != 0) {
 628                 len -= PAGE_SIZE;
 629                 srmmu_unmapioaddr(virt_addr);
 630                 virt_addr += PAGE_SIZE;
 631         }
 632         flush_tlb_all();
 633 }
 634
 635 /*
 636  * On the SRMMU we do not have the problems with limited tlb entries
 637  * for mapping kernel pages, so we just take things from the free page
 638  * pool.  As a side effect we are putting a little too much pressure
 639  * on the gfp() subsystem.  This setup also makes the logic of the
 640  * iommu mapping code a lot easier as we can transparently handle
 641  * mappings on the kernel stack without any special code as we did
 642  * need on the sun4c.
 643  */
 644 struct thread_info *srmmu_alloc_thread_info(void)
 645 {
 646         struct thread_info *ret;
 647
 648         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 649                                                      THREAD_INFO_ORDER);
 650 #ifdef CONFIG_DEBUG_STACK_USAGE
 651         if (ret)
 652                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 653 #endif /* DEBUG_STACK_USAGE */
 654
 655         return ret;
 656 }
 657
 658 static void srmmu_free_thread_info(struct thread_info *ti)
 659 {
 660         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 661 }
 662
 663 /* tsunami.S */
 664 extern void tsunami_flush_cache_all(void);
 665 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 666 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 667 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 668 extern void tsunami_flush_page_to_ram(unsigned long page);
 669 extern void tsunami_flush_page_for_dma(unsigned long page);
 670 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 671 extern void tsunami_flush_tlb_all(void);
 672 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 673 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 674 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 675 extern void tsunami_setup_blockops(void);
 676
 677 /*
 678  * Workaround, until we find what's going on with Swift. When low on memory,
 679  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 680  * out it is already in page tables/ fault again on the same instruction.
 681  * I really don't understand it, have checked it and contexts
 682  * are right, flush_tlb_all is done as well, and it faults again...
 683  * Strange. -jj
 684  *
 685  * The following code is a deadwood that may be necessary when
 686  * we start to make precise page flushes again. --zaitcev
 687  */
 688 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 689 {
 690 #if 0
 691         static unsigned long last;
 692         unsigned int val;
 693         /* unsigned int n; */
 694
 695         if (address == last) {
 696                 val = srmmu_hwprobe(address);
 697                 if (val != 0 && pte_val(pte) != val) {
 698                         printk("swift_update_mmu_cache: "
 699                             "addr %lx put %08x probed %08x from %p\n",
 700                             address, pte_val(pte), val,
 701                             __builtin_return_address(0));
 702                         srmmu_flush_whole_tlb();
 703                 }
 704         }
 705         last = address;
 706 #endif
 707 }
 708
 709 /* swift.S */
 710 extern void swift_flush_cache_all(void);
 711 extern void swift_flush_cache_mm(struct mm_struct *mm);
 712 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 713                                     unsigned long start, unsigned long end);
 714 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 715 extern void swift_flush_page_to_ram(unsigned long page);
 716 extern void swift_flush_page_for_dma(unsigned long page);
 717 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 718 extern void swift_flush_tlb_all(void);
 719 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 720 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 721                                   unsigned long start, unsigned long end);
 722 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 723
 724 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 725 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 726 {
 727         int cctx, ctx1;
 728
 729         page &= PAGE_MASK;
 730         if ((ctx1 = vma->vm_mm->context) != -1) {
 731                 cctx = srmmu_get_context();
 732 /* Is context # ever different from current context? P3 */
 733                 if (cctx != ctx1) {
 734                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 735                         srmmu_set_context(ctx1);
 736                         swift_flush_page(page);
 737                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 738                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 739                         srmmu_set_context(cctx);
 740                 } else {
 741                          /* Rm. prot. bits from virt. c. */
 742                         /* swift_flush_cache_all(); */
 743                         /* swift_flush_cache_page(vma, page); */
 744                         swift_flush_page(page);
 745
 746                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 747                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 748                         /* same as above: srmmu_flush_tlb_page() */
 749                 }
 750         }
 751 }
 752 #endif
 753
 754 /*
 755  * The following are all MBUS based SRMMU modules, and therefore could
 756  * be found in a multiprocessor configuration.  On the whole, these
 757  * chips seems to be much more touchy about DVMA and page tables
 758  * with respect to cache coherency.
 759  */
 760
 761 /* Cypress flushes. */
 762 static void cypress_flush_cache_all(void)
 763 {
 764         volatile unsigned long cypress_sucks;
 765         unsigned long faddr, tagval;
 766
 767         flush_user_windows();
 768         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 769                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 770                                      "=r" (tagval) :
 771                                      "r" (faddr), "r" (0x40000),
 772                                      "i" (ASI_M_DATAC_TAG));
 773
 774                 /* If modified and valid, kick it. */
 775                 if((tagval & 0x60) == 0x60)
 776                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 777         }
 778 }
 779
 780 static void cypress_flush_cache_mm(struct mm_struct *mm)
 781 {
 782         register unsigned long a, b, c, d, e, f, g;
 783         unsigned long flags, faddr;
 784         int octx;
 785
 786         FLUSH_BEGIN(mm)
 787         flush_user_windows();
 788         local_irq_save(flags);
 789         octx = srmmu_get_context();
 790         srmmu_set_context(mm->context);
 791         a = 0x20; b = 0x40; c = 0x60;
 792         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 793
 794         faddr = (0x10000 - 0x100);
 795         goto inside;
 796         do {
 797                 faddr -= 0x100;
 798         inside:
 799                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 800                                      "sta %%g0, [%0 + %2] %1\n\t"
 801                                      "sta %%g0, [%0 + %3] %1\n\t"
 802                                      "sta %%g0, [%0 + %4] %1\n\t"
 803                                      "sta %%g0, [%0 + %5] %1\n\t"
 804                                      "sta %%g0, [%0 + %6] %1\n\t"
 805                                      "sta %%g0, [%0 + %7] %1\n\t"
 806                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 807                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 808                                      "r" (a), "r" (b), "r" (c), "r" (d),
 809                                      "r" (e), "r" (f), "r" (g));
 810         } while(faddr);
 811         srmmu_set_context(octx);
 812         local_irq_restore(flags);
 813         FLUSH_END
 814 }
 815
 816 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 817 {
 818         struct mm_struct *mm = vma->vm_mm;
 819         register unsigned long a, b, c, d, e, f, g;
 820         unsigned long flags, faddr;
 821         int octx;
 822
 823         FLUSH_BEGIN(mm)
 824         flush_user_windows();
 825         local_irq_save(flags);
 826         octx = srmmu_get_context();
 827         srmmu_set_context(mm->context);
 828         a = 0x20; b = 0x40; c = 0x60;
 829         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 830
 831         start &= SRMMU_REAL_PMD_MASK;
 832         while(start < end) {
 833                 faddr = (start + (0x10000 - 0x100));
 834                 goto inside;
 835                 do {
 836                         faddr -= 0x100;
 837                 inside:
 838                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 839                                              "sta %%g0, [%0 + %2] %1\n\t"
 840                                              "sta %%g0, [%0 + %3] %1\n\t"
 841                                              "sta %%g0, [%0 + %4] %1\n\t"
 842                                              "sta %%g0, [%0 + %5] %1\n\t"
 843                                              "sta %%g0, [%0 + %6] %1\n\t"
 844                                              "sta %%g0, [%0 + %7] %1\n\t"
 845                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 846                                              "r" (faddr),
 847                                              "i" (ASI_M_FLUSH_SEG),
 848                                              "r" (a), "r" (b), "r" (c), "r" (d),
 849                                              "r" (e), "r" (f), "r" (g));
 850                 } while (faddr != start);
 851                 start += SRMMU_REAL_PMD_SIZE;
 852         }
 853         srmmu_set_context(octx);
 854         local_irq_restore(flags);
 855         FLUSH_END
 856 }
 857
 858 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 859 {
 860         register unsigned long a, b, c, d, e, f, g;
 861         struct mm_struct *mm = vma->vm_mm;
 862         unsigned long flags, line;
 863         int octx;
 864
 865         FLUSH_BEGIN(mm)
 866         flush_user_windows();
 867         local_irq_save(flags);
 868         octx = srmmu_get_context();
 869         srmmu_set_context(mm->context);
 870         a = 0x20; b = 0x40; c = 0x60;
 871         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 872
 873         page &= PAGE_MASK;
 874         line = (page + PAGE_SIZE) - 0x100;
 875         goto inside;
 876         do {
 877                 line -= 0x100;
 878         inside:
 879                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 880                                              "sta %%g0, [%0 + %2] %1\n\t"
 881                                              "sta %%g0, [%0 + %3] %1\n\t"
 882                                              "sta %%g0, [%0 + %4] %1\n\t"
 883                                              "sta %%g0, [%0 + %5] %1\n\t"
 884                                              "sta %%g0, [%0 + %6] %1\n\t"
 885                                              "sta %%g0, [%0 + %7] %1\n\t"
 886                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 887                                              "r" (line),
 888                                              "i" (ASI_M_FLUSH_PAGE),
 889                                              "r" (a), "r" (b), "r" (c), "r" (d),
 890                                              "r" (e), "r" (f), "r" (g));
 891         } while(line != page);
 892         srmmu_set_context(octx);
 893         local_irq_restore(flags);
 894         FLUSH_END
 895 }
 896
 897 /* Cypress is copy-back, at least that is how we configure it. */
 898 static void cypress_flush_page_to_ram(unsigned long page)
 899 {
 900         register unsigned long a, b, c, d, e, f, g;
 901         unsigned long line;
 902
 903         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 904         page &= PAGE_MASK;
 905         line = (page + PAGE_SIZE) - 0x100;
 906         goto inside;
 907         do {
 908                 line -= 0x100;
 909         inside:
 910                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 911                                      "sta %%g0, [%0 + %2] %1\n\t"
 912                                      "sta %%g0, [%0 + %3] %1\n\t"
 913                                      "sta %%g0, [%0 + %4] %1\n\t"
 914                                      "sta %%g0, [%0 + %5] %1\n\t"
 915                                      "sta %%g0, [%0 + %6] %1\n\t"
 916                                      "sta %%g0, [%0 + %7] %1\n\t"
 917                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 918                                      "r" (line),
 919                                      "i" (ASI_M_FLUSH_PAGE),
 920                                      "r" (a), "r" (b), "r" (c), "r" (d),
 921                                      "r" (e), "r" (f), "r" (g));
 922         } while(line != page);
 923 }
 924
 925 /* Cypress is also IO cache coherent. */
 926 static void cypress_flush_page_for_dma(unsigned long page)
 927 {
 928 }
 929
 930 /* Cypress has unified L2 VIPT, from which both instructions and data
 931  * are stored.  It does not have an onboard icache of any sort, therefore
 932  * no flush is necessary.
 933  */
 934 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 935 {
 936 }
 937
 938 static void cypress_flush_tlb_all(void)
 939 {
 940         srmmu_flush_whole_tlb();
 941 }
 942
 943 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 944 {
 945         FLUSH_BEGIN(mm)
 946         __asm__ __volatile__(
 947         "lda    [%0] %3, %%g5\n\t"
 948         "sta    %2, [%0] %3\n\t"
 949         "sta    %%g0, [%1] %4\n\t"
 950         "sta    %%g5, [%0] %3\n"
 951         : /* no outputs */
 952         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 953           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 954         : "g5");
 955         FLUSH_END
 956 }
 957
 958 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 959 {
 960         struct mm_struct *mm = vma->vm_mm;
 961         unsigned long size;
 962
 963         FLUSH_BEGIN(mm)
 964         start &= SRMMU_PGDIR_MASK;
 965         size = SRMMU_PGDIR_ALIGN(end) - start;
 966         __asm__ __volatile__(
 967                 "lda    [%0] %5, %%g5\n\t"
 968                 "sta    %1, [%0] %5\n"
 969                 "1:\n\t"
 970                 "subcc  %3, %4, %3\n\t"
 971                 "bne    1b\n\t"
 972                 " sta   %%g0, [%2 + %3] %6\n\t"
 973                 "sta    %%g5, [%0] %5\n"
 974         : /* no outputs */
 975         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 976           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 977           "i" (ASI_M_FLUSH_PROBE)
 978         : "g5", "cc");
 979         FLUSH_END
 980 }
 981
 982 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 983 {
 984         struct mm_struct *mm = vma->vm_mm;
 985
 986         FLUSH_BEGIN(mm)
 987         __asm__ __volatile__(
 988         "lda    [%0] %3, %%g5\n\t"
 989         "sta    %1, [%0] %3\n\t"
 990         "sta    %%g0, [%2] %4\n\t"
 991         "sta    %%g5, [%0] %3\n"
 992         : /* no outputs */
 993         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 994           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 995         : "g5");
 996         FLUSH_END
 997 }
 998
 999 /* viking.S */
1000 extern void viking_flush_cache_all(void);
1001 extern void viking_flush_cache_mm(struct mm_struct *mm);
1002 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1003                                      unsigned long end);
1004 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1005 extern void viking_flush_page_to_ram(unsigned long page);
1006 extern void viking_flush_page_for_dma(unsigned long page);
1007 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1008 extern void viking_flush_page(unsigned long page);
1009 extern void viking_mxcc_flush_page(unsigned long page);
1010 extern void viking_flush_tlb_all(void);
1011 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1012 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1013                                    unsigned long end);
1014 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1015                                   unsigned long page);
1016 extern void sun4dsmp_flush_tlb_all(void);
1017 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1018 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1019                                    unsigned long end);
1020 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1021                                   unsigned long page);
1022
1023 /* hypersparc.S */
1024 extern void hypersparc_flush_cache_all(void);
1025 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1026 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1027 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1028 extern void hypersparc_flush_page_to_ram(unsigned long page);
1029 extern void hypersparc_flush_page_for_dma(unsigned long page);
1030 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1031 extern void hypersparc_flush_tlb_all(void);
1032 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1033 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1034 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1035 extern void hypersparc_setup_blockops(void);
1036
1037 /*
1038  * NOTE: All of this startup code assumes the low 16mb (approx.) of
1039  *       kernel mappings are done with one single contiguous chunk of
1040  *       ram.  On small ram machines (classics mainly) we only get
1041  *       around 8mb mapped for us.
1042  */
1043
1044 void __init early_pgtable_allocfail(char *type)
1045 {
1046         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1047         prom_halt();
1048 }
1049
1050 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1051 {
1052         pgd_t *pgdp;
1053         pmd_t *pmdp;
1054         pte_t *ptep;
1055
1056         while(start < end) {
1057                 pgdp = pgd_offset_k(start);
1058                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1059                         pmdp = (pmd_t *) __srmmu_get_nocache(
1060                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1061                         if (pmdp == NULL)
1062                                 early_pgtable_allocfail("pmd");
1063                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1064                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1065                 }
1066                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1067                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1068                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1069                         if (ptep == NULL)
1070                                 early_pgtable_allocfail("pte");
1071                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1072                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1073                 }
1074                 if (start > (0xffffffffUL - PMD_SIZE))
1075                         break;
1076                 start = (start + PMD_SIZE) & PMD_MASK;
1077         }
1078 }
1079
1080 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1081 {
1082         pgd_t *pgdp;
1083         pmd_t *pmdp;
1084         pte_t *ptep;
1085
1086         while(start < end) {
1087                 pgdp = pgd_offset_k(start);
1088                 if(srmmu_pgd_none(*pgdp)) {
1089                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1090                         if (pmdp == NULL)
1091                                 early_pgtable_allocfail("pmd");
1092                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1093                         srmmu_pgd_set(pgdp, pmdp);
1094                 }
1095                 pmdp = srmmu_pmd_offset(pgdp, start);
1096                 if(srmmu_pmd_none(*pmdp)) {
1097                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1098                                                              PTE_SIZE);
1099                         if (ptep == NULL)
1100                                 early_pgtable_allocfail("pte");
1101                         memset(ptep, 0, PTE_SIZE);
1102                         srmmu_pmd_set(pmdp, ptep);
1103                 }
1104                 if (start > (0xffffffffUL - PMD_SIZE))
1105                         break;
1106                 start = (start + PMD_SIZE) & PMD_MASK;
1107         }
1108 }
1109
1110 /*
1111  * This is much cleaner than poking around physical address space
1112  * looking at the prom's page table directly which is what most
1113  * other OS's do.  Yuck... this is much better.
1114  */
1115 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)
1116 {
1117         pgd_t *pgdp;
1118         pmd_t *pmdp;
1119         pte_t *ptep;
1120         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1121         unsigned long prompte;
1122
1123         while(start <= end) {
1124                 if (start == 0)
1125                         break; /* probably wrap around */
1126                 if(start == 0xfef00000)
1127                         start = KADB_DEBUGGER_BEGVM;
1128                 if(!(prompte = srmmu_hwprobe(start))) {
1129                         start += PAGE_SIZE;
1130                         continue;
1131                 }
1132
1133                 /* A red snapper, see what it really is. */
1134                 what = 0;
1135
1136                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1137                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1138                                 what = 1;
1139                 }
1140
1141                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1142                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1143                            prompte)
1144                                 what = 2;
1145                 }
1146
1147                 pgdp = pgd_offset_k(start);
1148                 if(what == 2) {
1149                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1150                         start += SRMMU_PGDIR_SIZE;
1151                         continue;
1152                 }
1153                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1154                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1155                         if (pmdp == NULL)
1156                                 early_pgtable_allocfail("pmd");
1157                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1158                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1159                 }
1160                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1161                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1162                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1163                                                              PTE_SIZE);
1164                         if (ptep == NULL)
1165                                 early_pgtable_allocfail("pte");
1166                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1167                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1168                 }
1169                 if(what == 1) {
1170                         /*
1171                          * We bend the rule where all 16 PTPs in a pmd_t point
1172                          * inside the same PTE page, and we leak a perfectly
1173                          * good hardware PTE piece. Alternatives seem worse.
1174                          */
1175                         unsigned int x; /* Index of HW PMD in soft cluster */
1176                         x = (start >> PMD_SHIFT) & 15;
1177                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1178                         start += SRMMU_REAL_PMD_SIZE;
1179                         continue;
1180                 }
1181                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1182                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1183                 start += PAGE_SIZE;
1184         }
1185 }
1186
1187 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1188
1189 /* Create a third-level SRMMU 16MB page mapping. */
1190 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1191 {
1192         pgd_t *pgdp = pgd_offset_k(vaddr);
1193         unsigned long big_pte;
1194
1195         big_pte = KERNEL_PTE(phys_base >> 4);
1196         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1197 }
1198
1199 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1200 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1201 {
1202         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1203         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1204         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1205         /* Map "low" memory only */
1206         const unsigned long min_vaddr = PAGE_OFFSET;
1207         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1208
1209         if (vstart < min_vaddr || vstart >= max_vaddr)
1210                 return vstart;
1211
1212         if (vend > max_vaddr || vend < min_vaddr)
1213                 vend = max_vaddr;
1214
1215         while(vstart < vend) {
1216                 do_large_mapping(vstart, pstart);
1217                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1218         }
1219         return vstart;
1220 }
1221
1222 static inline void memprobe_error(char *msg)
1223 {
1224         prom_printf(msg);
1225         prom_printf("Halting now...\n");
1226         prom_halt();
1227 }
1228
1229 static inline void map_kernel(void)
1230 {
1231         int i;
1232
1233         if (phys_base > 0) {
1234                 do_large_mapping(PAGE_OFFSET, phys_base);
1235         }
1236
1237         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1238                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1239         }
1240
1241         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1242 }
1243
1244 /* Paging initialization on the Sparc Reference MMU. */
1245 extern void sparc_context_init(int);
1246
1247 void (*poke_srmmu)(void) __initdata = NULL;
1248
1249 extern unsigned long bootmem_init(unsigned long *pages_avail);
1250
1251 void __init srmmu_paging_init(void)
1252 {
1253         int i, cpunode;
1254         char node_str[128];
1255         pgd_t *pgd;
1256         pmd_t *pmd;
1257         pte_t *pte;
1258         unsigned long pages_avail;
1259
1260         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1261
1262         if (sparc_cpu_model == sun4d)
1263                 num_contexts = 65536; /* We know it is Viking */
1264         else {
1265                 /* Find the number of contexts on the srmmu. */
1266                 cpunode = prom_getchild(prom_root_node);
1267                 num_contexts = 0;
1268                 while(cpunode != 0) {
1269                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1270                         if(!strcmp(node_str, "cpu")) {
1271                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1272                                 break;
1273                         }
1274                         cpunode = prom_getsibling(cpunode);
1275                 }
1276         }
1277
1278         if(!num_contexts) {
1279                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1280                 prom_halt();
1281         }
1282
1283         pages_avail = 0;
1284         last_valid_pfn = bootmem_init(&pages_avail);
1285
1286         srmmu_nocache_calcsize();
1287         srmmu_nocache_init();
1288         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1289         map_kernel();
1290
1291         /* ctx table has to be physically aligned to its size */
1292         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1293         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1294
1295         for(i = 0; i < num_contexts; i++)
1296                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1297
1298         flush_cache_all();
1299         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1300 #ifdef CONFIG_SMP
1301         /* Stop from hanging here... */
1302         local_flush_tlb_all();
1303 #else
1304         flush_tlb_all();
1305 #endif
1306         poke_srmmu();
1307
1308 #ifdef CONFIG_SUN_IO
1309         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1310         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1311 #endif
1312
1313         srmmu_allocate_ptable_skeleton(
1314                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1315         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1316
1317         pgd = pgd_offset_k(PKMAP_BASE);
1318         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1319         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1320         pkmap_page_table = pte;
1321
1322         flush_cache_all();
1323         flush_tlb_all();
1324
1325         sparc_context_init(num_contexts);
1326
1327         kmap_init();
1328
1329         {
1330                 unsigned long zones_size[MAX_NR_ZONES];
1331                 unsigned long zholes_size[MAX_NR_ZONES];
1332                 unsigned long npages;
1333                 int znum;
1334
1335                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1336                         zones_size[znum] = zholes_size[znum] = 0;
1337
1338                 npages = max_low_pfn - pfn_base;
1339
1340                 zones_size[ZONE_DMA] = npages;
1341                 zholes_size[ZONE_DMA] = npages - pages_avail;
1342
1343                 npages = highend_pfn - max_low_pfn;
1344                 zones_size[ZONE_HIGHMEM] = npages;
1345                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1346
1347                 free_area_init_node(0, &contig_page_data, zones_size,
1348                                     pfn_base, zholes_size);
1349         }
1350 }
1351
1352 static void srmmu_mmu_info(struct seq_file *m)
1353 {
1354         seq_printf(m,
1355                    "MMU type\t: %s\n"
1356                    "contexts\t: %d\n"
1357                    "nocache total\t: %ld\n"
1358                    "nocache used\t: %d\n",
1359                    srmmu_name,
1360                    num_contexts,
1361                    srmmu_nocache_size,
1362                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1363 }
1364
1365 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1366 {
1367 }
1368
1369 static void srmmu_destroy_context(struct mm_struct *mm)
1370 {
1371
1372         if(mm->context != NO_CONTEXT) {
1373                 flush_cache_mm(mm);
1374                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1375                 flush_tlb_mm(mm);
1376                 spin_lock(&srmmu_context_spinlock);
1377                 free_context(mm->context);
1378                 spin_unlock(&srmmu_context_spinlock);
1379                 mm->context = NO_CONTEXT;
1380         }
1381 }
1382
1383 /* Init various srmmu chip types. */
1384 static void __init srmmu_is_bad(void)
1385 {
1386         prom_printf("Could not determine SRMMU chip type.\n");
1387         prom_halt();
1388 }
1389
1390 static void __init init_vac_layout(void)
1391 {
1392         int nd, cache_lines;
1393         char node_str[128];
1394 #ifdef CONFIG_SMP
1395         int cpu = 0;
1396         unsigned long max_size = 0;
1397         unsigned long min_line_size = 0x10000000;
1398 #endif
1399
1400         nd = prom_getchild(prom_root_node);
1401         while((nd = prom_getsibling(nd)) != 0) {
1402                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1403                 if(!strcmp(node_str, "cpu")) {
1404                         vac_line_size = prom_getint(nd, "cache-line-size");
1405                         if (vac_line_size == -1) {
1406                                 prom_printf("can't determine cache-line-size, "
1407                                             "halting.\n");
1408                                 prom_halt();
1409                         }
1410                         cache_lines = prom_getint(nd, "cache-nlines");
1411                         if (cache_lines == -1) {
1412                                 prom_printf("can't determine cache-nlines, halting.\n");
1413                                 prom_halt();
1414                         }
1415
1416                         vac_cache_size = cache_lines * vac_line_size;
1417 #ifdef CONFIG_SMP
1418                         if(vac_cache_size > max_size)
1419                                 max_size = vac_cache_size;
1420                         if(vac_line_size < min_line_size)
1421                                 min_line_size = vac_line_size;
1422                         //FIXME: cpus not contiguous!!
1423                         cpu++;
1424                         if (cpu >= NR_CPUS || !cpu_online(cpu))
1425                                 break;
1426 #else
1427                         break;
1428 #endif
1429                 }
1430         }
1431         if(nd == 0) {
1432                 prom_printf("No CPU nodes found, halting.\n");
1433                 prom_halt();
1434         }
1435 #ifdef CONFIG_SMP
1436         vac_cache_size = max_size;
1437         vac_line_size = min_line_size;
1438 #endif
1439         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1440                (int)vac_cache_size, (int)vac_line_size);
1441 }
1442
1443 static void __init poke_hypersparc(void)
1444 {
1445         volatile unsigned long clear;
1446         unsigned long mreg = srmmu_get_mmureg();
1447
1448         hyper_flush_unconditional_combined();
1449
1450         mreg &= ~(HYPERSPARC_CWENABLE);
1451         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1452         mreg |= (HYPERSPARC_CMODE);
1453
1454         srmmu_set_mmureg(mreg);
1455
1456 #if 0 /* XXX I think this is bad news... -DaveM */
1457         hyper_clear_all_tags();
1458 #endif
1459
1460         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1461         hyper_flush_whole_icache();
1462         clear = srmmu_get_faddr();
1463         clear = srmmu_get_fstatus();
1464 }
1465
1466 static void __init init_hypersparc(void)
1467 {
1468         srmmu_name = "ROSS HyperSparc";
1469         srmmu_modtype = HyperSparc;
1470
1471         init_vac_layout();
1472
1473         is_hypersparc = 1;
1474
1475         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1476         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1477         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1478         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1479         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1480         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1481         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1482
1483         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1484         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1485         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1486         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1487
1488         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1489         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1490         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1491
1492
1493         poke_srmmu = poke_hypersparc;
1494
1495         hypersparc_setup_blockops();
1496 }
1497
1498 static void __init poke_cypress(void)
1499 {
1500         unsigned long mreg = srmmu_get_mmureg();
1501         unsigned long faddr, tagval;
1502         volatile unsigned long cypress_sucks;
1503         volatile unsigned long clear;
1504
1505         clear = srmmu_get_faddr();
1506         clear = srmmu_get_fstatus();
1507
1508         if (!(mreg & CYPRESS_CENABLE)) {
1509                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1510                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1511                                              "sta %%g0, [%0] %2\n\t" : :
1512                                              "r" (faddr), "r" (0x40000),
1513                                              "i" (ASI_M_DATAC_TAG));
1514                 }
1515         } else {
1516                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1517                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1518                                              "=r" (tagval) :
1519                                              "r" (faddr), "r" (0x40000),
1520                                              "i" (ASI_M_DATAC_TAG));
1521
1522                         /* If modified and valid, kick it. */
1523                         if((tagval & 0x60) == 0x60)
1524                                 cypress_sucks = *(unsigned long *)
1525                                                         (0xf0020000 + faddr);
1526                 }
1527         }
1528
1529         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1530         clear = srmmu_get_faddr();
1531         clear = srmmu_get_fstatus();
1532
1533         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1534         srmmu_set_mmureg(mreg);
1535 }
1536
1537 static void __init init_cypress_common(void)
1538 {
1539         init_vac_layout();
1540
1541         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1542         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1543         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1544         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1545         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1546         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1547         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1548
1549         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1550         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1551         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1552         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1553
1554
1555         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1556         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1557         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1558
1559         poke_srmmu = poke_cypress;
1560 }
1561
1562 static void __init init_cypress_604(void)
1563 {
1564         srmmu_name = "ROSS Cypress-604(UP)";
1565         srmmu_modtype = Cypress;
1566         init_cypress_common();
1567 }
1568
1569 static void __init init_cypress_605(unsigned long mrev)
1570 {
1571         srmmu_name = "ROSS Cypress-605(MP)";
1572         if(mrev == 0xe) {
1573                 srmmu_modtype = Cypress_vE;
1574                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1575         } else {
1576                 if(mrev == 0xd) {
1577                         srmmu_modtype = Cypress_vD;
1578                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1579                 } else {
1580                         srmmu_modtype = Cypress;
1581                 }
1582         }
1583         init_cypress_common();
1584 }
1585
1586 static void __init poke_swift(void)
1587 {
1588         unsigned long mreg;
1589
1590         /* Clear any crap from the cache or else... */
1591         swift_flush_cache_all();
1592
1593         /* Enable I & D caches */
1594         mreg = srmmu_get_mmureg();
1595         mreg |= (SWIFT_IE | SWIFT_DE);
1596         /*
1597          * The Swift branch folding logic is completely broken.  At
1598          * trap time, if things are just right, if can mistakenly
1599          * think that a trap is coming from kernel mode when in fact
1600          * it is coming from user mode (it mis-executes the branch in
1601          * the trap code).  So you see things like crashme completely
1602          * hosing your machine which is completely unacceptable.  Turn
1603          * this shit off... nice job Fujitsu.
1604          */
1605         mreg &= ~(SWIFT_BF);
1606         srmmu_set_mmureg(mreg);
1607 }
1608
1609 #define SWIFT_MASKID_ADDR  0x10003018
1610 static void __init init_swift(void)
1611 {
1612         unsigned long swift_rev;
1613
1614         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1615                              "srl %0, 0x18, %0\n\t" :
1616                              "=r" (swift_rev) :
1617                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1618         srmmu_name = "Fujitsu Swift";
1619         switch(swift_rev) {
1620         case 0x11:
1621         case 0x20:
1622         case 0x23:
1623         case 0x30:
1624                 srmmu_modtype = Swift_lots_o_bugs;
1625                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1626                 /*
1627                  * Gee george, I wonder why Sun is so hush hush about
1628                  * this hardware bug... really braindamage stuff going
1629                  * on here.  However I think we can find a way to avoid
1630                  * all of the workaround overhead under Linux.  Basically,
1631                  * any page fault can cause kernel pages to become user
1632                  * accessible (the mmu gets confused and clears some of
1633                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1634                  * horrible eh?  But wait, after extensive testing it appears
1635                  * that if you use pgd_t level large kernel pte's (like the
1636                  * 4MB pages on the Pentium) the bug does not get tripped
1637                  * at all.  This avoids almost all of the major overhead.
1638                  * Welcome to a world where your vendor tells you to,
1639                  * "apply this kernel patch" instead of "sorry for the
1640                  * broken hardware, send it back and we'll give you
1641                  * properly functioning parts"
1642                  */
1643                 break;
1644         case 0x25:
1645         case 0x31:
1646                 srmmu_modtype = Swift_bad_c;
1647                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1648                 /*
1649                  * You see Sun allude to this hardware bug but never
1650                  * admit things directly, they'll say things like,
1651                  * "the Swift chip cache problems" or similar.
1652                  */
1653                 break;
1654         default:
1655                 srmmu_modtype = Swift_ok;
1656                 break;
1657         };
1658
1659         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1660         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1661         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1662         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1663
1664
1665         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1666         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1667         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1668         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1669
1670         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1671         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1672         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1673
1674         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1675
1676         flush_page_for_dma_global = 0;
1677
1678         /*
1679          * Are you now convinced that the Swift is one of the
1680          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1681          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1682          * you examined the microcode of the Swift you'd find
1683          * XXX's all over the place.
1684          */
1685         poke_srmmu = poke_swift;
1686 }
1687
1688 static void turbosparc_flush_cache_all(void)
1689 {
1690         flush_user_windows();
1691         turbosparc_idflash_clear();
1692 }
1693
1694 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1695 {
1696         FLUSH_BEGIN(mm)
1697         flush_user_windows();
1698         turbosparc_idflash_clear();
1699         FLUSH_END
1700 }
1701
1702 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1703 {
1704         FLUSH_BEGIN(vma->vm_mm)
1705         flush_user_windows();
1706         turbosparc_idflash_clear();
1707         FLUSH_END
1708 }
1709
1710 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1711 {
1712         FLUSH_BEGIN(vma->vm_mm)
1713         flush_user_windows();
1714         if (vma->vm_flags & VM_EXEC)
1715                 turbosparc_flush_icache();
1716         turbosparc_flush_dcache();
1717         FLUSH_END
1718 }
1719
1720 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1721 static void turbosparc_flush_page_to_ram(unsigned long page)
1722 {
1723 #ifdef TURBOSPARC_WRITEBACK
1724         volatile unsigned long clear;
1725
1726         if (srmmu_hwprobe(page))
1727                 turbosparc_flush_page_cache(page);
1728         clear = srmmu_get_fstatus();
1729 #endif
1730 }
1731
1732 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1733 {
1734 }
1735
1736 static void turbosparc_flush_page_for_dma(unsigned long page)
1737 {
1738         turbosparc_flush_dcache();
1739 }
1740
1741 static void turbosparc_flush_tlb_all(void)
1742 {
1743         srmmu_flush_whole_tlb();
1744 }
1745
1746 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1747 {
1748         FLUSH_BEGIN(mm)
1749         srmmu_flush_whole_tlb();
1750         FLUSH_END
1751 }
1752
1753 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1754 {
1755         FLUSH_BEGIN(vma->vm_mm)
1756         srmmu_flush_whole_tlb();
1757         FLUSH_END
1758 }
1759
1760 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1761 {
1762         FLUSH_BEGIN(vma->vm_mm)
1763         srmmu_flush_whole_tlb();
1764         FLUSH_END
1765 }
1766
1767
1768 static void __init poke_turbosparc(void)
1769 {
1770         unsigned long mreg = srmmu_get_mmureg();
1771         unsigned long ccreg;
1772
1773         /* Clear any crap from the cache or else... */
1774         turbosparc_flush_cache_all();
1775         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1776         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1777         srmmu_set_mmureg(mreg);
1778
1779         ccreg = turbosparc_get_ccreg();
1780
1781 #ifdef TURBOSPARC_WRITEBACK
1782         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1783         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1784                         /* Write-back D-cache, emulate VLSI
1785                          * abortion number three, not number one */
1786 #else
1787         /* For now let's play safe, optimize later */
1788         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1789                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1790         ccreg &= ~(TURBOSPARC_uS2);
1791                         /* Emulate VLSI abortion number three, not number one */
1792 #endif
1793
1794         switch (ccreg & 7) {
1795         case 0: /* No SE cache */
1796         case 7: /* Test mode */
1797                 break;
1798         default:
1799                 ccreg |= (TURBOSPARC_SCENABLE);
1800         }
1801         turbosparc_set_ccreg (ccreg);
1802
1803         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1804         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1805         srmmu_set_mmureg(mreg);
1806 }
1807
1808 static void __init init_turbosparc(void)
1809 {
1810         srmmu_name = "Fujitsu TurboSparc";
1811         srmmu_modtype = TurboSparc;
1812
1813         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1814         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1815         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1816         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1817
1818         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1819         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1820         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1821         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1822
1823         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1824
1825         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1826         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1827
1828         poke_srmmu = poke_turbosparc;
1829 }
1830
1831 static void __init poke_tsunami(void)
1832 {
1833         unsigned long mreg = srmmu_get_mmureg();
1834
1835         tsunami_flush_icache();
1836         tsunami_flush_dcache();
1837         mreg &= ~TSUNAMI_ITD;
1838         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1839         srmmu_set_mmureg(mreg);
1840 }
1841
1842 static void __init init_tsunami(void)
1843 {
1844         /*
1845          * Tsunami's pretty sane, Sun and TI actually got it
1846          * somewhat right this time.  Fujitsu should have
1847          * taken some lessons from them.
1848          */
1849
1850         srmmu_name = "TI Tsunami";
1851         srmmu_modtype = Tsunami;
1852
1853         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1854         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1855         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1856         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1857
1858
1859         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1860         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1861         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1862         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1863
1864         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1865         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1866         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1867
1868         poke_srmmu = poke_tsunami;
1869
1870         tsunami_setup_blockops();
1871 }
1872
1873 static void __init poke_viking(void)
1874 {
1875         unsigned long mreg = srmmu_get_mmureg();
1876         static int smp_catch;
1877
1878         if(viking_mxcc_present) {
1879                 unsigned long mxcc_control = mxcc_get_creg();
1880
1881                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1882                 mxcc_control &= ~(MXCC_CTL_RRC);
1883                 mxcc_set_creg(mxcc_control);
1884
1885                 /*
1886                  * We don't need memory parity checks.
1887                  * XXX This is a mess, have to dig out later. ecd.
1888                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1889                  */
1890
1891                 /* We do cache ptables on MXCC. */
1892                 mreg |= VIKING_TCENABLE;
1893         } else {
1894                 unsigned long bpreg;
1895
1896                 mreg &= ~(VIKING_TCENABLE);
1897                 if(smp_catch++) {
1898                         /* Must disable mixed-cmd mode here for other cpu's. */
1899                         bpreg = viking_get_bpreg();
1900                         bpreg &= ~(VIKING_ACTION_MIX);
1901                         viking_set_bpreg(bpreg);
1902
1903                         /* Just in case PROM does something funny. */
1904                         msi_set_sync();
1905                 }
1906         }
1907
1908         mreg |= VIKING_SPENABLE;
1909         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1910         mreg |= VIKING_SBENABLE;
1911         mreg &= ~(VIKING_ACENABLE);
1912         srmmu_set_mmureg(mreg);
1913
1914 #ifdef CONFIG_SMP
1915         /* Avoid unnecessary cross calls. */
1916         BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
1917         BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
1918         BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
1919         BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
1920         BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
1921         BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
1922         BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
1923         btfixup();
1924 #endif
1925 }
1926
1927 static void __init init_viking(void)
1928 {
1929         unsigned long mreg = srmmu_get_mmureg();
1930
1931         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1932         if(mreg & VIKING_MMODE) {
1933                 srmmu_name = "TI Viking";
1934                 viking_mxcc_present = 0;
1935                 msi_set_sync();
1936
1937                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1938                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1939                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1940
1941                 /*
1942                  * We need this to make sure old viking takes no hits
1943                  * on it's cache for dma snoops to workaround the
1944                  * "load from non-cacheable memory" interrupt bug.
1945                  * This is only necessary because of the new way in
1946                  * which we use the IOMMU.
1947                  */
1948                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1949
1950                 flush_page_for_dma_global = 0;
1951         } else {
1952                 srmmu_name = "TI Viking/MXCC";
1953                 viking_mxcc_present = 1;
1954
1955                 srmmu_cache_pagetables = 1;
1956
1957                 /* MXCC vikings lack the DMA snooping bug. */
1958                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1959         }
1960
1961         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1962         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1963         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1964         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1965
1966 #ifdef CONFIG_SMP
1967         if (sparc_cpu_model == sun4d) {
1968                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1969                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1970                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1971                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1972         } else
1973 #endif
1974         {
1975                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1976                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1977                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1978                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1979         }
1980
1981         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1982         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1983
1984         poke_srmmu = poke_viking;
1985 }
1986
1987 /* Probe for the srmmu chip version. */
1988 static void __init get_srmmu_type(void)
1989 {
1990         unsigned long mreg, psr;
1991         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1992
1993         srmmu_modtype = SRMMU_INVAL_MOD;
1994         hwbug_bitmask = 0;
1995
1996         mreg = srmmu_get_mmureg(); psr = get_psr();
1997         mod_typ = (mreg & 0xf0000000) >> 28;
1998         mod_rev = (mreg & 0x0f000000) >> 24;
1999         psr_typ = (psr >> 28) & 0xf;
2000         psr_vers = (psr >> 24) & 0xf;
2001
2002         /* First, check for HyperSparc or Cypress. */
2003         if(mod_typ == 1) {
2004                 switch(mod_rev) {
2005                 case 7:
2006                         /* UP or MP Hypersparc */
2007                         init_hypersparc();
2008                         break;
2009                 case 0:
2010                 case 2:
2011                         /* Uniprocessor Cypress */
2012                         init_cypress_604();
2013                         break;
2014                 case 10:
2015                 case 11:
2016                 case 12:
2017                         /* _REALLY OLD_ Cypress MP chips... */
2018                 case 13:
2019                 case 14:
2020                 case 15:
2021                         /* MP Cypress mmu/cache-controller */
2022                         init_cypress_605(mod_rev);
2023                         break;
2024                 default:
2025                         /* Some other Cypress revision, assume a 605. */
2026                         init_cypress_605(mod_rev);
2027                         break;
2028                 };
2029                 return;
2030         }
2031
2032         /*
2033          * Now Fujitsu TurboSparc. It might happen that it is
2034          * in Swift emulation mode, so we will check later...
2035          */
2036         if (psr_typ == 0 && psr_vers == 5) {
2037                 init_turbosparc();
2038                 return;
2039         }
2040
2041         /* Next check for Fujitsu Swift. */
2042         if(psr_typ == 0 && psr_vers == 4) {
2043                 int cpunode;
2044                 char node_str[128];
2045
2046                 /* Look if it is not a TurboSparc emulating Swift... */
2047                 cpunode = prom_getchild(prom_root_node);
2048                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2049                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2050                         if(!strcmp(node_str, "cpu")) {
2051                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2052                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2053                                         init_turbosparc();
2054                                         return;
2055                                 }
2056                                 break;
2057                         }
2058                 }
2059
2060                 init_swift();
2061                 return;
2062         }
2063
2064         /* Now the Viking family of srmmu. */
2065         if(psr_typ == 4 &&
2066            ((psr_vers == 0) ||
2067             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2068                 init_viking();
2069                 return;
2070         }
2071
2072         /* Finally the Tsunami. */
2073         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2074                 init_tsunami();
2075                 return;
2076         }
2077
2078         /* Oh well */
2079         srmmu_is_bad();
2080 }
2081
2082 /* don't laugh, static pagetables */
2083 static void srmmu_check_pgt_cache(int low, int high)
2084 {
2085 }
2086
2087 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2088         tsetup_mmu_patchme, rtrap_mmu_patchme;
2089
2090 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2091         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2092
2093 extern unsigned long srmmu_fault;
2094
2095 #define PATCH_BRANCH(insn, dest) do { \
2096                 iaddr = &(insn); \
2097                 daddr = &(dest); \
2098                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2099         } while(0)
2100
2101 static void __init patch_window_trap_handlers(void)
2102 {
2103         unsigned long *iaddr, *daddr;
2104
2105         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2106         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2107         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2108         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2109         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2110         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2111         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2112 }
2113
2114 #ifdef CONFIG_SMP
2115 /* Local cross-calls. */
2116 static void smp_flush_page_for_dma(unsigned long page)
2117 {
2118         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2119         local_flush_page_for_dma(page);
2120 }
2121
2122 #endif
2123
2124 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2125 {
2126         return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2127 }
2128
2129 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2130 {
2131         return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2132 }
2133
2134 static pgprot_t srmmu_pgprot_noncached(pgprot_t prot)
2135 {
2136         prot &= ~__pgprot(SRMMU_CACHE);
2137
2138         return prot;
2139 }
2140
2141 /* Load up routines and constants for sun4m and sun4d mmu */
2142 void __init ld_mmu_srmmu(void)
2143 {
2144         extern void ld_mmu_iommu(void);
2145         extern void ld_mmu_iounit(void);
2146         extern void ___xchg32_sun4md(void);
2147
2148         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2149         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2150         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2151
2152         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2153         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2154
2155         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2156         PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
2157         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2158         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2159         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2160         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2161
2162         /* Functions */
2163         BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM);
2164 #ifndef CONFIG_SMP
2165         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2166 #endif
2167         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2168
2169         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2170         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2171
2172         BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2173         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2174         BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
2175
2176         BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2177
2178         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2179         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2180
2181         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2182         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2183         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2184
2185         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2186         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2187         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2188         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2189
2190         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2191         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2192         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2193         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2194         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2195         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2196
2197         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2198         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2199         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2200
2201         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2202         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2203         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2204         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2205         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2206         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2207         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2208         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2209
2210         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2211         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2212         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2213         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2214         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2215         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2216         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2217         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2218         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2219         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2220         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2221         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2222
2223         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2224         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2225
2226         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2227         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2228         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2229
2230         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2231
2232         BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2233         BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2234
2235         BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2236         BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2237
2238         get_srmmu_type();
2239         patch_window_trap_handlers();
2240
2241 #ifdef CONFIG_SMP
2242         /* El switcheroo... */
2243
2244         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2245         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2246         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2247         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2248         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2249         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2250         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2251         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2252         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2253         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2254         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2255
2256         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2257         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2258         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2259         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2260         if (sparc_cpu_model != sun4d) {
2261                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2262                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2263                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2264                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2265         }
2266         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2267         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2268         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2269 #endif
2270
2271         if (sparc_cpu_model == sun4d)
2272                 ld_mmu_iounit();
2273         else
2274                 ld_mmu_iommu();
2275 #ifdef CONFIG_SMP
2276         if (sparc_cpu_model == sun4d)
2277                 sun4d_init_smp();
2278         else
2279                 sun4m_init_smp();
2280 #endif
2281 }