arch/sparc/kernel/sun4m_irq.c

   1 /*  sun4m_irq.c
   2  *  arch/sparc/kernel/sun4m_irq.c:
   3  *
   4  *  djhr: Hacked out of irq.c into a CPU dependent version.
   5  *
   6  *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8  *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
   9  *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/linkage.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/sched.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/smp.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/slab.h>
  21 #include <linux/init.h>
  22 #include <linux/ioport.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/system.h>
  29 #include <asm/psr.h>
  30 #include <asm/vaddrs.h>
  31 #include <asm/timer.h>
  32 #include <asm/openprom.h>
  33 #include <asm/oplib.h>
  34 #include <asm/traps.h>
  35 #include <asm/pgalloc.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/smp.h>
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40 #include <asm/cacheflush.h>
  41
  42 #include "irq.h"
  43
  44 struct sun4m_irq_percpu {
  45         u32             pending;
  46         u32             clear;
  47         u32             set;
  48 };
  49
  50 struct sun4m_irq_global {
  51         u32             pending;
  52         u32             mask;
  53         u32             mask_clear;
  54         u32             mask_set;
  55         u32             interrupt_target;
  56 };
  57
  58 /* Code in entry.S needs to get at these register mappings.  */
  59 struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
  60 struct sun4m_irq_global __iomem *sun4m_irq_global;
  61
  62 /* Dave Redman (djhr@tadpole.co.uk)
  63  * The sun4m interrupt registers.
  64  */
  65 #define SUN4M_INT_ENABLE        0x80000000
  66 #define SUN4M_INT_E14           0x00000080
  67 #define SUN4M_INT_E10           0x00080000
  68
  69 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
  70 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
  71
  72 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
  73 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
  74 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
  75 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
  76 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
  77 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
  78 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
  79 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
  80 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
  81 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
  82 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
  83 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
  84 #define SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
  85 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
  86
  87 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
  88 #define SUN4M_INT_VME(x)        (1 << (x))
  89
  90 /* These tables only apply for interrupts greater than 15..
  91  *
  92  * any intr value below 0x10 is considered to be a soft-int
  93  * this may be useful or it may not.. but that's how I've done it.
  94  * and it won't clash with what OBP is telling us about devices.
  95  *
  96  * take an encoded intr value and lookup if it's valid
  97  * then get the mask bits that match from irq_mask
  98  *
  99  * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
 100  */
 101 static unsigned char irq_xlate[32] = {
 102     /*  0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  a,  b,  c,  d,  e,  f */
 103         0,  0,  0,  0,  1,  0,  2,  0,  3,  0,  4,  5,  6, 14,  0,  7,
 104         0,  0,  8,  9,  0, 10,  0, 11,  0, 12,  0, 13,  0, 14,  0,  0
 105 };
 106
 107 static unsigned long irq_mask[] = {
 108         0,                                                /* illegal index */
 109         SUN4M_INT_SCSI,                                   /*  1 irq 4 */
 110         SUN4M_INT_ETHERNET,                               /*  2 irq 6 */
 111         SUN4M_INT_VIDEO,                                  /*  3 irq 8 */
 112         SUN4M_INT_REALTIME,                               /*  4 irq 10 */
 113         SUN4M_INT_FLOPPY,                                 /*  5 irq 11 */
 114         (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),             /*  6 irq 12 */
 115         SUN4M_INT_MODULE_ERR,                             /*  7 irq 15 */
 116         SUN4M_INT_SBUS(0),                                /*  8 irq 2 */
 117         SUN4M_INT_SBUS(1),                                /*  9 irq 3 */
 118         SUN4M_INT_SBUS(2),                                /* 10 irq 5 */
 119         SUN4M_INT_SBUS(3),                                /* 11 irq 7 */
 120         SUN4M_INT_SBUS(4),                                /* 12 irq 9 */
 121         SUN4M_INT_SBUS(5),                                /* 13 irq 11 */
 122         SUN4M_INT_SBUS(6)                                 /* 14 irq 13 */
 123 };
 124
 125 static unsigned long sun4m_get_irqmask(unsigned int irq)
 126 {
 127         unsigned long mask;
 128
 129         if (irq > 0x20) {
 130                 /* OBIO/SBUS interrupts */
 131                 irq &= 0x1f;
 132                 mask = irq_mask[irq_xlate[irq]];
 133                 if (!mask)
 134                         printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
 135         } else {
 136                 /* Soft Interrupts will come here.
 137                  * Currently there is no way to trigger them but I'm sure
 138                  * something could be cooked up.
 139                  */
 140                 irq &= 0xf;
 141                 mask = SUN4M_SOFT_INT(irq);
 142         }
 143         return mask;
 144 }
 145
 146 static void sun4m_disable_irq(unsigned int irq_nr)
 147 {
 148         unsigned long mask, flags;
 149         int cpu = smp_processor_id();
 150
 151         mask = sun4m_get_irqmask(irq_nr);
 152         local_irq_save(flags);
 153         if (irq_nr > 15)
 154                 sbus_writel(mask, &sun4m_irq_global->mask_set);
 155         else
 156                 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
 157         local_irq_restore(flags);
 158 }
 159
 160 static void sun4m_enable_irq(unsigned int irq_nr)
 161 {
 162         unsigned long mask, flags;
 163         int cpu = smp_processor_id();
 164
 165         /* Dreadful floppy hack. When we use 0x2b instead of
 166          * 0x0b the system blows (it starts to whistle!).
 167          * So we continue to use 0x0b. Fixme ASAP. --P3
 168          */
 169         if (irq_nr != 0x0b) {
 170                 mask = sun4m_get_irqmask(irq_nr);
 171                 local_irq_save(flags);
 172                 if (irq_nr > 15)
 173                         sbus_writel(mask, &sun4m_irq_global->mask_clear);
 174                 else
 175                         sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
 176                 local_irq_restore(flags);
 177         } else {
 178                 local_irq_save(flags);
 179                 sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
 180                 local_irq_restore(flags);
 181         }
 182 }
 183
 184 static unsigned long cpu_pil_to_imask[16] = {
 185 /*0*/   0x00000000,
 186 /*1*/   0x00000000,
 187 /*2*/   SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
 188 /*3*/   SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
 189 /*4*/   SUN4M_INT_SCSI,
 190 /*5*/   SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
 191 /*6*/   SUN4M_INT_ETHERNET,
 192 /*7*/   SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
 193 /*8*/   SUN4M_INT_VIDEO,
 194 /*9*/   SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
 195 /*10*/  SUN4M_INT_REALTIME,
 196 /*11*/  SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
 197 /*12*/  SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
 198 /*13*/  SUN4M_INT_AUDIO,
 199 /*14*/  SUN4M_INT_E14,
 200 /*15*/  0x00000000
 201 };
 202
 203 /* We assume the caller has disabled local interrupts when these are called,
 204  * or else very bizarre behavior will result.
 205  */
 206 static void sun4m_disable_pil_irq(unsigned int pil)
 207 {
 208         sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
 209 }
 210
 211 static void sun4m_enable_pil_irq(unsigned int pil)
 212 {
 213         sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
 214 }
 215
 216 #ifdef CONFIG_SMP
 217 static void sun4m_send_ipi(int cpu, int level)
 218 {
 219         unsigned long mask = sun4m_get_irqmask(level);
 220         sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
 221 }
 222
 223 static void sun4m_clear_ipi(int cpu, int level)
 224 {
 225         unsigned long mask = sun4m_get_irqmask(level);
 226         sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
 227 }
 228
 229 static void sun4m_set_udt(int cpu)
 230 {
 231         sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
 232 }
 233 #endif
 234
 235 struct sun4m_timer_percpu {
 236         u32             l14_limit;
 237         u32             l14_count;
 238         u32             l14_limit_noclear;
 239         u32             user_timer_start_stop;
 240 };
 241
 242 static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
 243
 244 struct sun4m_timer_global {
 245         u32             l10_limit;
 246         u32             l10_count;
 247         u32             l10_limit_noclear;
 248         u32             reserved;
 249         u32             timer_config;
 250 };
 251
 252 static struct sun4m_timer_global __iomem *timers_global;
 253
 254 #define OBIO_INTR       0x20
 255 #define TIMER_IRQ       (OBIO_INTR | 10)
 256
 257 unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
 258
 259 static void sun4m_clear_clock_irq(void)
 260 {
 261         sbus_readl(&timers_global->l10_limit);
 262 }
 263
 264 /* Exported for sun4m_smp.c */
 265 void sun4m_clear_profile_irq(int cpu)
 266 {
 267         sbus_readl(&timers_percpu[cpu]->l14_limit);
 268 }
 269
 270 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
 271 {
 272         sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
 273 }
 274
 275 static void __init sun4m_init_timers(irq_handler_t counter_fn)
 276 {
 277         struct device_node *dp = of_find_node_by_name(NULL, "counter");
 278         int i, err, len, num_cpu_timers;
 279         const u32 *addr;
 280
 281         if (!dp) {
 282                 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
 283                 return;
 284         }
 285
 286         addr = of_get_property(dp, "address", &len);
 287         if (!addr) {
 288                 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
 289                 return;
 290         }
 291
 292         num_cpu_timers = (len / sizeof(u32)) - 1;
 293         for (i = 0; i < num_cpu_timers; i++) {
 294                 timers_percpu[i] = (void __iomem *)
 295                         (unsigned long) addr[i];
 296         }
 297         timers_global = (void __iomem *)
 298                 (unsigned long) addr[num_cpu_timers];
 299
 300         sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
 301
 302         master_l10_counter = &timers_global->l10_count;
 303
 304         err = request_irq(TIMER_IRQ, counter_fn,
 305                           (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
 306         if (err) {
 307                 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
 308                         err);
 309                 return;
 310         }
 311
 312         for (i = 0; i < num_cpu_timers; i++)
 313                 sbus_writel(0, &timers_percpu[i]->l14_limit);
 314         if (num_cpu_timers == 4)
 315                 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
 316
 317 #ifdef CONFIG_SMP
 318         {
 319                 unsigned long flags;
 320                 extern unsigned long lvl14_save[4];
 321                 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
 322
 323                 /* For SMP we use the level 14 ticker, however the bootup code
 324                  * has copied the firmware's level 14 vector into the boot cpu's
 325                  * trap table, we must fix this now or we get squashed.
 326                  */
 327                 local_irq_save(flags);
 328                 trap_table->inst_one = lvl14_save[0];
 329                 trap_table->inst_two = lvl14_save[1];
 330                 trap_table->inst_three = lvl14_save[2];
 331                 trap_table->inst_four = lvl14_save[3];
 332                 local_flush_cache_all();
 333                 local_irq_restore(flags);
 334         }
 335 #endif
 336 }
 337
 338 void __init sun4m_init_IRQ(void)
 339 {
 340         struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
 341         int len, i, mid, num_cpu_iregs;
 342         const u32 *addr;
 343
 344         if (!dp) {
 345                 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
 346                 return;
 347         }
 348
 349         addr = of_get_property(dp, "address", &len);
 350         if (!addr) {
 351                 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
 352                 return;
 353         }
 354
 355         num_cpu_iregs = (len / sizeof(u32)) - 1;
 356         for (i = 0; i < num_cpu_iregs; i++) {
 357                 sun4m_irq_percpu[i] = (void __iomem *)
 358                         (unsigned long) addr[i];
 359         }
 360         sun4m_irq_global = (void __iomem *)
 361                 (unsigned long) addr[num_cpu_iregs];
 362
 363         local_irq_disable();
 364
 365         sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
 366         for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
 367                 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
 368
 369         if (num_cpu_iregs == 4)
 370                 sbus_writel(0, &sun4m_irq_global->interrupt_target);
 371
 372         BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
 373         BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
 374         BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
 375         BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
 376         BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
 377         BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
 378         sparc_init_timers = sun4m_init_timers;
 379 #ifdef CONFIG_SMP
 380         BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
 381         BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
 382         BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
 383 #endif
 384
 385         /* Cannot enable interrupts until OBP ticker is disabled. */
 386 }