1 #ifndef __SPARC64_SYSTEM_H
2 #define __SPARC64_SYSTEM_H
4 #include <asm/ptrace.h>
5 #include <asm/processor.h>
6 #include <asm/visasm.h>
10 #include <linux/irqflags.h>
11 #include <asm-generic/cmpxchg-local.h>
14 * Sparc (general) CPU types
22 sun4u = 0x05, /* V8 ploos ploos */
24 ap1000 = 0x07, /* almost a sun4m */
27 #define sparc_cpu_model sun4u
29 /* This cannot ever be a sun4c :) That's just history. */
32 extern char reboot_command[];
34 /* These are here in an effort to more fully work around Spitfire Errata
35 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
36 * branch, the chip can stop executing instructions until a trap occurs.
37 * Therefore, if interrupts are disabled, the chip can hang forever.
39 * It used to be believed that the memory barrier had to be right in the
40 * delay slot, but a case has been traced recently wherein the memory barrier
41 * was one instruction after the branch delay slot and the chip still hung.
42 * The offending sequence was the following in sym_wakeup_done() of the
45 * call sym_ccb_from_dsa, 0
51 * The branch has to be mispredicted for the bug to occur. Therefore, we put
52 * the memory barrier explicitly into a "branch always, predicted taken"
53 * delay slot to avoid the problem case.
55 #define membar_safe(type) \
56 do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
57 " membar " type "\n" \
63 membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
65 membar_safe("#LoadLoad")
67 membar_safe("#StoreStore")
68 #define membar_storeload() \
69 membar_safe("#StoreLoad")
70 #define membar_storeload_storestore() \
71 membar_safe("#StoreLoad | #StoreStore")
72 #define membar_storeload_loadload() \
73 membar_safe("#StoreLoad | #LoadLoad")
74 #define membar_storestore_loadstore() \
75 membar_safe("#StoreStore | #LoadStore")
79 #define nop() __asm__ __volatile__ ("nop")
81 #define read_barrier_depends() do { } while(0)
82 #define set_mb(__var, __value) \
83 do { __var = __value; membar_storeload_storestore(); } while(0)
87 #define smp_rmb() rmb()
88 #define smp_wmb() wmb()
89 #define smp_read_barrier_depends() read_barrier_depends()
91 #define smp_mb() __asm__ __volatile__("":::"memory")
92 #define smp_rmb() __asm__ __volatile__("":::"memory")
93 #define smp_wmb() __asm__ __volatile__("":::"memory")
94 #define smp_read_barrier_depends() do { } while(0)
97 #define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
99 #define flushw_all() __asm__ __volatile__("flushw")
101 /* Performance counter register access. */
102 #define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
103 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
104 #define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
106 /* Blackbird errata workaround. See commentary in
107 * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
108 * for more information.
110 #define reset_pic() \
111 __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
113 "99:wr %g0, 0x0, %pic\n\t" \
118 extern void sun_do_break(void);
119 extern int stop_a_enabled;
121 extern void fault_in_user_windows(void);
122 extern void synchronize_user_stack(void);
124 extern void __flushw_user(void);
125 #define flushw_user() __flushw_user()
127 #define flush_user_windows flushw_user
128 #define flush_register_windows flushw_all
130 /* Don't hold the runqueue lock over context switch */
131 #define __ARCH_WANT_UNLOCKED_CTXSW
132 #define prepare_arch_switch(next) \
137 /* See what happens when you design the chip correctly?
139 * We tell gcc we clobber all non-fixed-usage registers except
140 * for l0/l1. It will use one for 'next' and the other to hold
141 * the output value of 'last'. 'next' is not referenced again
142 * past the invocation of switch_to in the scheduler, so we need
143 * not preserve it's value. Hairy, but it lets us remove 2 loads
144 * and 2 stores in this critical code path. -DaveM
146 #define switch_to(prev, next, last) \
147 do { if (test_thread_flag(TIF_PERFCTR)) { \
148 unsigned long __tmp; \
150 current_thread_info()->pcr_reg = __tmp; \
152 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
153 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
155 flush_tlb_pending(); \
156 save_and_clear_fpu(); \
157 /* If you are tempted to conditionalize the following */ \
158 /* so that ASI is only written if it changes, think again. */ \
159 __asm__ __volatile__("wr %%g0, %0, %%asi" \
160 : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
161 trap_block[current_thread_info()->cpu].thread = \
162 task_thread_info(next); \
163 __asm__ __volatile__( \
164 "mov %%g4, %%g7\n\t" \
165 "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
166 "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
167 "rdpr %%wstate, %%o5\n\t" \
168 "stx %%o6, [%%g6 + %6]\n\t" \
169 "stb %%o5, [%%g6 + %5]\n\t" \
170 "rdpr %%cwp, %%o5\n\t" \
171 "stb %%o5, [%%g6 + %8]\n\t" \
173 "ldub [%4 + %8], %%g1\n\t" \
174 "wrpr %%g1, %%cwp\n\t" \
175 "ldx [%%g6 + %6], %%o6\n\t" \
176 "ldub [%%g6 + %5], %%o5\n\t" \
177 "ldub [%%g6 + %7], %%o7\n\t" \
178 "wrpr %%o5, 0x0, %%wstate\n\t" \
179 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
180 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
181 "ldx [%%g6 + %9], %%g4\n\t" \
182 "brz,pt %%o7, switch_to_pc\n\t" \
183 " mov %%g7, %0\n\t" \
184 "sethi %%hi(ret_from_syscall), %%g1\n\t" \
185 "jmpl %%g1 + %%lo(ret_from_syscall), %%g0\n\t" \
187 ".globl switch_to_pc\n\t" \
188 "switch_to_pc:\n\t" \
189 : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
190 "=r" (__local_per_cpu_offset) \
191 : "0" (task_thread_info(next)), \
192 "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
193 "i" (TI_CWP), "i" (TI_TASK) \
195 "g1", "g2", "g3", "g7", \
196 "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
197 "i0", "i1", "i2", "i3", "i4", "i5", \
198 "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
199 /* If you fuck with this, update ret_from_syscall code too. */ \
200 if (test_thread_flag(TIF_PERFCTR)) { \
201 write_pcr(current_thread_info()->pcr_reg); \
206 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
208 unsigned long tmp1, tmp2;
210 __asm__ __volatile__(
211 " membar #StoreLoad | #LoadLoad\n"
214 " cas [%4], %2, %0\n"
216 " bne,a,pn %%icc, 1b\n"
218 " membar #StoreLoad | #StoreStore\n"
219 : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
225 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
227 unsigned long tmp1, tmp2;
229 __asm__ __volatile__(
230 " membar #StoreLoad | #LoadLoad\n"
233 " casx [%4], %2, %0\n"
235 " bne,a,pn %%xcc, 1b\n"
237 " membar #StoreLoad | #StoreStore\n"
238 : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
244 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
246 extern void __xchg_called_with_bad_pointer(void);
248 static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
253 return xchg32(ptr, x);
255 return xchg64(ptr, x);
257 __xchg_called_with_bad_pointer();
261 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
264 * Atomic compare and exchange. Compare OLD with MEM, if identical,
265 * store NEW in MEM. Return the initial value in MEM. Success is
266 * indicated by comparing RETURN with OLD.
269 #define __HAVE_ARCH_CMPXCHG 1
271 static inline unsigned long
272 __cmpxchg_u32(volatile int *m, int old, int new)
274 __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
275 "cas [%2], %3, %0\n\t"
276 "membar #StoreLoad | #StoreStore"
278 : "0" (new), "r" (m), "r" (old)
284 static inline unsigned long
285 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
287 __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
288 "casx [%2], %3, %0\n\t"
289 "membar #StoreLoad | #StoreStore"
291 : "0" (new), "r" (m), "r" (old)
297 /* This function doesn't exist, so you'll get a linker error
298 if something tries to do an invalid cmpxchg(). */
299 extern void __cmpxchg_called_with_bad_pointer(void);
301 static inline unsigned long
302 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
306 return __cmpxchg_u32(ptr, old, new);
308 return __cmpxchg_u64(ptr, old, new);
310 __cmpxchg_called_with_bad_pointer();
314 #define cmpxchg(ptr,o,n) \
316 __typeof__(*(ptr)) _o_ = (o); \
317 __typeof__(*(ptr)) _n_ = (n); \
318 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
319 (unsigned long)_n_, sizeof(*(ptr))); \
323 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
327 static inline unsigned long __cmpxchg_local(volatile void *ptr,
329 unsigned long new, int size)
333 case 8: return __cmpxchg(ptr, old, new, size);
335 return __cmpxchg_local_generic(ptr, old, new, size);
341 #define cmpxchg_local(ptr, o, n) \
342 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
343 (unsigned long)(n), sizeof(*(ptr))))
344 #define cmpxchg64_local(ptr, o, n) \
346 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
347 cmpxchg_local((ptr), (o), (n)); \
350 #endif /* !(__ASSEMBLY__) */
352 #define arch_align_stack(x) (x)
354 #endif /* !(__SPARC64_SYSTEM_H) */