1 #ifndef __SPARC_SYSTEM_H
2 #define __SPARC_SYSTEM_H
4 #include <linux/kernel.h>
5 #include <linux/threads.h> /* NR_CPUS */
6 #include <linux/thread_info.h>
10 #include <asm/ptrace.h>
11 #include <asm/btfixup.h>
16 #include <linux/irqflags.h>
19 * Sparc (general) CPU types
27 sun4u = 0x05, /* V8 ploos ploos */
29 ap1000 = 0x07, /* almost a sun4m */
32 /* Really, userland should not be looking at any of this... */
35 extern enum sparc_cpu sparc_cpu_model;
37 #define ARCH_SUN4C (sparc_cpu_model==sun4c)
39 #define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
41 extern char reboot_command[];
43 extern struct thread_info *current_set[NR_CPUS];
45 extern unsigned long empty_bad_page;
46 extern unsigned long empty_bad_page_table;
47 extern unsigned long empty_zero_page;
49 extern void sun_do_break(void);
50 extern int serial_console;
51 extern int stop_a_enabled;
53 static inline int con_is_present(void)
55 return serial_console ? 0 : 1;
58 /* When a context switch happens we must flush all user windows so that
59 * the windows of the current process are flushed onto its stack. This
60 * way the windows are all clean for the next process and the stack
61 * frames are up to date.
63 extern void flush_user_windows(void);
64 extern void kill_user_windows(void);
65 extern void synchronize_user_stack(void);
66 extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
67 void *fpqueue, unsigned long *fpqdepth);
70 #define SWITCH_ENTER(prv) \
72 if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
73 put_psr(get_psr() | PSR_EF); \
74 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
75 &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
76 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
77 (prv)->thread.kregs->psr &= ~PSR_EF; \
81 #define SWITCH_DO_LAZY_FPU(next) /* */
83 #define SWITCH_ENTER(prv) /* */
84 #define SWITCH_DO_LAZY_FPU(nxt) \
86 if (last_task_used_math != (nxt)) \
87 (nxt)->thread.kregs->psr&=~PSR_EF; \
91 extern void flushw_all(void);
94 * Flush windows so that the VM switch which follows
95 * would not pull the stack from under us.
97 * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
98 * XXX WTF is the above comment? Found in late teen 2.4.x.
100 #define prepare_arch_switch(next) do { \
101 __asm__ __volatile__( \
102 ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
103 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
104 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
105 "save %sp, -0x40, %sp\n\t" \
106 "restore; restore; restore; restore; restore; restore; restore"); \
109 /* Much care has gone into this code, do not touch it.
111 * We need to loadup regs l0/l1 for the newly forked child
112 * case because the trap return path relies on those registers
113 * holding certain values, gcc is told that they are clobbered.
114 * Gcc needs registers for 3 values in and 1 value out, so we
115 * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
117 * Hey Dave, that do not touch sign is too much of an incentive
120 #define switch_to(prev, next, last) do { \
121 SWITCH_ENTER(prev); \
122 SWITCH_DO_LAZY_FPU(next); \
123 cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
124 __asm__ __volatile__( \
125 "sethi %%hi(here - 0x8), %%o7\n\t" \
126 "mov %%g6, %%g3\n\t" \
127 "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
128 "rd %%psr, %%g4\n\t" \
129 "std %%sp, [%%g6 + %4]\n\t" \
130 "rd %%wim, %%g5\n\t" \
131 "wr %%g4, 0x20, %%psr\n\t" \
133 "std %%g4, [%%g6 + %3]\n\t" \
134 "ldd [%2 + %3], %%g4\n\t" \
136 ".globl patchme_store_new_current\n" \
137 "patchme_store_new_current:\n\t" \
139 "wr %%g4, 0x20, %%psr\n\t" \
142 "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
143 "ldd [%%g6 + %4], %%sp\n\t" \
144 "wr %%g5, 0x0, %%wim\n\t" \
145 "ldd [%%sp + 0x00], %%l0\n\t" \
146 "ldd [%%sp + 0x38], %%i6\n\t" \
147 "wr %%g4, 0x0, %%psr\n\t" \
150 "jmpl %%o7 + 0x8, %%g0\n\t" \
151 " ld [%%g3 + %5], %0\n\t" \
154 : "r" (&(current_set[hard_smp_processor_id()])), \
155 "r" (task_thread_info(next)), \
159 : "g1", "g2", "g3", "g4", "g5", "g7", \
160 "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
161 "i0", "i1", "i2", "i3", "i4", "i5", \
162 "o0", "o1", "o2", "o3", "o7"); \
165 /* XXX Change this if we ever use a PSO mode kernel. */
166 #define mb() __asm__ __volatile__ ("" : : : "memory")
169 #define read_barrier_depends() do { } while(0)
170 #define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
171 #define smp_mb() __asm__ __volatile__("":::"memory")
172 #define smp_rmb() __asm__ __volatile__("":::"memory")
173 #define smp_wmb() __asm__ __volatile__("":::"memory")
174 #define smp_read_barrier_depends() do { } while(0)
176 #define nop() __asm__ __volatile__ ("nop")
178 /* This has special calling conventions */
180 BTFIXUPDEF_CALL(void, ___xchg32, void)
183 static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
186 __asm__ __volatile__("swap [%2], %0"
192 register unsigned long *ptr asm("g1");
193 register unsigned long ret asm("g2");
195 ptr = (unsigned long *) m;
198 /* Note: this is magic and the nop there is
200 __asm__ __volatile__(
202 "call ___f____xchg32\n\t"
205 : "0" (ret), "r" (ptr)
206 : "g3", "g4", "g7", "memory", "cc");
212 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
214 extern void __xchg_called_with_bad_pointer(void);
216 static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
220 return xchg_u32(ptr, x);
222 __xchg_called_with_bad_pointer();
226 /* Emulate cmpxchg() the same way we emulate atomics,
227 * by hashing the object address and indexing into an array
228 * of spinlocks to get a bit of performance...
230 * See arch/sparc/lib/atomic32.c for implementation.
232 * Cribbed from <asm-parisc/atomic.h>
234 #define __HAVE_ARCH_CMPXCHG 1
236 /* bug catcher for when unsupported size is used - won't link */
237 extern void __cmpxchg_called_with_bad_pointer(void);
238 /* we only need to support cmpxchg of a u32 on sparc */
239 extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
241 /* don't worry...optimizer will get rid of most of this */
242 static inline unsigned long
243 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
247 return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
249 __cmpxchg_called_with_bad_pointer();
255 #define cmpxchg(ptr, o, n) \
257 __typeof__(*(ptr)) _o_ = (o); \
258 __typeof__(*(ptr)) _n_ = (n); \
259 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
260 (unsigned long)_n_, sizeof(*(ptr))); \
263 #include <asm-generic/cmpxchg-local.h>
266 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
269 #define cmpxchg_local(ptr, o, n) \
270 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
271 (unsigned long)(n), sizeof(*(ptr))))
272 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
274 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
276 #endif /* __KERNEL__ */
278 #endif /* __ASSEMBLY__ */
280 #define arch_align_stack(x) (x)
282 #endif /* !(__SPARC_SYSTEM_H) */