4 * Copyright (C) 2006 - 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <asm/mmzone.h>
18 static struct resource usbf_resources[] = {
23 .flags = IORESOURCE_MEM,
28 .flags = IORESOURCE_IRQ,
32 static struct platform_device usbf_device = {
37 .coherent_dma_mask = 0xffffffff,
39 .num_resources = ARRAY_SIZE(usbf_resources),
40 .resource = usbf_resources,
43 static struct resource iic_resources[] = {
48 .flags = IORESOURCE_MEM,
53 .flags = IORESOURCE_IRQ,
57 static struct platform_device iic_device = {
58 .name = "i2c-sh_mobile",
59 .num_resources = ARRAY_SIZE(iic_resources),
60 .resource = iic_resources,
63 static struct uio_info vpu_platform_data = {
69 static struct resource vpu_resources[] = {
74 .flags = IORESOURCE_MEM,
77 /* place holder for contiguous memory */
81 static struct platform_device vpu_device = {
82 .name = "uio_pdrv_genirq",
85 .platform_data = &vpu_platform_data,
87 .resource = vpu_resources,
88 .num_resources = ARRAY_SIZE(vpu_resources),
91 static struct uio_info veu_platform_data = {
97 static struct resource veu_resources[] = {
102 .flags = IORESOURCE_MEM,
105 /* place holder for contiguous memory */
109 static struct platform_device veu_device = {
110 .name = "uio_pdrv_genirq",
113 .platform_data = &veu_platform_data,
115 .resource = veu_resources,
116 .num_resources = ARRAY_SIZE(veu_resources),
119 static struct plat_sci_port sci_platform_data[] = {
121 .mapbase = 0xffe00000,
122 .flags = UPF_BOOT_AUTOCONF,
124 .irqs = { 80, 80, 80, 80 },
127 .mapbase = 0xffe10000,
128 .flags = UPF_BOOT_AUTOCONF,
130 .irqs = { 81, 81, 81, 81 },
133 .mapbase = 0xffe20000,
134 .flags = UPF_BOOT_AUTOCONF,
136 .irqs = { 82, 82, 82, 82 },
143 static struct platform_device sci_device = {
147 .platform_data = sci_platform_data,
151 static struct platform_device *sh7722_devices[] __initdata = {
159 static int __init sh7722_devices_setup(void)
161 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
162 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
163 return platform_add_devices(sh7722_devices,
164 ARRAY_SIZE(sh7722_devices));
166 __initcall(sh7722_devices_setup);
171 /* interrupt sources */
172 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
174 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
175 RTC_ATI, RTC_PRI, RTC_CUI,
176 DMAC0, DMAC1, DMAC2, DMAC3,
177 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
179 USB_USBI0, USB_USBI1,
180 DMAC4, DMAC5, DMAC_DADERR,
182 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
183 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
184 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
185 SDHI0, SDHI1, SDHI2, SDHI3,
186 CMT, TSIF, SIU, TWODG,
190 /* interrupt groups */
192 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
195 static struct intc_vect vectors[] __initdata = {
196 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
197 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
198 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
199 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
200 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
201 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
202 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
203 INTC_VECT(RTC_CUI, 0x7c0),
204 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
205 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
206 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
207 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
208 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
209 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
210 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
211 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
212 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
213 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
214 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
215 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
216 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
217 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
218 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
219 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
220 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
221 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
222 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
223 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
224 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
225 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
228 static struct intc_group groups[] __initdata = {
229 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
230 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
231 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
232 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
233 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
234 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
235 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
236 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
237 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
238 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
241 static struct intc_mask_reg mask_registers[] __initdata = {
242 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
244 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
245 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
246 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
248 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
249 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
250 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
251 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
252 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
253 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
254 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
255 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
256 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
257 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
258 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
259 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
260 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
261 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
262 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
263 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
265 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
266 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
267 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
268 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
271 static struct intc_prio_reg prio_registers[] __initdata = {
272 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
273 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
274 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
275 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
276 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
277 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
278 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
279 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
280 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
281 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
282 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
283 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
284 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
285 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
288 static struct intc_sense_reg sense_registers[] __initdata = {
289 { 0xa414001c, 16, 2, /* ICR1 */
290 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
293 static struct intc_mask_reg ack_registers[] __initdata = {
294 { 0xa4140024, 0, 8, /* INTREQ00 */
295 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
298 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
299 mask_registers, prio_registers, sense_registers,
302 void __init plat_irq_setup(void)
304 register_intc_controller(&intc_desc);
307 void __init plat_mem_setup(void)
309 /* Register the URAM space as Node 1 */
310 setup_bootmem_node(1, 0x055f0000, 0x05610000);