2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
4 * SH7722 & SH7366 support for the clock framework
6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc
7 * Based on code for sh7343 by Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/stringify.h>
18 #include <asm/clock.h>
23 #define ROUND_NEAREST 0
27 static int adjust_algos[][3] = {
29 { NM, N, 1 }, /* N:1, N:1 */
30 { 3, 2, 2 }, /* 3:2:2 */
31 { 5, 2, 2 }, /* 5:2:2 */
32 { N, 1, 1 }, /* N:1:1 */
44 static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
45 int m1, int m2, int round_flag)
47 unsigned long rem, div;
50 pr_debug( "Actual values: r1 = %ld\n", r1);
51 pr_debug( "...............r2 = %ld\n", r2);
55 pr_debug( "setting equal rates: r2 now %ld\n", r2);
56 } else if ((m2 == N && m1 == 1) ||
57 (m2 == NM && m1 == N)) { /* N:1 or NM:N */
58 pr_debug( "Setting rates as 1:N (N:N*M)\n");
60 pr_debug( "...remainder = %ld\n", rem);
63 pr_debug( "...div = %ld\n", div);
66 the_one = rem >= r1/2 ? 1 : 0; break;
73 r2 = r1 * (div + the_one);
74 pr_debug( "...setting r2 to %ld\n", r2);
76 } else if ((m2 == 1 && m1 == N) ||
77 (m2 == N && m1 == NM)) { /* 1:N or N:NM */
78 pr_debug( "Setting rates as N:1 (N*M:N)\n");
80 pr_debug( "...remainder = %ld\n", rem);
83 pr_debug( "...div = %ld\n", div);
86 the_one = rem > r2/2 ? 1 : 0; break;
93 r2 = r1 / (div + the_one);
94 pr_debug( "...setting r2 to %ld\n", r2);
96 } else { /* value:value */
97 pr_debug( "Setting rates as %d:%d\n", m1, m2);
100 pr_debug( "...div = %ld\n", div);
101 pr_debug( "...setting r2 to %ld\n", r2);
107 static void adjust_clocks(int originate, int *l, unsigned long v[],
112 pr_debug( "Go down from %d...\n", originate);
113 /* go up recalculation clocks */
114 for (x = originate; x>0; x -- )
115 v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
119 pr_debug( "Go up from %d...\n", originate);
120 /* go down recalculation clocks */
121 for (x = originate; x<n_in_line - 1; x ++ )
122 v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
129 * SH7722 uses a common set of multipliers and divisors, so this
134 * Instead of having two separate multipliers/divisors set, like this:
136 * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
137 * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
139 * I created the divisors2 array, which is used to calculate rate like
140 * rate = parent * 2 / divisors2[ divisor ];
142 static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
144 static void master_clk_recalc(struct clk *clk)
146 unsigned frqcr = ctrl_inl(FRQCR);
148 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
151 static void master_clk_init(struct clk *clk)
154 clk->flags |= CLK_RATE_PROPAGATES;
155 clk->rate = CONFIG_SH_PCLK_FREQ;
156 master_clk_recalc(clk);
160 static void module_clk_recalc(struct clk *clk)
162 unsigned long frqcr = ctrl_inl(FRQCR);
164 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
167 static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
169 int div = rate / clk->rate;
170 int master_divs[] = { 2, 3, 4, 6, 8, 16 };
174 for (index = 1; index < ARRAY_SIZE(master_divs); index++)
175 if (div >= master_divs[index - 1] && div < master_divs[index])
178 if (index >= ARRAY_SIZE(master_divs))
179 index = ARRAY_SIZE(master_divs);
180 div = master_divs[index - 1];
182 frqcr = ctrl_inl(FRQCR);
183 frqcr &= ~(0xF << 24);
184 frqcr |= ( (div-1) << 24);
185 ctrl_outl(frqcr, FRQCR);
190 static struct clk_ops sh7722_master_clk_ops = {
191 .init = master_clk_init,
192 .recalc = master_clk_recalc,
193 .set_rate = master_clk_setrate,
196 static struct clk_ops sh7722_module_clk_ops = {
197 .recalc = module_clk_recalc,
200 struct frqcr_context {
205 struct frqcr_context sh7722_get_clk_context(const char *name)
207 struct frqcr_context ctx = { 0, };
209 if (!strcmp(name, "peripheral_clk")) {
212 } else if (!strcmp(name, "sdram_clk")) {
215 } else if (!strcmp(name, "bus_clk")) {
218 } else if (!strcmp(name, "sh_clk")) {
221 } else if (!strcmp(name, "umem_clk")) {
224 } else if (!strcmp(name, "cpu_clk")) {
232 * sh7722_find_divisors - find divisor for setting rate
234 * All sh7722 clocks use the same set of multipliers/divisors. This function
235 * chooses correct divisor to set the rate of clock with parent clock that
236 * generates frequency of 'parent_rate'
238 * @parent_rate: rate of parent clock
239 * @rate: requested rate to be set
241 static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate)
243 unsigned div2 = parent_rate * 2 / rate;
246 if (rate > parent_rate)
249 for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
250 if (div2 > divisors2[index] && div2 <= divisors2[index])
253 if (index >= ARRAY_SIZE(divisors2))
254 index = ARRAY_SIZE(divisors2) - 1;
255 return divisors2[index];
258 static void sh7722_frqcr_recalc(struct clk *clk)
260 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
261 unsigned long frqcr = ctrl_inl(FRQCR);
264 index = (frqcr >> ctx.shift) & ctx.mask;
265 clk->rate = clk->parent->rate * 2 / divisors2[index];
268 static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
271 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
272 unsigned long parent_rate = clk->parent->rate;
278 if (parent_rate < rate)
281 /* look for multiplier/divisor pair */
282 div = sh7722_find_divisors(parent_rate, rate);
286 /* calculate new value of clock rate */
287 clk->rate = parent_rate * 2 / div;
288 frqcr = ctrl_inl(FRQCR);
290 /* FIXME: adjust as algo_id specifies */
291 if (algo_id != NO_CHANGE) {
293 char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
294 char *algo_group_2[] = { "sh_clk", "bus_clk" };
295 char *algo_group_3[] = { "sh_clk", "sdram_clk" };
296 char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
297 char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
298 char **algo_current = NULL;
299 /* 3 is the maximum number of clocks in relation */
301 unsigned long values[3]; /* the same comment as above */
302 int part_length = -1;
306 * all the steps below only required if adjustion was
309 if (algo_id == IUS_N1_N1 ||
310 algo_id == IUS_322 ||
311 algo_id == IUS_522 ||
312 algo_id == IUS_N11) {
313 algo_current = algo_group_1;
316 if (algo_id == SB_N1) {
317 algo_current = algo_group_2;
320 if (algo_id == SB3_N1 ||
324 algo_current = algo_group_3;
327 if (algo_id == BP_N1) {
328 algo_current = algo_group_4;
331 if (algo_id == IP_N1) {
332 algo_current = algo_group_5;
336 goto incorrect_algo_id;
339 for (i = 0; i < part_length; i ++ ) {
340 if (originator >= 0 && !strcmp(clk->name,
343 ck[i] = clk_get(NULL, algo_current[i]);
344 values[i] = clk_get_rate(ck[i]);
348 adjust_clocks(originator, adjust_algos[algo_id],
349 values, part_length);
351 for (i = 0; i < part_length; i ++ ) {
352 struct frqcr_context part_ctx;
356 part_div = sh7722_find_divisors(parent_rate,
359 part_ctx = sh7722_get_clk_context(
361 frqcr &= ~(part_ctx.mask <<
363 frqcr |= part_div << part_ctx.shift;
368 ck[i]->ops->recalc(ck[i]);
373 /* was there any error during recalculation ? If so, bail out.. */
374 if (unlikely(err!=0))
377 /* clear FRQCR bits */
378 frqcr &= ~(ctx.mask << ctx.shift);
379 frqcr |= div << ctx.shift;
381 /* ...and perform actual change */
382 ctrl_outl(frqcr, FRQCR);
391 static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
393 unsigned long parent_rate = clk->parent->rate;
396 /* look for multiplier/divisor pair */
397 div = sh7722_find_divisors(parent_rate, rate);
401 /* calculate new value of clock rate */
402 return parent_rate * 2 / div;
405 static struct clk_ops sh7722_frqcr_clk_ops = {
406 .recalc = sh7722_frqcr_recalc,
407 .set_rate = sh7722_frqcr_set_rate,
408 .round_rate = sh7722_frqcr_round_rate,
412 * clock ops methods for SIU A/B and IrDA clock
416 static int sh7722_siu_start_stop(struct clk *clk, int enable)
420 r = ctrl_inl(clk->arch_flags);
422 ctrl_outl(r & ~(1 << 8), clk->arch_flags);
424 ctrl_outl(r | (1 << 8), clk->arch_flags);
428 static void sh7722_siu_enable(struct clk *clk)
430 sh7722_siu_start_stop(clk, 1);
433 static void sh7722_siu_disable(struct clk *clk)
435 sh7722_siu_start_stop(clk, 0);
438 static void sh7722_video_enable(struct clk *clk)
442 r = ctrl_inl(VCLKCR);
443 ctrl_outl( r & ~(1<<8), VCLKCR);
446 static void sh7722_video_disable(struct clk *clk)
450 r = ctrl_inl(VCLKCR);
451 ctrl_outl( r | (1<<8), VCLKCR);
454 static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
459 r = ctrl_inl(VCLKCR);
461 r |= ((clk->parent->rate / rate - 1) & 0x3F);
462 ctrl_outl(r, VCLKCR);
466 static void sh7722_video_recalc(struct clk *clk)
470 r = ctrl_inl(VCLKCR);
471 clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
474 static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
479 r = ctrl_inl(clk->arch_flags);
480 div = sh7722_find_divisors(clk->parent->rate, rate);
483 r = (r & ~0xF) | div;
484 ctrl_outl(r, clk->arch_flags);
488 static void sh7722_siu_recalc(struct clk *clk)
492 r = ctrl_inl(clk->arch_flags);
493 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
496 static struct clk_ops sh7722_siu_clk_ops = {
497 .recalc = sh7722_siu_recalc,
498 .set_rate = sh7722_siu_set_rate,
499 .enable = sh7722_siu_enable,
500 .disable = sh7722_siu_disable,
503 static struct clk_ops sh7722_video_clk_ops = {
504 .recalc = sh7722_video_recalc,
505 .set_rate = sh7722_video_set_rate,
506 .enable = sh7722_video_enable,
507 .disable = sh7722_video_disable,
510 * and at last, clock definitions themselves
512 static struct clk sh7722_umem_clock = {
514 .ops = &sh7722_frqcr_clk_ops,
517 static struct clk sh7722_sh_clock = {
519 .ops = &sh7722_frqcr_clk_ops,
522 static struct clk sh7722_peripheral_clock = {
523 .name = "peripheral_clk",
524 .ops = &sh7722_frqcr_clk_ops,
527 static struct clk sh7722_sdram_clock = {
529 .ops = &sh7722_frqcr_clk_ops,
533 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
534 * methods of clk_ops determine which register they should access by
535 * examining clk->name field
537 static struct clk sh7722_siu_a_clock = {
539 .arch_flags = SCLKACR,
540 .ops = &sh7722_siu_clk_ops,
543 static struct clk sh7722_siu_b_clock = {
545 .arch_flags = SCLKBCR,
546 .ops = &sh7722_siu_clk_ops,
549 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
550 static struct clk sh7722_irda_clock = {
552 .arch_flags = IrDACLKCR,
553 .ops = &sh7722_siu_clk_ops,
557 static struct clk sh7722_video_clock = {
559 .ops = &sh7722_video_clk_ops,
562 static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg,
565 unsigned long bit = clk->arch_flags;
579 static void sh7722_mstpcr0_enable(struct clk *clk)
581 sh7722_mstpcr_start_stop(clk, MSTPCR0, 1);
584 static void sh7722_mstpcr0_disable(struct clk *clk)
586 sh7722_mstpcr_start_stop(clk, MSTPCR0, 0);
589 static void sh7722_mstpcr1_enable(struct clk *clk)
591 sh7722_mstpcr_start_stop(clk, MSTPCR1, 1);
594 static void sh7722_mstpcr1_disable(struct clk *clk)
596 sh7722_mstpcr_start_stop(clk, MSTPCR1, 0);
599 static void sh7722_mstpcr2_enable(struct clk *clk)
601 sh7722_mstpcr_start_stop(clk, MSTPCR2, 1);
604 static void sh7722_mstpcr2_disable(struct clk *clk)
606 sh7722_mstpcr_start_stop(clk, MSTPCR2, 0);
609 static struct clk_ops sh7722_mstpcr0_clk_ops = {
610 .enable = sh7722_mstpcr0_enable,
611 .disable = sh7722_mstpcr0_disable,
614 static struct clk_ops sh7722_mstpcr1_clk_ops = {
615 .enable = sh7722_mstpcr1_enable,
616 .disable = sh7722_mstpcr1_disable,
619 static struct clk_ops sh7722_mstpcr2_clk_ops = {
620 .enable = sh7722_mstpcr2_enable,
621 .disable = sh7722_mstpcr2_disable,
624 #define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \
626 .name = "mstp" __stringify(regnr) bitstr, \
627 .arch_flags = bitnr, \
628 .ops = &sh7722_mstpcr ## regnr ## _clk_ops, \
631 #define DECLARE_MSTPCR(regnr) \
632 DECLARE_MSTPCRN(regnr, 31, "31"), \
633 DECLARE_MSTPCRN(regnr, 30, "30"), \
634 DECLARE_MSTPCRN(regnr, 29, "29"), \
635 DECLARE_MSTPCRN(regnr, 28, "28"), \
636 DECLARE_MSTPCRN(regnr, 27, "27"), \
637 DECLARE_MSTPCRN(regnr, 26, "26"), \
638 DECLARE_MSTPCRN(regnr, 25, "25"), \
639 DECLARE_MSTPCRN(regnr, 24, "24"), \
640 DECLARE_MSTPCRN(regnr, 23, "23"), \
641 DECLARE_MSTPCRN(regnr, 22, "22"), \
642 DECLARE_MSTPCRN(regnr, 21, "21"), \
643 DECLARE_MSTPCRN(regnr, 20, "20"), \
644 DECLARE_MSTPCRN(regnr, 19, "19"), \
645 DECLARE_MSTPCRN(regnr, 18, "18"), \
646 DECLARE_MSTPCRN(regnr, 17, "17"), \
647 DECLARE_MSTPCRN(regnr, 16, "16"), \
648 DECLARE_MSTPCRN(regnr, 15, "15"), \
649 DECLARE_MSTPCRN(regnr, 14, "14"), \
650 DECLARE_MSTPCRN(regnr, 13, "13"), \
651 DECLARE_MSTPCRN(regnr, 12, "12"), \
652 DECLARE_MSTPCRN(regnr, 11, "11"), \
653 DECLARE_MSTPCRN(regnr, 10, "10"), \
654 DECLARE_MSTPCRN(regnr, 9, "09"), \
655 DECLARE_MSTPCRN(regnr, 8, "08"), \
656 DECLARE_MSTPCRN(regnr, 7, "07"), \
657 DECLARE_MSTPCRN(regnr, 6, "06"), \
658 DECLARE_MSTPCRN(regnr, 5, "05"), \
659 DECLARE_MSTPCRN(regnr, 4, "04"), \
660 DECLARE_MSTPCRN(regnr, 3, "03"), \
661 DECLARE_MSTPCRN(regnr, 2, "02"), \
662 DECLARE_MSTPCRN(regnr, 1, "01"), \
663 DECLARE_MSTPCRN(regnr, 0, "00")
665 static struct clk sh7722_mstpcr[] = {
671 static struct clk *sh7722_clocks[] = {
674 &sh7722_peripheral_clock,
678 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
685 * init in order: master, module, bus, cpu
687 struct clk_ops *onchip_ops[] = {
688 &sh7722_master_clk_ops,
689 &sh7722_module_clk_ops,
690 &sh7722_frqcr_clk_ops,
691 &sh7722_frqcr_clk_ops,
695 arch_init_clk_ops(struct clk_ops **ops, int type)
697 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
698 *ops = onchip_ops[type];
701 int __init arch_clk_init(void)
706 master = clk_get(NULL, "master_clk");
707 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
708 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
709 sh7722_clocks[i]->parent = master;
710 clk_register(sh7722_clocks[i]);
714 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) {
715 pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name);
716 clk_register(&sh7722_mstpcr[i]);