2 * SH7203 and SH7263 Setup
4 * Copyright (C) 2007 - 2009 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
18 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
22 USB, LCDC, CMT0, CMT1, BSC, WDT,
24 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
25 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
29 IIC30, IIC31, IIC32, IIC33,
30 SCIF0, SCIF1, SCIF2, SCIF3,
34 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
36 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
37 ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF,
40 FLCTL, SDHI3, SDHI0, SDHI1, RTC, RCAN0, RCAN1,
42 SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI,
44 /* interrupt groups */
45 PINT, ROMDEC, SDHI, SRC
48 static struct intc_vect vectors[] __initdata = {
49 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
50 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
51 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
52 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
53 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
54 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
55 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
56 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
57 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
58 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
59 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
60 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
61 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
62 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
63 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
64 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
65 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
66 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
67 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
68 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
69 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
70 INTC_IRQ(MTU0_VEF, 150),
71 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
72 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
73 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
74 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
75 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
76 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
77 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
78 INTC_IRQ(MTU2_TCI3V, 165),
79 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
80 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
81 INTC_IRQ(MTU2_TCI4V, 170),
82 INTC_IRQ(ADC_ADI, 171),
83 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
84 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
86 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
87 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
89 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
90 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
92 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
93 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
95 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
96 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
97 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
98 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
99 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
100 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
101 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
102 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
103 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
105 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
107 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
108 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
109 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
110 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
111 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
113 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
114 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
115 INTC_IRQ(RCAN0, 238),
116 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
117 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
118 INTC_IRQ(RCAN1, 243),
120 /* SH7263-specific trash */
121 #ifdef CONFIG_CPU_SUBTYPE_SH7263
122 INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219),
123 INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221),
124 INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223),
126 INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230),
128 INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245),
129 INTC_IRQ(SRC_IDEI, 246),
135 static struct intc_group groups[] __initdata = {
136 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
137 PINT4, PINT5, PINT6, PINT7),
138 #ifdef CONFIG_CPU_SUBTYPE_SH7263
139 INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,
140 ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),
141 INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),
142 INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),
146 static struct intc_prio_reg prio_registers[] __initdata = {
147 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
148 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
149 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
150 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
151 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
152 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
153 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
154 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
156 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
158 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
159 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
160 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
161 #ifdef CONFIG_CPU_SUBTYPE_SH7203
162 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
164 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
165 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
167 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
168 SSI3_SSII, ROMDEC } },
169 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
170 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
174 static struct intc_mask_reg mask_registers[] __initdata = {
175 { 0xfffe0808, 0, 16, /* PINTER */
176 { 0, 0, 0, 0, 0, 0, 0, 0,
177 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
180 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
181 mask_registers, prio_registers, NULL);
183 static struct plat_sci_port sci_platform_data[] = {
185 .mapbase = 0xfffe8000,
186 .flags = UPF_BOOT_AUTOCONF,
188 .irqs = { 192, 192, 192, 192 },
190 .mapbase = 0xfffe8800,
191 .flags = UPF_BOOT_AUTOCONF,
193 .irqs = { 196, 196, 196, 196 },
195 .mapbase = 0xfffe9000,
196 .flags = UPF_BOOT_AUTOCONF,
198 .irqs = { 200, 200, 200, 200 },
200 .mapbase = 0xfffe9800,
201 .flags = UPF_BOOT_AUTOCONF,
203 .irqs = { 204, 204, 204, 204 },
209 static struct platform_device sci_device = {
213 .platform_data = sci_platform_data,
217 static struct resource rtc_resources[] = {
220 .end = 0xffff2000 + 0x58 - 1,
221 .flags = IORESOURCE_IO,
224 /* Shared Period/Carry/Alarm IRQ */
226 .flags = IORESOURCE_IRQ,
230 static struct platform_device rtc_device = {
233 .num_resources = ARRAY_SIZE(rtc_resources),
234 .resource = rtc_resources,
237 static struct platform_device *sh7203_devices[] __initdata = {
242 static int __init sh7203_devices_setup(void)
244 return platform_add_devices(sh7203_devices,
245 ARRAY_SIZE(sh7203_devices));
247 __initcall(sh7203_devices_setup);
249 void __init plat_irq_setup(void)
251 register_intc_controller(&intc_desc);