2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
6 * Based on intc2.c and ipr.c
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
25 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
29 #define _INTC_SHIFT(h) (h & 0x1f)
30 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31 #define _INTC_FN(h) ((h >> 9) & 0xf)
32 #define _INTC_MODE(h) ((h >> 13) & 0x7)
33 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
36 struct intc_handle_int {
41 struct intc_desc_int {
47 struct intc_handle_int *prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
55 #define IS_SMP(x) x.smp
56 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
60 #define INTC_REG(d, x, c) (d->reg[(x)])
61 #define SMP_NR(d, x) 1
64 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
66 static unsigned long ack_handle[NR_IRQS];
69 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
71 struct irq_chip *chip = get_irq_chip(irq);
72 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
75 static inline unsigned int set_field(unsigned int value,
76 unsigned int field_value,
79 unsigned int width = _INTC_WIDTH(handle);
80 unsigned int shift = _INTC_SHIFT(handle);
82 value &= ~(((1 << width) - 1) << shift);
83 value |= field_value << shift;
87 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
89 ctrl_outb(set_field(0, data, h), addr);
92 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
94 ctrl_outw(set_field(0, data, h), addr);
97 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
99 ctrl_outl(set_field(0, data, h), addr);
102 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
104 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
107 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
109 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
112 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
114 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
117 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
119 static void (*intc_reg_fns[])(unsigned long addr,
121 unsigned long data) = {
122 [REG_FN_WRITE_BASE + 0] = write_8,
123 [REG_FN_WRITE_BASE + 1] = write_16,
124 [REG_FN_WRITE_BASE + 3] = write_32,
125 [REG_FN_MODIFY_BASE + 0] = modify_8,
126 [REG_FN_MODIFY_BASE + 1] = modify_16,
127 [REG_FN_MODIFY_BASE + 3] = modify_32,
130 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
131 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
132 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
133 MODE_PRIO_REG, /* Priority value written to enable interrupt */
134 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
137 static void intc_mode_field(unsigned long addr,
138 unsigned long handle,
139 void (*fn)(unsigned long,
144 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
147 static void intc_mode_zero(unsigned long addr,
148 unsigned long handle,
149 void (*fn)(unsigned long,
157 static void intc_mode_prio(unsigned long addr,
158 unsigned long handle,
159 void (*fn)(unsigned long,
164 fn(addr, handle, intc_prio_level[irq]);
167 static void (*intc_enable_fns[])(unsigned long addr,
168 unsigned long handle,
169 void (*fn)(unsigned long,
172 unsigned int irq) = {
173 [MODE_ENABLE_REG] = intc_mode_field,
174 [MODE_MASK_REG] = intc_mode_zero,
175 [MODE_DUAL_REG] = intc_mode_field,
176 [MODE_PRIO_REG] = intc_mode_prio,
177 [MODE_PCLR_REG] = intc_mode_prio,
180 static void (*intc_disable_fns[])(unsigned long addr,
181 unsigned long handle,
182 void (*fn)(unsigned long,
185 unsigned int irq) = {
186 [MODE_ENABLE_REG] = intc_mode_zero,
187 [MODE_MASK_REG] = intc_mode_field,
188 [MODE_DUAL_REG] = intc_mode_field,
189 [MODE_PRIO_REG] = intc_mode_zero,
190 [MODE_PCLR_REG] = intc_mode_field,
193 static inline void _intc_enable(unsigned int irq, unsigned long handle)
195 struct intc_desc_int *d = get_intc_desc(irq);
199 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
200 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
201 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
202 [_INTC_FN(handle)], irq);
206 static void intc_enable(unsigned int irq)
208 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
211 static void intc_disable(unsigned int irq)
213 struct intc_desc_int *d = get_intc_desc(irq);
214 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
218 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
219 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
220 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
221 [_INTC_FN(handle)], irq);
225 #ifdef CONFIG_CPU_SH3
226 static void intc_mask_ack(unsigned int irq)
228 struct intc_desc_int *d = get_intc_desc(irq);
229 unsigned long handle = ack_handle[irq];
234 /* read register and write zero only to the assocaited bit */
237 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
239 ctrl_outb(0x3f ^ set_field(0, 1, handle), addr);
244 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
250 /* this doesn't scale well, but...
252 * this function should only be used for cerain uncommon
253 * operations such as intc_set_priority() and intc_set_sense()
254 * and in those rare cases performance doesn't matter that much.
255 * keeping the memory footprint low is more important.
257 * one rather simple way to speed this up and still keep the
258 * memory footprint down is to make sure the array is sorted
259 * and then perform a bisect to lookup the irq.
262 for (i = 0; i < nr_hp; i++) {
263 if ((hp + i)->irq != irq)
272 int intc_set_priority(unsigned int irq, unsigned int prio)
274 struct intc_desc_int *d = get_intc_desc(irq);
275 struct intc_handle_int *ihp;
277 if (!intc_prio_level[irq] || prio <= 1)
280 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
282 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
285 intc_prio_level[irq] = prio;
288 * only set secondary masking method directly
289 * primary masking method is using intc_prio_level[irq]
290 * priority level will be set during next enable()
293 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
294 _intc_enable(irq, ihp->handle);
299 #define VALID(x) (x | 0x80)
301 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
302 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
303 [IRQ_TYPE_EDGE_RISING] = VALID(1),
304 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
305 /* SH7706, SH7707 and SH7709 do not support high level triggered */
306 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
307 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
308 !defined(CONFIG_CPU_SUBTYPE_SH7709)
309 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
313 static int intc_set_sense(unsigned int irq, unsigned int type)
315 struct intc_desc_int *d = get_intc_desc(irq);
316 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
317 struct intc_handle_int *ihp;
323 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
325 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
326 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
331 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
332 unsigned long address)
336 for (k = 0; k < d->nr_reg; k++) {
337 if (d->reg[k] == address)
345 static intc_enum __init intc_grp_id(struct intc_desc *desc,
348 struct intc_group *g = desc->groups;
351 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
352 g = desc->groups + i;
354 for (j = 0; g->enum_ids[j]; j++) {
355 if (g->enum_ids[j] != enum_id)
365 static unsigned int __init intc_mask_data(struct intc_desc *desc,
366 struct intc_desc_int *d,
367 intc_enum enum_id, int do_grps)
369 struct intc_mask_reg *mr = desc->mask_regs;
370 unsigned int i, j, fn, mode;
371 unsigned long reg_e, reg_d;
373 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
374 mr = desc->mask_regs + i;
376 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
377 if (mr->enum_ids[j] != enum_id)
380 if (mr->set_reg && mr->clr_reg) {
381 fn = REG_FN_WRITE_BASE;
382 mode = MODE_DUAL_REG;
386 fn = REG_FN_MODIFY_BASE;
388 mode = MODE_ENABLE_REG;
392 mode = MODE_MASK_REG;
398 fn += (mr->reg_width >> 3) - 1;
399 return _INTC_MK(fn, mode,
400 intc_get_reg(d, reg_e),
401 intc_get_reg(d, reg_d),
403 (mr->reg_width - 1) - j);
408 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
413 static unsigned int __init intc_prio_data(struct intc_desc *desc,
414 struct intc_desc_int *d,
415 intc_enum enum_id, int do_grps)
417 struct intc_prio_reg *pr = desc->prio_regs;
418 unsigned int i, j, fn, mode, bit;
419 unsigned long reg_e, reg_d;
421 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
422 pr = desc->prio_regs + i;
424 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
425 if (pr->enum_ids[j] != enum_id)
428 if (pr->set_reg && pr->clr_reg) {
429 fn = REG_FN_WRITE_BASE;
430 mode = MODE_PCLR_REG;
434 fn = REG_FN_MODIFY_BASE;
435 mode = MODE_PRIO_REG;
442 fn += (pr->reg_width >> 3) - 1;
443 bit = pr->reg_width - ((j + 1) * pr->field_width);
447 return _INTC_MK(fn, mode,
448 intc_get_reg(d, reg_e),
449 intc_get_reg(d, reg_d),
450 pr->field_width, bit);
455 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
460 #ifdef CONFIG_CPU_SH3
461 static unsigned int __init intc_ack_data(struct intc_desc *desc,
462 struct intc_desc_int *d,
465 struct intc_mask_reg *mr = desc->ack_regs;
466 unsigned int i, j, fn, mode;
467 unsigned long reg_e, reg_d;
469 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
470 mr = desc->ack_regs + i;
472 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
473 if (mr->enum_ids[j] != enum_id)
476 fn = REG_FN_MODIFY_BASE;
477 mode = MODE_ENABLE_REG;
481 fn += (mr->reg_width >> 3) - 1;
482 return _INTC_MK(fn, mode,
483 intc_get_reg(d, reg_e),
484 intc_get_reg(d, reg_d),
486 (mr->reg_width - 1) - j);
494 static unsigned int __init intc_sense_data(struct intc_desc *desc,
495 struct intc_desc_int *d,
498 struct intc_sense_reg *sr = desc->sense_regs;
499 unsigned int i, j, fn, bit;
501 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
502 sr = desc->sense_regs + i;
504 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
505 if (sr->enum_ids[j] != enum_id)
508 fn = REG_FN_MODIFY_BASE;
509 fn += (sr->reg_width >> 3) - 1;
510 bit = sr->reg_width - ((j + 1) * sr->field_width);
514 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
515 0, sr->field_width, bit);
522 static void __init intc_register_irq(struct intc_desc *desc,
523 struct intc_desc_int *d,
527 struct intc_handle_int *hp;
528 unsigned int data[2], primary;
530 /* Prefer single interrupt source bitmap over other combinations:
531 * 1. bitmap, single interrupt source
532 * 2. priority, single interrupt source
533 * 3. bitmap, multiple interrupt sources (groups)
534 * 4. priority, multiple interrupt sources (groups)
537 data[0] = intc_mask_data(desc, d, enum_id, 0);
538 data[1] = intc_prio_data(desc, d, enum_id, 0);
541 if (!data[0] && data[1])
544 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
545 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
550 BUG_ON(!data[primary]); /* must have primary masking method */
552 disable_irq_nosync(irq);
553 set_irq_chip_and_handler_name(irq, &d->chip,
554 handle_level_irq, "level");
555 set_irq_chip_data(irq, (void *)data[primary]);
557 /* set priority level
558 * - this needs to be at least 2 for 5-bit priorities on 7780
560 intc_prio_level[irq] = 2;
562 /* enable secondary masking method if present */
564 _intc_enable(irq, data[!primary]);
566 /* add irq to d->prio list if priority is available */
568 hp = d->prio + d->nr_prio;
570 hp->handle = data[1];
574 * only secondary priority should access registers, so
575 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
578 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
579 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
584 /* add irq to d->sense list if sense is available */
585 data[0] = intc_sense_data(desc, d, enum_id);
587 (d->sense + d->nr_sense)->irq = irq;
588 (d->sense + d->nr_sense)->handle = data[0];
592 /* irq should be disabled by default */
595 #ifdef CONFIG_CPU_SH3
597 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
601 static unsigned int __init save_reg(struct intc_desc_int *d,
618 void __init register_intc_controller(struct intc_desc *desc)
620 unsigned int i, k, smp;
621 struct intc_desc_int *d;
623 d = alloc_bootmem(sizeof(*d));
625 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
626 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
627 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
629 #ifdef CONFIG_CPU_SH3
630 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
632 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
634 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
638 if (desc->mask_regs) {
639 for (i = 0; i < desc->nr_mask_regs; i++) {
640 smp = IS_SMP(desc->mask_regs[i]);
641 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
642 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
646 if (desc->prio_regs) {
647 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
649 for (i = 0; i < desc->nr_prio_regs; i++) {
650 smp = IS_SMP(desc->prio_regs[i]);
651 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
652 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
656 if (desc->sense_regs) {
657 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
659 for (i = 0; i < desc->nr_sense_regs; i++) {
660 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
664 d->chip.name = desc->name;
665 d->chip.mask = intc_disable;
666 d->chip.unmask = intc_enable;
667 d->chip.mask_ack = intc_disable;
668 d->chip.set_type = intc_set_sense;
670 #ifdef CONFIG_CPU_SH3
671 if (desc->ack_regs) {
672 for (i = 0; i < desc->nr_ack_regs; i++)
673 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
675 d->chip.mask_ack = intc_mask_ack;
679 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
681 for (i = 0; i < desc->nr_vectors; i++) {
682 struct intc_vect *vect = desc->vectors + i;
684 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));