6 * read{b,w,l}/write{b,w,l} are for PCI,
7 * while in{b,w,l}/out{b,w,l} are for ISA
8 * These may (will) be platform specific function.
9 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
10 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
12 * do not have a memory barrier after them.
14 * In addition, we have
15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
16 * which are processor specific.
20 * We follow the Alpha convention here:
21 * __inb expands to an inline function call (which calls via the mv)
22 * _inb is a real function call (note ___raw fns are _ version of __raw)
23 * inb by default expands to _inb, but the machine specific code may
24 * define it to __inb if it chooses.
26 #include <asm/cache.h>
27 #include <asm/system.h>
28 #include <asm/addrspace.h>
29 #include <asm/machvec.h>
30 #include <asm/pgtable.h>
31 #include <asm-generic/iomap.h>
36 * Depending on which platform we are running on, we need different
39 #define __IO_PREFIX generic
40 #include <asm/io_generic.h>
41 #include <asm/io_trapped.h>
43 #define maybebadio(port) \
44 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
45 __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
48 * Since boards are able to define their own set of I/O routines through
49 * their respective machine vector, we always wrap through the mv.
51 * Also, in the event that a board hasn't provided its own definition for
52 * a given routine, it will be wrapped to generic code at run-time.
55 #define __inb(p) sh_mv.mv_inb((p))
56 #define __inw(p) sh_mv.mv_inw((p))
57 #define __inl(p) sh_mv.mv_inl((p))
58 #define __outb(x,p) sh_mv.mv_outb((x),(p))
59 #define __outw(x,p) sh_mv.mv_outw((x),(p))
60 #define __outl(x,p) sh_mv.mv_outl((x),(p))
62 #define __inb_p(p) sh_mv.mv_inb_p((p))
63 #define __inw_p(p) sh_mv.mv_inw_p((p))
64 #define __inl_p(p) sh_mv.mv_inl_p((p))
65 #define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
66 #define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
67 #define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
69 #define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
70 #define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
71 #define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
72 #define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
73 #define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
74 #define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
76 #define __readb(a) sh_mv.mv_readb((a))
77 #define __readw(a) sh_mv.mv_readw((a))
78 #define __readl(a) sh_mv.mv_readl((a))
79 #define __writeb(v,a) sh_mv.mv_writeb((v),(a))
80 #define __writew(v,a) sh_mv.mv_writew((v),(a))
81 #define __writel(v,a) sh_mv.mv_writel((v),(a))
93 #define outb_p __outb_p
94 #define outw_p __outw_p
95 #define outl_p __outl_p
100 #define outsb __outsb
101 #define outsw __outsw
102 #define outsl __outsl
104 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
105 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
106 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
108 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
109 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
110 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
112 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
113 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
116 * The platform header files may define some of these macros to use
117 * the inlined versions where appropriate. These macros may also be
118 * redefined by userlevel programs.
120 #define readb(a) ({ unsigned int r_ = __readb(a); mb(); r_; })
121 #define readw(a) ({ unsigned int r_ = __readw(a); mb(); r_; })
122 #define readl(a) ({ unsigned int r_ = __readl(a); mb(); r_; })
124 #define writeb(v,a) ({ __writeb((v),(a)); mb(); })
125 #define writew(v,a) ({ __writew((v),(a)); mb(); })
126 #define writel(v,a) ({ __writel((v),(a)); mb(); })
128 #define __BUILD_MEMORY_STRING(bwlq, type) \
130 static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
131 const void *addr, unsigned int count) \
133 const volatile type *__addr = addr; \
136 __raw_write##bwlq(*__addr, mem); \
141 static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
142 void *addr, unsigned int count) \
144 volatile type *__addr = addr; \
147 *__addr = __raw_read##bwlq(mem); \
152 __BUILD_MEMORY_STRING(b, u8)
153 __BUILD_MEMORY_STRING(w, u16)
155 #define writesb __raw_writesb
156 #define writesw __raw_writesw
157 #define writesl __raw_writesl
159 #define readsb __raw_readsb
160 #define readsw __raw_readsw
161 #define readsl __raw_readsl
163 #define readb_relaxed(a) readb(a)
164 #define readw_relaxed(a) readw(a)
165 #define readl_relaxed(a) readl(a)
168 #define ioread8(a) __raw_readb(a)
169 #define ioread16(a) __raw_readw(a)
170 #define ioread16be(a) be16_to_cpu(__raw_readw((a)))
171 #define ioread32(a) __raw_readl(a)
172 #define ioread32be(a) be32_to_cpu(__raw_readl((a)))
174 #define iowrite8(v,a) __raw_writeb((v),(a))
175 #define iowrite16(v,a) __raw_writew((v),(a))
176 #define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
177 #define iowrite32(v,a) __raw_writel((v),(a))
178 #define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
180 #define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c))
181 #define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c))
182 #define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c))
184 #define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
185 #define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
186 #define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
188 #define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
190 #define IO_SPACE_LIMIT 0xffffffff
192 extern unsigned long generic_io_base;
195 * This function provides a method for the generic case where a board-specific
196 * ioport_map simply needs to return the port + some arbitrary port base.
198 * We use this at board setup time to implicitly set the port base, and
199 * as a result, we can use the generic ioport_map.
201 static inline void __set_io_port_base(unsigned long pbase)
203 generic_io_base = pbase;
206 #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
208 /* We really want to try and get these to memcpy etc */
209 extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
210 extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
211 extern void memset_io(volatile void __iomem *, int, unsigned long);
213 /* SuperH on-chip I/O functions */
214 static inline unsigned char ctrl_inb(unsigned long addr)
216 return *(volatile unsigned char*)addr;
219 static inline unsigned short ctrl_inw(unsigned long addr)
221 return *(volatile unsigned short*)addr;
224 static inline unsigned int ctrl_inl(unsigned long addr)
226 return *(volatile unsigned long*)addr;
229 static inline unsigned long long ctrl_inq(unsigned long addr)
231 return *(volatile unsigned long long*)addr;
234 static inline void ctrl_outb(unsigned char b, unsigned long addr)
236 *(volatile unsigned char*)addr = b;
239 static inline void ctrl_outw(unsigned short b, unsigned long addr)
241 *(volatile unsigned short*)addr = b;
244 static inline void ctrl_outl(unsigned int b, unsigned long addr)
246 *(volatile unsigned long*)addr = b;
249 static inline void ctrl_outq(unsigned long long b, unsigned long addr)
251 *(volatile unsigned long long*)addr = b;
254 static inline void ctrl_delay(void)
261 /* Quad-word real-mode I/O, don't ask.. */
262 unsigned long long peek_real_address_q(unsigned long long addr);
263 unsigned long long poke_real_address_q(unsigned long long addr,
264 unsigned long long val);
266 #if !defined(CONFIG_MMU)
267 #define virt_to_phys(address) ((unsigned long)(address))
268 #define phys_to_virt(address) ((void *)(address))
270 #define virt_to_phys(address) (__pa(address))
271 #define phys_to_virt(address) (__va(address))
275 * On 32-bit SH, we traditionally have the whole physical address space
276 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
277 * not need to do anything but place the address in the proper segment.
278 * This is true for P1 and P2 addresses, as well as some P3 ones.
279 * However, most of the P3 addresses and newer cores using extended
280 * addressing need to map through page tables, so the ioremap()
281 * implementation becomes a bit more complicated.
283 * See arch/sh/mm/ioremap.c for additional notes on this.
285 * We cheat a bit and always return uncachable areas until we've fixed
286 * the drivers to handle caching properly.
288 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
289 * doesn't exist, so everything must go through page tables.
292 void __iomem *__ioremap(unsigned long offset, unsigned long size,
293 unsigned long flags);
294 void __iounmap(void __iomem *addr);
296 /* arch/sh/mm/ioremap_64.c */
297 unsigned long onchip_remap(unsigned long addr, unsigned long size,
299 extern void onchip_unmap(unsigned long vaddr);
301 #define __ioremap(offset, size, flags) ((void __iomem *)(offset))
302 #define __iounmap(addr) do { } while (0)
303 #define onchip_remap(addr, size, name) (addr)
304 #define onchip_unmap(addr) do { } while (0)
305 #endif /* CONFIG_MMU */
307 static inline void __iomem *
308 __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
310 #ifdef CONFIG_SUPERH32
311 unsigned long last_addr = offset + size - 1;
315 ret = __ioremap_trapped(offset, size);
319 #ifdef CONFIG_SUPERH32
321 * For P1 and P2 space this is trivial, as everything is already
322 * mapped. Uncached access for P1 addresses are done through P2.
323 * In the P3 case or for addresses outside of the 29-bit space,
324 * mapping must be done by the PMB or by using page tables.
326 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
327 if (unlikely(flags & _PAGE_CACHABLE))
328 return (void __iomem *)P1SEGADDR(offset);
330 return (void __iomem *)P2SEGADDR(offset);
334 return __ioremap(offset, size, flags);
337 #define ioremap(offset, size) \
338 __ioremap_mode((offset), (size), 0)
339 #define ioremap_nocache(offset, size) \
340 __ioremap_mode((offset), (size), 0)
341 #define ioremap_cache(offset, size) \
342 __ioremap_mode((offset), (size), _PAGE_CACHABLE)
343 #define p3_ioremap(offset, size, flags) \
344 __ioremap((offset), (size), (flags))
345 #define ioremap_prot(offset, size, flags) \
346 __ioremap_mode((offset), (size), (flags))
347 #define iounmap(addr) \
351 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
354 #define xlate_dev_mem_ptr(p) __va(p)
357 * Convert a virtual cached pointer to an uncached pointer
359 #define xlate_dev_kmem_ptr(p) p
361 #endif /* __KERNEL__ */
363 #endif /* __ASM_SH_IO_H */