2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
15 #include <linux/errno.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/param.h>
20 #include <linux/string.h>
22 #include <linux/interrupt.h>
23 #include <linux/time.h>
24 #include <linux/sysdev.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/smp.h>
28 #include <linux/types.h>
29 #include <linux/profile.h>
30 #include <linux/timex.h>
31 #include <linux/notifier.h>
32 #include <linux/clocksource.h>
33 #include <linux/clockchips.h>
34 #include <asm/uaccess.h>
35 #include <asm/delay.h>
36 #include <asm/s390_ext.h>
37 #include <asm/div64.h>
39 #include <asm/irq_regs.h>
40 #include <asm/timer.h>
43 /* change this if you have some constant time drift */
44 #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
45 #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
47 /* The value of the TOD clock for 1.1.1970. */
48 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
51 * Create a small time difference between the timer interrupts
52 * on the different cpus to avoid lock contention.
54 #define CPU_DEVIATION (smp_processor_id() << 12)
56 #define TICK_SIZE tick
58 static ext_int_info_t ext_int_info_cc;
59 static ext_int_info_t ext_int_etr_cc;
60 static u64 jiffies_timer_cc;
62 static DEFINE_PER_CPU(struct clock_event_device, comparators);
65 * Scheduler clock - returns current time in nanosec units.
67 unsigned long long sched_clock(void)
69 return ((get_clock_xt() - jiffies_timer_cc) * 125) >> 9;
73 * Monotonic_clock - returns # of nanoseconds passed since time_init()
75 unsigned long long monotonic_clock(void)
79 EXPORT_SYMBOL(monotonic_clock);
81 void tod_to_timeval(__u64 todval, struct timespec *xtime)
83 unsigned long long sec;
88 todval -= (sec * 1000000) << 12;
89 xtime->tv_nsec = ((todval * 1000) >> 12);
92 #ifdef CONFIG_PROFILING
93 #define s390_do_profile() profile_tick(CPU_PROFILING)
95 #define s390_do_profile() do { ; } while(0)
96 #endif /* CONFIG_PROFILING */
98 void clock_comparator_work(void)
100 struct clock_event_device *cd;
102 S390_lowcore.clock_comparator = -1ULL;
103 set_clock_comparator(S390_lowcore.clock_comparator);
104 cd = &__get_cpu_var(comparators);
105 cd->event_handler(cd);
110 * Fixup the clock comparator.
112 static void fixup_clock_comparator(unsigned long long delta)
114 /* If nobody is waiting there's nothing to fix. */
115 if (S390_lowcore.clock_comparator == -1ULL)
117 S390_lowcore.clock_comparator += delta;
118 set_clock_comparator(S390_lowcore.clock_comparator);
121 static int s390_next_event(unsigned long delta,
122 struct clock_event_device *evt)
124 S390_lowcore.clock_comparator = get_clock() + delta;
125 set_clock_comparator(S390_lowcore.clock_comparator);
129 static void s390_set_mode(enum clock_event_mode mode,
130 struct clock_event_device *evt)
135 * Set up lowcore and control register of the current cpu to
136 * enable TOD clock and clock comparator interrupts.
138 void init_cpu_timer(void)
140 struct clock_event_device *cd;
143 S390_lowcore.clock_comparator = -1ULL;
144 set_clock_comparator(S390_lowcore.clock_comparator);
146 cpu = smp_processor_id();
147 cd = &per_cpu(comparators, cpu);
148 cd->name = "comparator";
149 cd->features = CLOCK_EVT_FEAT_ONESHOT;
152 cd->min_delta_ns = 1;
153 cd->max_delta_ns = LONG_MAX;
155 cd->cpumask = cpumask_of_cpu(cpu);
156 cd->set_next_event = s390_next_event;
157 cd->set_mode = s390_set_mode;
159 clockevents_register_device(cd);
161 /* Enable clock comparator timer interrupt. */
164 /* Always allow ETR external interrupts, even without an ETR. */
168 static void clock_comparator_interrupt(__u16 code)
172 static void etr_reset(void);
173 static void etr_ext_handler(__u16);
176 * Get the TOD clock running.
178 static u64 __init reset_tod_clock(void)
183 if (store_clock(&time) == 0)
185 /* TOD clock not running. Set the clock to Unix Epoch. */
186 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
187 panic("TOD clock not operational.");
189 return TOD_UNIX_EPOCH;
192 static cycle_t read_tod_clock(void)
197 static struct clocksource clocksource_tod = {
200 .read = read_tod_clock,
204 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
209 * Initialize the TOD clock and the CPU timer of
212 void __init time_init(void)
216 init_timer_cc = reset_tod_clock();
217 jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY;
220 tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime);
221 set_normalized_timespec(&wall_to_monotonic,
222 -xtime.tv_sec, -xtime.tv_nsec);
224 /* request the clock comparator external interrupt */
225 if (register_early_external_interrupt(0x1004,
226 clock_comparator_interrupt,
227 &ext_int_info_cc) != 0)
228 panic("Couldn't request external interrupt 0x1004");
230 if (clocksource_register(&clocksource_tod) != 0)
231 panic("Could not register TOD clock source");
233 /* request the etr external interrupt */
234 if (register_early_external_interrupt(0x1406, etr_ext_handler,
235 &ext_int_etr_cc) != 0)
236 panic("Couldn't request external interrupt 0x1406");
238 /* Enable TOD clock interrupts on the boot cpu. */
241 #ifdef CONFIG_VIRT_TIMER
247 * External Time Reference (ETR) code.
249 static int etr_port0_online;
250 static int etr_port1_online;
252 static int __init early_parse_etr(char *p)
254 if (strncmp(p, "off", 3) == 0)
255 etr_port0_online = etr_port1_online = 0;
256 else if (strncmp(p, "port0", 5) == 0)
257 etr_port0_online = 1;
258 else if (strncmp(p, "port1", 5) == 0)
259 etr_port1_online = 1;
260 else if (strncmp(p, "on", 2) == 0)
261 etr_port0_online = etr_port1_online = 1;
264 early_param("etr", early_parse_etr);
267 ETR_EVENT_PORT0_CHANGE,
268 ETR_EVENT_PORT1_CHANGE,
269 ETR_EVENT_PORT_ALERT,
270 ETR_EVENT_SYNC_CHECK,
271 ETR_EVENT_SWITCH_LOCAL,
282 * Valid bit combinations of the eacr register are (x = don't care):
283 * e0 e1 dp p0 p1 ea es sl
284 * 0 0 x 0 0 0 0 0 initial, disabled state
285 * 0 0 x 0 1 1 0 0 port 1 online
286 * 0 0 x 1 0 1 0 0 port 0 online
287 * 0 0 x 1 1 1 0 0 both ports online
288 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
289 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
290 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
291 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
292 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
293 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
294 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
295 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
296 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
297 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
298 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
299 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
300 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
301 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
302 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
303 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
305 static struct etr_eacr etr_eacr;
306 static u64 etr_tolec; /* time of last eacr update */
307 static unsigned long etr_flags;
308 static struct etr_aib etr_port0;
309 static int etr_port0_uptodate;
310 static struct etr_aib etr_port1;
311 static int etr_port1_uptodate;
312 static unsigned long etr_events;
313 static struct timer_list etr_timer;
314 static DEFINE_PER_CPU(atomic_t, etr_sync_word);
316 static void etr_timeout(unsigned long dummy);
317 static void etr_work_fn(struct work_struct *work);
318 static DECLARE_WORK(etr_work, etr_work_fn);
321 * The etr get_clock function. It will write the current clock value
322 * to the clock pointer and return 0 if the clock is in sync with the
323 * external time source. If the clock mode is local it will return
324 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
325 * reference. This function is what ETR is all about..
327 int get_sync_clock(unsigned long long *clock)
330 unsigned int sw0, sw1;
332 sw_ptr = &get_cpu_var(etr_sync_word);
333 sw0 = atomic_read(sw_ptr);
334 *clock = get_clock();
335 sw1 = atomic_read(sw_ptr);
336 put_cpu_var(etr_sync_sync);
337 if (sw0 == sw1 && (sw0 & 0x80000000U))
338 /* Success: time is in sync. */
340 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
342 if (test_bit(ETR_FLAG_EACCES, &etr_flags))
346 EXPORT_SYMBOL(get_sync_clock);
349 * Make get_sync_clock return -EAGAIN.
351 static void etr_disable_sync_clock(void *dummy)
353 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word);
355 * Clear the in-sync bit 2^31. All get_sync_clock calls will
356 * fail until the sync bit is turned back on. In addition
357 * increase the "sequence" counter to avoid the race of an
358 * etr event and the complete recovery against get_sync_clock.
360 atomic_clear_mask(0x80000000, sw_ptr);
365 * Make get_sync_clock return 0 again.
366 * Needs to be called from a context disabled for preemption.
368 static void etr_enable_sync_clock(void)
370 atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word);
371 atomic_set_mask(0x80000000, sw_ptr);
375 * Reset ETR attachment.
377 static void etr_reset(void)
379 etr_eacr = (struct etr_eacr) {
380 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
381 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
383 if (etr_setr(&etr_eacr) == 0)
384 etr_tolec = get_clock();
386 set_bit(ETR_FLAG_ENOSYS, &etr_flags);
387 if (etr_port0_online || etr_port1_online) {
388 printk(KERN_WARNING "Running on non ETR capable "
389 "machine, only local mode available.\n");
390 etr_port0_online = etr_port1_online = 0;
395 static int __init etr_init(void)
399 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
401 /* Check if this machine has the steai instruction. */
402 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
403 set_bit(ETR_FLAG_STEAI, &etr_flags);
404 setup_timer(&etr_timer, etr_timeout, 0UL);
405 if (!etr_port0_online && !etr_port1_online)
406 set_bit(ETR_FLAG_EACCES, &etr_flags);
407 if (etr_port0_online) {
408 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
409 schedule_work(&etr_work);
411 if (etr_port1_online) {
412 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
413 schedule_work(&etr_work);
418 arch_initcall(etr_init);
421 * Two sorts of ETR machine checks. The architecture reads:
422 * "When a machine-check niterruption occurs and if a switch-to-local or
423 * ETR-sync-check interrupt request is pending but disabled, this pending
424 * disabled interruption request is indicated and is cleared".
425 * Which means that we can get etr_switch_to_local events from the machine
426 * check handler although the interruption condition is disabled. Lovely..
430 * Switch to local machine check. This is called when the last usable
431 * ETR port goes inactive. After switch to local the clock is not in sync.
433 void etr_switch_to_local(void)
437 etr_disable_sync_clock(NULL);
438 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
439 schedule_work(&etr_work);
443 * ETR sync check machine check. This is called when the ETR OTE and the
444 * local clock OTE are farther apart than the ETR sync check tolerance.
445 * After a ETR sync check the clock is not in sync. The machine check
446 * is broadcasted to all cpus at the same time.
448 void etr_sync_check(void)
452 etr_disable_sync_clock(NULL);
453 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
454 schedule_work(&etr_work);
458 * ETR external interrupt. There are two causes:
459 * 1) port state change, check the usability of the port
460 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
461 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
462 * or ETR-data word 4 (edf4) has changed.
464 static void etr_ext_handler(__u16 code)
466 struct etr_interruption_parameter *intparm =
467 (struct etr_interruption_parameter *) &S390_lowcore.ext_params;
470 /* ETR port 0 state change. */
471 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
473 /* ETR port 1 state change. */
474 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
477 * ETR port alert on either port 0, 1 or both.
478 * Both ports are not up-to-date now.
480 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
481 schedule_work(&etr_work);
484 static void etr_timeout(unsigned long dummy)
486 set_bit(ETR_EVENT_UPDATE, &etr_events);
487 schedule_work(&etr_work);
491 * Check if the etr mode is pss.
493 static inline int etr_mode_is_pps(struct etr_eacr eacr)
495 return eacr.es && !eacr.sl;
499 * Check if the etr mode is etr.
501 static inline int etr_mode_is_etr(struct etr_eacr eacr)
503 return eacr.es && eacr.sl;
507 * Check if the port can be used for TOD synchronization.
508 * For PPS mode the port has to receive OTEs. For ETR mode
509 * the port has to receive OTEs, the ETR stepping bit has to
510 * be zero and the validity bits for data frame 1, 2, and 3
513 static int etr_port_valid(struct etr_aib *aib, int port)
517 /* Check that this port is receiving OTEs. */
521 psc = port ? aib->esw.psc1 : aib->esw.psc0;
522 if (psc == etr_lpsc_pps_mode)
524 if (psc == etr_lpsc_operational_step)
525 return !aib->esw.y && aib->slsw.v1 &&
526 aib->slsw.v2 && aib->slsw.v3;
531 * Check if two ports are on the same network.
533 static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
535 // FIXME: any other fields we have to compare?
536 return aib1->edf1.net_id == aib2->edf1.net_id;
540 * Wrapper for etr_stei that converts physical port states
541 * to logical port states to be consistent with the output
542 * of stetr (see etr_psc vs. etr_lpsc).
544 static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
546 BUG_ON(etr_steai(aib, func) != 0);
547 /* Convert port state to logical port state. */
548 if (aib->esw.psc0 == 1)
550 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
552 if (aib->esw.psc1 == 1)
554 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
559 * Check if the aib a2 is still connected to the same attachment as
560 * aib a1, the etv values differ by one and a2 is valid.
562 static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
564 int state_a1, state_a2;
566 /* Paranoia check: e0/e1 should better be the same. */
567 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
568 a1->esw.eacr.e1 != a2->esw.eacr.e1)
571 /* Still connected to the same etr ? */
572 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
573 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
574 if (state_a1 == etr_lpsc_operational_step) {
575 if (state_a2 != etr_lpsc_operational_step ||
576 a1->edf1.net_id != a2->edf1.net_id ||
577 a1->edf1.etr_id != a2->edf1.etr_id ||
578 a1->edf1.etr_pn != a2->edf1.etr_pn)
580 } else if (state_a2 != etr_lpsc_pps_mode)
583 /* The ETV value of a2 needs to be ETV of a1 + 1. */
584 if (a1->edf2.etv + 1 != a2->edf2.etv)
587 if (!etr_port_valid(a2, p))
594 * The time is "clock". old is what we think the time is.
595 * Adjust the value by a multiple of jiffies and add the delta to ntp.
596 * "delay" is an approximation how long the synchronization took. If
597 * the time correction is positive, then "delay" is subtracted from
598 * the time difference and only the remaining part is passed to ntp.
600 static unsigned long long etr_adjust_time(unsigned long long old,
601 unsigned long long clock,
602 unsigned long long delay)
604 unsigned long long delta, ticks;
608 /* It is later than we thought. */
609 delta = ticks = clock - old;
610 delta = ticks = (delta < delay) ? 0 : delta - delay;
611 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
612 adjust.offset = ticks * (1000000 / HZ);
614 /* It is earlier than we thought. */
615 delta = ticks = old - clock;
616 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
618 adjust.offset = -ticks * (1000000 / HZ);
620 jiffies_timer_cc += delta;
621 if (adjust.offset != 0) {
622 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
624 adjust.modes = ADJ_OFFSET_SINGLESHOT;
625 do_adjtimex(&adjust);
632 unsigned long long fixup_cc;
635 static void etr_sync_cpu_start(void *dummy)
637 etr_enable_sync_clock();
639 * This looks like a busy wait loop but it isn't. etr_sync_cpus
640 * is called on all other cpus while the TOD clocks is stopped.
641 * __udelay will stop the cpu on an enabled wait psw until the
642 * TOD is running again.
644 while (etr_sync.in_sync == 0) {
647 * A different cpu changes *in_sync. Therefore use
648 * barrier() to force memory access.
652 if (etr_sync.in_sync != 1)
653 /* Didn't work. Clear per-cpu in sync bit again. */
654 etr_disable_sync_clock(NULL);
656 * This round of TOD syncing is done. Set the clock comparator
657 * to the next tick and let the processor continue.
659 fixup_clock_comparator(etr_sync.fixup_cc);
662 static void etr_sync_cpu_end(void *dummy)
667 * Sync the TOD clock using the port refered to by aibp. This port
668 * has to be enabled and the other port has to be disabled. The
669 * last eacr update has to be more than 1.6 seconds in the past.
671 static int etr_sync_clock(struct etr_aib *aib, int port)
673 struct etr_aib *sync_port;
674 unsigned long long clock, old_clock, delay, delta;
678 /* Check if the current aib is adjacent to the sync port aib. */
679 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
680 follows = etr_aib_follows(sync_port, aib, port);
681 memcpy(sync_port, aib, sizeof(*aib));
686 * Catch all other cpus and make them wait until we have
687 * successfully synced the clock. smp_call_function will
688 * return after all other cpus are in etr_sync_cpu_start.
690 memset(&etr_sync, 0, sizeof(etr_sync));
692 smp_call_function(etr_sync_cpu_start, NULL, 0, 0);
694 etr_enable_sync_clock();
696 /* Set clock to next OTE. */
697 __ctl_set_bit(14, 21);
698 __ctl_set_bit(0, 29);
699 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
700 old_clock = get_clock();
701 if (set_clock(clock) == 0) {
702 __udelay(1); /* Wait for the clock to start. */
703 __ctl_clear_bit(0, 29);
704 __ctl_clear_bit(14, 21);
706 /* Adjust Linux timing variables. */
707 delay = (unsigned long long)
708 (aib->edf2.etv - sync_port->edf2.etv) << 32;
709 delta = etr_adjust_time(old_clock, clock, delay);
710 etr_sync.fixup_cc = delta;
711 fixup_clock_comparator(delta);
712 /* Verify that the clock is properly set. */
713 if (!etr_aib_follows(sync_port, aib, port)) {
715 etr_disable_sync_clock(NULL);
716 etr_sync.in_sync = -EAGAIN;
719 etr_sync.in_sync = 1;
723 /* Could not set the clock ?!? */
724 __ctl_clear_bit(0, 29);
725 __ctl_clear_bit(14, 21);
726 etr_disable_sync_clock(NULL);
727 etr_sync.in_sync = -EAGAIN;
731 smp_call_function(etr_sync_cpu_end,NULL,0,0);
737 * Handle the immediate effects of the different events.
738 * The port change event is used for online/offline changes.
740 static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
742 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
744 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
745 eacr.es = eacr.sl = 0;
746 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
747 etr_port0_uptodate = etr_port1_uptodate = 0;
749 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
752 * Port change of an enabled port. We have to
753 * assume that this can have caused an stepping
756 etr_tolec = get_clock();
757 eacr.p0 = etr_port0_online;
760 etr_port0_uptodate = 0;
762 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
765 * Port change of an enabled port. We have to
766 * assume that this can have caused an stepping
769 etr_tolec = get_clock();
770 eacr.p1 = etr_port1_online;
773 etr_port1_uptodate = 0;
775 clear_bit(ETR_EVENT_UPDATE, &etr_events);
780 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
781 * one of the ports needs an update.
783 static void etr_set_tolec_timeout(unsigned long long now)
785 unsigned long micros;
787 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
788 (!etr_eacr.p1 || etr_port1_uptodate))
790 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
791 micros = (micros > 1600000) ? 0 : 1600000 - micros;
792 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
796 * Set up a time that expires after 1/2 second.
798 static void etr_set_sync_timeout(void)
800 mod_timer(&etr_timer, jiffies + HZ/2);
804 * Update the aib information for one or both ports.
806 static struct etr_eacr etr_handle_update(struct etr_aib *aib,
807 struct etr_eacr eacr)
809 /* With both ports disabled the aib information is useless. */
810 if (!eacr.e0 && !eacr.e1)
813 /* Update port0 or port1 with aib stored in etr_work_fn. */
814 if (aib->esw.q == 0) {
815 /* Information for port 0 stored. */
816 if (eacr.p0 && !etr_port0_uptodate) {
818 if (etr_port0_online)
819 etr_port0_uptodate = 1;
822 /* Information for port 1 stored. */
823 if (eacr.p1 && !etr_port1_uptodate) {
825 if (etr_port0_online)
826 etr_port1_uptodate = 1;
831 * Do not try to get the alternate port aib if the clock
832 * is not in sync yet.
838 * If steai is available we can get the information about
839 * the other port immediately. If only stetr is available the
840 * data-port bit toggle has to be used.
842 if (test_bit(ETR_FLAG_STEAI, &etr_flags)) {
843 if (eacr.p0 && !etr_port0_uptodate) {
844 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
845 etr_port0_uptodate = 1;
847 if (eacr.p1 && !etr_port1_uptodate) {
848 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
849 etr_port1_uptodate = 1;
853 * One port was updated above, if the other
854 * port is not uptodate toggle dp bit.
856 if ((eacr.p0 && !etr_port0_uptodate) ||
857 (eacr.p1 && !etr_port1_uptodate))
866 * Write new etr control register if it differs from the current one.
867 * Return 1 if etr_tolec has been updated as well.
869 static void etr_update_eacr(struct etr_eacr eacr)
873 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
874 /* No change, return. */
877 * The disable of an active port of the change of the data port
878 * bit can/will cause a change in the data port.
880 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
881 (etr_eacr.dp ^ eacr.dp) != 0;
885 etr_tolec = get_clock();
889 * ETR tasklet. In this function you'll find the main logic. In
890 * particular this is the only function that calls etr_update_eacr(),
891 * it "controls" the etr control register.
893 static void etr_work_fn(struct work_struct *work)
895 unsigned long long now;
896 struct etr_eacr eacr;
900 /* Create working copy of etr_eacr. */
903 /* Check for the different events and their immediate effects. */
904 eacr = etr_handle_events(eacr);
906 /* Check if ETR is supposed to be active. */
907 eacr.ea = eacr.p0 || eacr.p1;
909 /* Both ports offline. Reset everything. */
910 eacr.dp = eacr.es = eacr.sl = 0;
911 on_each_cpu(etr_disable_sync_clock, NULL, 0, 1);
912 del_timer_sync(&etr_timer);
913 etr_update_eacr(eacr);
914 set_bit(ETR_FLAG_EACCES, &etr_flags);
918 /* Store aib to get the current ETR status word. */
919 BUG_ON(etr_stetr(&aib) != 0);
920 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
924 * Update the port information if the last stepping port change
925 * or data port change is older than 1.6 seconds.
927 if (now >= etr_tolec + (1600000 << 12))
928 eacr = etr_handle_update(&aib, eacr);
931 * Select ports to enable. The prefered synchronization mode is PPS.
932 * If a port can be enabled depends on a number of things:
933 * 1) The port needs to be online and uptodate. A port is not
934 * disabled just because it is not uptodate, but it is only
935 * enabled if it is uptodate.
936 * 2) The port needs to have the same mode (pps / etr).
937 * 3) The port needs to be usable -> etr_port_valid() == 1
938 * 4) To enable the second port the clock needs to be in sync.
939 * 5) If both ports are useable and are ETR ports, the network id
940 * has to be the same.
941 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
943 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
946 if (!etr_mode_is_pps(etr_eacr))
948 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
950 // FIXME: uptodate checks ?
951 else if (etr_port0_uptodate && etr_port1_uptodate)
953 sync_port = (etr_port0_uptodate &&
954 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
955 clear_bit(ETR_FLAG_EACCES, &etr_flags);
956 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
960 if (!etr_mode_is_pps(etr_eacr))
962 sync_port = (etr_port1_uptodate &&
963 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
964 clear_bit(ETR_FLAG_EACCES, &etr_flags);
965 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
968 if (!etr_mode_is_etr(etr_eacr))
970 if (!eacr.es || !eacr.p1 ||
971 aib.esw.psc1 != etr_lpsc_operational_alt)
973 else if (etr_port0_uptodate && etr_port1_uptodate &&
974 etr_compare_network(&etr_port0, &etr_port1))
976 sync_port = (etr_port0_uptodate &&
977 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
978 clear_bit(ETR_FLAG_EACCES, &etr_flags);
979 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
983 if (!etr_mode_is_etr(etr_eacr))
985 sync_port = (etr_port1_uptodate &&
986 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
987 clear_bit(ETR_FLAG_EACCES, &etr_flags);
989 /* Both ports not usable. */
990 eacr.es = eacr.sl = 0;
992 set_bit(ETR_FLAG_EACCES, &etr_flags);
996 * If the clock is in sync just update the eacr and return.
997 * If there is no valid sync port wait for a port update.
999 if (eacr.es || sync_port < 0) {
1000 etr_update_eacr(eacr);
1001 etr_set_tolec_timeout(now);
1006 * Prepare control register for clock syncing
1007 * (reset data port bit, set sync check control.
1013 * Update eacr and try to synchronize the clock. If the update
1014 * of eacr caused a stepping port switch (or if we have to
1015 * assume that a stepping port switch has occured) or the
1016 * clock syncing failed, reset the sync check control bit
1017 * and set up a timer to try again after 0.5 seconds
1019 etr_update_eacr(eacr);
1020 if (now < etr_tolec + (1600000 << 12) ||
1021 etr_sync_clock(&aib, sync_port) != 0) {
1022 /* Sync failed. Try again in 1/2 second. */
1024 etr_update_eacr(eacr);
1025 etr_set_sync_timeout();
1027 etr_set_tolec_timeout(now);
1031 * Sysfs interface functions
1033 static struct sysdev_class etr_sysclass = {
1037 static struct sys_device etr_port0_dev = {
1039 .cls = &etr_sysclass,
1042 static struct sys_device etr_port1_dev = {
1044 .cls = &etr_sysclass,
1048 * ETR class attributes
1050 static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf)
1052 return sprintf(buf, "%i\n", etr_port0.esw.p);
1055 static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1057 static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf)
1061 if (etr_mode_is_pps(etr_eacr))
1063 else if (etr_mode_is_etr(etr_eacr))
1067 return sprintf(buf, "%s\n", mode_str);
1070 static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1073 * ETR port attributes
1075 static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1077 if (dev == &etr_port0_dev)
1078 return etr_port0_online ? &etr_port0 : NULL;
1080 return etr_port1_online ? &etr_port1 : NULL;
1083 static ssize_t etr_online_show(struct sys_device *dev, char *buf)
1085 unsigned int online;
1087 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1088 return sprintf(buf, "%i\n", online);
1091 static ssize_t etr_online_store(struct sys_device *dev,
1092 const char *buf, size_t count)
1096 value = simple_strtoul(buf, NULL, 0);
1097 if (value != 0 && value != 1)
1099 if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
1101 if (dev == &etr_port0_dev) {
1102 if (etr_port0_online == value)
1103 return count; /* Nothing to do. */
1104 etr_port0_online = value;
1105 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
1106 schedule_work(&etr_work);
1108 if (etr_port1_online == value)
1109 return count; /* Nothing to do. */
1110 etr_port1_online = value;
1111 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
1112 schedule_work(&etr_work);
1117 static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1119 static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf)
1121 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1122 etr_eacr.e0 : etr_eacr.e1);
1125 static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1127 static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf)
1129 if (!etr_port0_online && !etr_port1_online)
1130 /* Status word is not uptodate if both ports are offline. */
1132 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1133 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1136 static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1138 static ssize_t etr_untuned_show(struct sys_device *dev, char *buf)
1140 struct etr_aib *aib = etr_aib_from_dev(dev);
1142 if (!aib || !aib->slsw.v1)
1144 return sprintf(buf, "%i\n", aib->edf1.u);
1147 static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1149 static ssize_t etr_network_id_show(struct sys_device *dev, char *buf)
1151 struct etr_aib *aib = etr_aib_from_dev(dev);
1153 if (!aib || !aib->slsw.v1)
1155 return sprintf(buf, "%i\n", aib->edf1.net_id);
1158 static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1160 static ssize_t etr_id_show(struct sys_device *dev, char *buf)
1162 struct etr_aib *aib = etr_aib_from_dev(dev);
1164 if (!aib || !aib->slsw.v1)
1166 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1169 static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1171 static ssize_t etr_port_number_show(struct sys_device *dev, char *buf)
1173 struct etr_aib *aib = etr_aib_from_dev(dev);
1175 if (!aib || !aib->slsw.v1)
1177 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1180 static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1182 static ssize_t etr_coupled_show(struct sys_device *dev, char *buf)
1184 struct etr_aib *aib = etr_aib_from_dev(dev);
1186 if (!aib || !aib->slsw.v3)
1188 return sprintf(buf, "%i\n", aib->edf3.c);
1191 static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1193 static ssize_t etr_local_time_show(struct sys_device *dev, char *buf)
1195 struct etr_aib *aib = etr_aib_from_dev(dev);
1197 if (!aib || !aib->slsw.v3)
1199 return sprintf(buf, "%i\n", aib->edf3.blto);
1202 static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1204 static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf)
1206 struct etr_aib *aib = etr_aib_from_dev(dev);
1208 if (!aib || !aib->slsw.v3)
1210 return sprintf(buf, "%i\n", aib->edf3.buo);
1213 static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1215 static struct sysdev_attribute *etr_port_attributes[] = {
1217 &attr_stepping_control,
1229 static int __init etr_register_port(struct sys_device *dev)
1231 struct sysdev_attribute **attr;
1234 rc = sysdev_register(dev);
1237 for (attr = etr_port_attributes; *attr; attr++) {
1238 rc = sysdev_create_file(dev, *attr);
1244 for (; attr >= etr_port_attributes; attr--)
1245 sysdev_remove_file(dev, *attr);
1246 sysdev_unregister(dev);
1251 static void __init etr_unregister_port(struct sys_device *dev)
1253 struct sysdev_attribute **attr;
1255 for (attr = etr_port_attributes; *attr; attr++)
1256 sysdev_remove_file(dev, *attr);
1257 sysdev_unregister(dev);
1260 static int __init etr_init_sysfs(void)
1264 rc = sysdev_class_register(&etr_sysclass);
1267 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1269 goto out_unreg_class;
1270 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1272 goto out_remove_stepping_port;
1273 rc = etr_register_port(&etr_port0_dev);
1275 goto out_remove_stepping_mode;
1276 rc = etr_register_port(&etr_port1_dev);
1278 goto out_remove_port0;
1282 etr_unregister_port(&etr_port0_dev);
1283 out_remove_stepping_mode:
1284 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1285 out_remove_stepping_port:
1286 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1288 sysdev_class_unregister(&etr_sysclass);
1293 device_initcall(etr_init_sysfs);