2 * include/asm-s390/ptrace.h
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 #define _S390_PTRACE_H
13 * Offsets in the user_regs_struct. They are used for the ptrace
14 * system call and in entry.S
18 #define PT_PSWMASK 0x00
19 #define PT_PSWADDR 0x04
52 #define PT_ORIGGPR2 0x88
55 * A nasty fact of life that the ptrace api
56 * only supports passing of longs.
58 #define PT_FPR0_HI 0x98
59 #define PT_FPR0_LO 0x9C
60 #define PT_FPR1_HI 0xA0
61 #define PT_FPR1_LO 0xA4
62 #define PT_FPR2_HI 0xA8
63 #define PT_FPR2_LO 0xAC
64 #define PT_FPR3_HI 0xB0
65 #define PT_FPR3_LO 0xB4
66 #define PT_FPR4_HI 0xB8
67 #define PT_FPR4_LO 0xBC
68 #define PT_FPR5_HI 0xC0
69 #define PT_FPR5_LO 0xC4
70 #define PT_FPR6_HI 0xC8
71 #define PT_FPR6_LO 0xCC
72 #define PT_FPR7_HI 0xD0
73 #define PT_FPR7_LO 0xD4
74 #define PT_FPR8_HI 0xD8
75 #define PT_FPR8_LO 0XDC
76 #define PT_FPR9_HI 0xE0
77 #define PT_FPR9_LO 0xE4
78 #define PT_FPR10_HI 0xE8
79 #define PT_FPR10_LO 0xEC
80 #define PT_FPR11_HI 0xF0
81 #define PT_FPR11_LO 0xF4
82 #define PT_FPR12_HI 0xF8
83 #define PT_FPR12_LO 0xFC
84 #define PT_FPR13_HI 0x100
85 #define PT_FPR13_LO 0x104
86 #define PT_FPR14_HI 0x108
87 #define PT_FPR14_LO 0x10C
88 #define PT_FPR15_HI 0x110
89 #define PT_FPR15_LO 0x114
91 #define PT_CR_10 0x11C
92 #define PT_CR_11 0x120
93 #define PT_IEEE_IP 0x13C
94 #define PT_LASTOFF PT_IEEE_IP
95 #define PT_ENDREGS 0x140-1
100 #define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */
102 #else /* __s390x__ */
104 #define PT_PSWMASK 0x00
105 #define PT_PSWADDR 0x08
116 #define PT_GPR10 0x60
117 #define PT_GPR11 0x68
118 #define PT_GPR12 0x70
119 #define PT_GPR13 0x78
120 #define PT_GPR14 0x80
121 #define PT_GPR15 0x88
132 #define PT_ACR10 0xB8
133 #define PT_ACR11 0xBC
134 #define PT_ACR12 0xC0
135 #define PT_ACR13 0xC4
136 #define PT_ACR14 0xC8
137 #define PT_ACR15 0xCC
138 #define PT_ORIGGPR2 0xD0
144 #define PT_FPR4 0x100
145 #define PT_FPR5 0x108
146 #define PT_FPR6 0x110
147 #define PT_FPR7 0x118
148 #define PT_FPR8 0x120
149 #define PT_FPR9 0x128
150 #define PT_FPR10 0x130
151 #define PT_FPR11 0x138
152 #define PT_FPR12 0x140
153 #define PT_FPR13 0x148
154 #define PT_FPR14 0x150
155 #define PT_FPR15 0x158
156 #define PT_CR_9 0x160
157 #define PT_CR_10 0x168
158 #define PT_CR_11 0x170
159 #define PT_IEEE_IP 0x1A8
160 #define PT_LASTOFF PT_IEEE_IP
161 #define PT_ENDREGS 0x1B0-1
166 #define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */
168 #endif /* __s390x__ */
177 #define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */
181 #define PTRACE_OLDSETOPTIONS 21
184 #include <linux/stddef.h>
185 #include <linux/types.h>
202 freg_t fprs[NUM_FPRS];
205 #define FPC_EXCEPTION_MASK 0xF8000000
206 #define FPC_FLAGS_MASK 0x00F80000
207 #define FPC_DXC_MASK 0x0000FF00
208 #define FPC_RM_MASK 0x00000003
209 #define FPC_VALID_MASK 0xF8F8FF03
211 /* this typedef defines how a Program Status Word looks like */
216 } __attribute__ ((aligned(8))) psw_t;
222 } __attribute__ ((aligned(8))) psw_compat_t;
226 #define PSW_MASK_PER 0x40000000UL
227 #define PSW_MASK_DAT 0x04000000UL
228 #define PSW_MASK_IO 0x02000000UL
229 #define PSW_MASK_EXT 0x01000000UL
230 #define PSW_MASK_KEY 0x00F00000UL
231 #define PSW_MASK_MCHECK 0x00040000UL
232 #define PSW_MASK_WAIT 0x00020000UL
233 #define PSW_MASK_PSTATE 0x00010000UL
234 #define PSW_MASK_ASC 0x0000C000UL
235 #define PSW_MASK_CC 0x00003000UL
236 #define PSW_MASK_PM 0x00000F00UL
238 #define PSW_ADDR_AMODE 0x80000000UL
239 #define PSW_ADDR_INSN 0x7FFFFFFFUL
241 #define PSW_BASE_BITS 0x00080000UL
242 #define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20)
244 #define PSW_ASC_PRIMARY 0x00000000UL
245 #define PSW_ASC_ACCREG 0x00004000UL
246 #define PSW_ASC_SECONDARY 0x00008000UL
247 #define PSW_ASC_HOME 0x0000C000UL
249 #else /* __s390x__ */
251 #define PSW_MASK_PER 0x4000000000000000UL
252 #define PSW_MASK_DAT 0x0400000000000000UL
253 #define PSW_MASK_IO 0x0200000000000000UL
254 #define PSW_MASK_EXT 0x0100000000000000UL
255 #define PSW_MASK_KEY 0x00F0000000000000UL
256 #define PSW_MASK_MCHECK 0x0004000000000000UL
257 #define PSW_MASK_WAIT 0x0002000000000000UL
258 #define PSW_MASK_PSTATE 0x0001000000000000UL
259 #define PSW_MASK_ASC 0x0000C00000000000UL
260 #define PSW_MASK_CC 0x0000300000000000UL
261 #define PSW_MASK_PM 0x00000F0000000000UL
263 #define PSW_ADDR_AMODE 0x0000000000000000UL
264 #define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL
266 #define PSW_BASE_BITS 0x0000000180000000UL
267 #define PSW_BASE32_BITS 0x0000000080000000UL
268 #define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52)
270 #define PSW_ASC_PRIMARY 0x0000000000000000UL
271 #define PSW_ASC_ACCREG 0x0000400000000000UL
272 #define PSW_ASC_SECONDARY 0x0000800000000000UL
273 #define PSW_ASC_HOME 0x0000C00000000000UL
275 extern long psw_user32_bits;
277 #endif /* __s390x__ */
279 extern long psw_kernel_bits;
280 extern long psw_user_bits;
282 /* This macro merges a NEW PSW mask specified by the user into
283 the currently active PSW mask CURRENT, modifying only those
284 bits in CURRENT that the user may be allowed to change: this
285 is the condition code and the program mask bits. */
286 #define PSW_MASK_MERGE(CURRENT,NEW) \
287 (((CURRENT) & ~(PSW_MASK_CC|PSW_MASK_PM)) | \
288 ((NEW) & (PSW_MASK_CC|PSW_MASK_PM)))
291 * The s390_regs structure is used to define the elf_gregset_t.
296 unsigned long gprs[NUM_GPRS];
297 unsigned int acrs[NUM_ACRS];
298 unsigned long orig_gpr2;
304 __u32 gprs[NUM_GPRS];
305 __u32 acrs[NUM_ACRS];
311 #include <asm/setup.h>
312 #include <asm/page.h>
315 * The pt_regs struct defines the way the registers are stored on
316 * the stack during a system call.
320 unsigned long args[1];
322 unsigned long gprs[NUM_GPRS];
323 unsigned long orig_gpr2;
324 unsigned short svcnr;
330 * Now for the program event recording (trace) definitions.
337 #define PER_EM_MASK 0xE8000000UL
343 #endif /* __s390x__ */
344 unsigned em_branching : 1;
345 unsigned em_instruction_fetch : 1;
347 * Switching on storage alteration automatically fixes
348 * the storage alteration event bit in the users std.
350 unsigned em_storage_alteration : 1;
351 unsigned em_gpr_alt_unused : 1;
352 unsigned em_store_real_address : 1;
354 unsigned branch_addr_ctl : 1;
356 unsigned storage_alt_space_ctl : 1;
358 unsigned long starting_addr;
359 unsigned long ending_addr;
364 unsigned short perc_atmid;
365 unsigned long address;
366 unsigned char access_id;
371 unsigned perc_branching : 1;
372 unsigned perc_instruction_fetch : 1;
373 unsigned perc_storage_alteration : 1;
374 unsigned perc_gpr_alt_unused : 1;
375 unsigned perc_store_real_address : 1;
377 unsigned atmid_psw_bit_31 : 1;
378 unsigned atmid_validity_bit : 1;
379 unsigned atmid_psw_bit_32 : 1;
380 unsigned atmid_psw_bit_5 : 1;
381 unsigned atmid_psw_bit_16 : 1;
382 unsigned atmid_psw_bit_17 : 1;
384 unsigned long address;
386 unsigned access_id : 4;
396 * Use these flags instead of setting em_instruction_fetch
397 * directly they are used so that single stepping can be
398 * switched on & off while not affecting other tracing
400 unsigned single_step : 1;
401 unsigned instruction_fetch : 1;
404 * These addresses are copied into cr10 & cr11 if single
405 * stepping is switched off
407 unsigned long starting_addr;
408 unsigned long ending_addr;
410 per_lowcore_words words;
411 per_lowcore_bits bits;
418 unsigned long kernel_addr;
419 unsigned long process_addr;
423 * S/390 specific non posix ptrace requests. I chose unusual values so
424 * they are unlikely to clash with future ptrace definitions.
426 #define PTRACE_PEEKUSR_AREA 0x5000
427 #define PTRACE_POKEUSR_AREA 0x5001
428 #define PTRACE_PEEKTEXT_AREA 0x5002
429 #define PTRACE_PEEKDATA_AREA 0x5003
430 #define PTRACE_POKETEXT_AREA 0x5004
431 #define PTRACE_POKEDATA_AREA 0x5005
434 * PT_PROT definition is loosely based on hppa bsd definition in
437 #define PTRACE_PROT 21
441 ptprot_set_access_watchpoint,
442 ptprot_set_write_watchpoint,
443 ptprot_disable_watchpoint
448 unsigned long lowaddr;
449 unsigned long hiaddr;
453 /* Sequence of bytes for breakpoint illegal instruction. */
454 #define S390_BREAKPOINT {0x0,0x1}
455 #define S390_BREAKPOINT_U16 ((__u16)0x0001)
456 #define S390_SYSCALL_OPCODE ((__u16)0x0a00)
457 #define S390_SYSCALL_SIZE 2
460 * The user_regs_struct defines the way the user registers are
461 * store on the stack for signal handling.
463 struct user_regs_struct
466 unsigned long gprs[NUM_GPRS];
467 unsigned int acrs[NUM_ACRS];
468 unsigned long orig_gpr2;
469 s390_fp_regs fp_regs;
471 * These per registers are in here so that gdb can modify them
472 * itself as there is no "official" ptrace interface for hardware
473 * watchpoints. This is the way intel does it.
476 unsigned long ieee_instruction_pointer;
477 /* Used to give failing instruction back to user for ieee exceptions */
482 * These are defined as per linux/ptrace.h, which see.
484 #define arch_has_single_step() (1)
486 extern void user_enable_single_step(struct task_struct *);
487 extern void user_disable_single_step(struct task_struct *);
489 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
490 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
491 #define user_stack_pointer(regs)((regs)->gprs[15])
492 #define regs_return_value(regs)((regs)->gprs[2])
493 #define profile_pc(regs) instruction_pointer(regs)
494 extern void show_regs(struct pt_regs * regs);
495 #endif /* __KERNEL__ */
496 #endif /* __ASSEMBLY__ */
498 #endif /* _S390_PTRACE_H */