arch/powerpc/platforms/pseries/xics.c

   1 /*
   2  * arch/powerpc/platforms/pseries/xics.c
   3  *
   4  * Copyright 2000 IBM Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/types.h>
  15 #include <linux/threads.h>
  16 #include <linux/kernel.h>
  17 #include <linux/irq.h>
  18 #include <linux/smp.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/signal.h>
  21 #include <linux/init.h>
  22 #include <linux/gfp.h>
  23 #include <linux/radix-tree.h>
  24 #include <linux/cpu.h>
  25
  26 #include <asm/firmware.h>
  27 #include <asm/prom.h>
  28 #include <asm/io.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/smp.h>
  31 #include <asm/rtas.h>
  32 #include <asm/hvcall.h>
  33 #include <asm/machdep.h>
  34 #include <asm/i8259.h>
  35
  36 #include "xics.h"
  37 #include "plpar_wrappers.h"
  38
  39 #define XICS_IPI                2
  40 #define XICS_IRQ_SPURIOUS       0
  41
  42 /* Want a priority other than 0.  Various HW issues require this. */
  43 #define DEFAULT_PRIORITY        5
  44
  45 /*
  46  * Mark IPIs as higher priority so we can take them inside interrupts that
  47  * arent marked IRQF_DISABLED
  48  */
  49 #define IPI_PRIORITY            4
  50
  51 struct xics_ipl {
  52         union {
  53                 u32 word;
  54                 u8 bytes[4];
  55         } xirr_poll;
  56         union {
  57                 u32 word;
  58                 u8 bytes[4];
  59         } xirr;
  60         u32 dummy;
  61         union {
  62                 u32 word;
  63                 u8 bytes[4];
  64         } qirr;
  65 };
  66
  67 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
  68
  69 static unsigned int default_server = 0xFF;
  70 static unsigned int default_distrib_server = 0;
  71 static unsigned int interrupt_server_size = 8;
  72
  73 static struct irq_host *xics_host;
  74
  75 /*
  76  * XICS only has a single IPI, so encode the messages per CPU
  77  */
  78 struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
  79
  80 /* RTAS service tokens */
  81 static int ibm_get_xive;
  82 static int ibm_set_xive;
  83 static int ibm_int_on;
  84 static int ibm_int_off;
  85
  86
  87 /* Direct HW low level accessors */
  88
  89
  90 static inline unsigned int direct_xirr_info_get(void)
  91 {
  92         int cpu = smp_processor_id();
  93
  94         return in_be32(&xics_per_cpu[cpu]->xirr.word);
  95 }
  96
  97 static inline void direct_xirr_info_set(int value)
  98 {
  99         int cpu = smp_processor_id();
 100
 101         out_be32(&xics_per_cpu[cpu]->xirr.word, value);
 102 }
 103
 104 static inline void direct_cppr_info(u8 value)
 105 {
 106         int cpu = smp_processor_id();
 107
 108         out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
 109 }
 110
 111 static inline void direct_qirr_info(int n_cpu, u8 value)
 112 {
 113         out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
 114 }
 115
 116
 117 /* LPAR low level accessors */
 118
 119
 120 static inline unsigned int lpar_xirr_info_get(void)
 121 {
 122         unsigned long lpar_rc;
 123         unsigned long return_value;
 124
 125         lpar_rc = plpar_xirr(&return_value);
 126         if (lpar_rc != H_SUCCESS)
 127                 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
 128         return (unsigned int)return_value;
 129 }
 130
 131 static inline void lpar_xirr_info_set(int value)
 132 {
 133         unsigned long lpar_rc;
 134         unsigned long val64 = value & 0xffffffff;
 135
 136         lpar_rc = plpar_eoi(val64);
 137         if (lpar_rc != H_SUCCESS)
 138                 panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
 139                       val64);
 140 }
 141
 142 static inline void lpar_cppr_info(u8 value)
 143 {
 144         unsigned long lpar_rc;
 145
 146         lpar_rc = plpar_cppr(value);
 147         if (lpar_rc != H_SUCCESS)
 148                 panic("bad return code cppr - rc = %lx\n", lpar_rc);
 149 }
 150
 151 static inline void lpar_qirr_info(int n_cpu , u8 value)
 152 {
 153         unsigned long lpar_rc;
 154
 155         lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
 156         if (lpar_rc != H_SUCCESS)
 157                 panic("bad return code qirr - rc = %lx\n", lpar_rc);
 158 }
 159
 160
 161 /* High level handlers and init code */
 162
 163
 164 #ifdef CONFIG_SMP
 165 static int get_irq_server(unsigned int virq, unsigned int strict_check)
 166 {
 167         int server;
 168         /* For the moment only implement delivery to all cpus or one cpu */
 169         cpumask_t cpumask = irq_desc[virq].affinity;
 170         cpumask_t tmp = CPU_MASK_NONE;
 171
 172         if (!distribute_irqs)
 173                 return default_server;
 174
 175         if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
 176                 cpus_and(tmp, cpu_online_map, cpumask);
 177
 178                 server = first_cpu(tmp);
 179
 180                 if (server < NR_CPUS)
 181                         return get_hard_smp_processor_id(server);
 182
 183                 if (strict_check)
 184                         return -1;
 185         }
 186
 187         if (cpus_equal(cpu_online_map, cpu_present_map))
 188                 return default_distrib_server;
 189
 190         return default_server;
 191 }
 192 #else
 193 static int get_irq_server(unsigned int virq, unsigned int strict_check)
 194 {
 195         return default_server;
 196 }
 197 #endif
 198
 199
 200 static void xics_unmask_irq(unsigned int virq)
 201 {
 202         unsigned int irq;
 203         int call_status;
 204         int server;
 205
 206         pr_debug("xics: unmask virq %d\n", virq);
 207
 208         irq = (unsigned int)irq_map[virq].hwirq;
 209         pr_debug(" -> map to hwirq 0x%x\n", irq);
 210         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 211                 return;
 212
 213         server = get_irq_server(virq, 0);
 214
 215         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
 216                                 DEFAULT_PRIORITY);
 217         if (call_status != 0) {
 218                 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
 219                        "returned %d\n", irq, call_status);
 220                 printk("set_xive %x, server %x\n", ibm_set_xive, server);
 221                 return;
 222         }
 223
 224         /* Now unmask the interrupt (often a no-op) */
 225         call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
 226         if (call_status != 0) {
 227                 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
 228                        "returned %d\n", irq, call_status);
 229                 return;
 230         }
 231 }
 232
 233 static void xics_mask_real_irq(unsigned int irq)
 234 {
 235         int call_status;
 236
 237         if (irq == XICS_IPI)
 238                 return;
 239
 240         call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
 241         if (call_status != 0) {
 242                 printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
 243                        "ibm_int_off returned %d\n", irq, call_status);
 244                 return;
 245         }
 246
 247         /* Have to set XIVE to 0xff to be able to remove a slot */
 248         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
 249                                 default_server, 0xff);
 250         if (call_status != 0) {
 251                 printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
 252                        " returned %d\n", irq, call_status);
 253                 return;
 254         }
 255 }
 256
 257 static void xics_mask_irq(unsigned int virq)
 258 {
 259         unsigned int irq;
 260
 261         pr_debug("xics: mask virq %d\n", virq);
 262
 263         irq = (unsigned int)irq_map[virq].hwirq;
 264         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 265                 return;
 266         xics_mask_real_irq(irq);
 267 }
 268
 269 static unsigned int xics_startup(unsigned int virq)
 270 {
 271         unsigned int irq;
 272
 273         /* force a reverse mapping of the interrupt so it gets in the cache */
 274         irq = (unsigned int)irq_map[virq].hwirq;
 275         irq_radix_revmap(xics_host, irq);
 276
 277         /* unmask it */
 278         xics_unmask_irq(virq);
 279         return 0;
 280 }
 281
 282 static void xics_eoi_direct(unsigned int virq)
 283 {
 284         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 285
 286         iosync();
 287         direct_xirr_info_set((0xff << 24) | irq);
 288 }
 289
 290
 291 static void xics_eoi_lpar(unsigned int virq)
 292 {
 293         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 294
 295         iosync();
 296         lpar_xirr_info_set((0xff << 24) | irq);
 297 }
 298
 299 static inline unsigned int xics_remap_irq(unsigned int vec)
 300 {
 301         unsigned int irq;
 302
 303         vec &= 0x00ffffff;
 304
 305         if (vec == XICS_IRQ_SPURIOUS)
 306                 return NO_IRQ;
 307         irq = irq_radix_revmap(xics_host, vec);
 308         if (likely(irq != NO_IRQ))
 309                 return irq;
 310
 311         printk(KERN_ERR "Interrupt %u (real) is invalid,"
 312                " disabling it.\n", vec);
 313         xics_mask_real_irq(vec);
 314         return NO_IRQ;
 315 }
 316
 317 static unsigned int xics_get_irq_direct(void)
 318 {
 319         return xics_remap_irq(direct_xirr_info_get());
 320 }
 321
 322 static unsigned int xics_get_irq_lpar(void)
 323 {
 324         return xics_remap_irq(lpar_xirr_info_get());
 325 }
 326
 327 #ifdef CONFIG_SMP
 328
 329 static irqreturn_t xics_ipi_dispatch(int cpu)
 330 {
 331         WARN_ON(cpu_is_offline(cpu));
 332
 333         while (xics_ipi_message[cpu].value) {
 334                 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
 335                                        &xics_ipi_message[cpu].value)) {
 336                         mb();
 337                         smp_message_recv(PPC_MSG_CALL_FUNCTION);
 338                 }
 339                 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
 340                                        &xics_ipi_message[cpu].value)) {
 341                         mb();
 342                         smp_message_recv(PPC_MSG_RESCHEDULE);
 343                 }
 344 #if 0
 345                 if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK,
 346                                        &xics_ipi_message[cpu].value)) {
 347                         mb();
 348                         smp_message_recv(PPC_MSG_MIGRATE_TASK);
 349                 }
 350 #endif
 351 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 352                 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
 353                                        &xics_ipi_message[cpu].value)) {
 354                         mb();
 355                         smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
 356                 }
 357 #endif
 358         }
 359         return IRQ_HANDLED;
 360 }
 361
 362 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
 363 {
 364         int cpu = smp_processor_id();
 365
 366         direct_qirr_info(cpu, 0xff);
 367
 368         return xics_ipi_dispatch(cpu);
 369 }
 370
 371 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
 372 {
 373         int cpu = smp_processor_id();
 374
 375         lpar_qirr_info(cpu, 0xff);
 376
 377         return xics_ipi_dispatch(cpu);
 378 }
 379
 380 void xics_cause_IPI(int cpu)
 381 {
 382         if (firmware_has_feature(FW_FEATURE_LPAR))
 383                 lpar_qirr_info(cpu, IPI_PRIORITY);
 384         else
 385                 direct_qirr_info(cpu, IPI_PRIORITY);
 386 }
 387
 388 #endif /* CONFIG_SMP */
 389
 390 static void xics_set_cpu_priority(unsigned char cppr)
 391 {
 392         if (firmware_has_feature(FW_FEATURE_LPAR))
 393                 lpar_cppr_info(cppr);
 394         else
 395                 direct_cppr_info(cppr);
 396         iosync();
 397 }
 398
 399 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
 400 {
 401         unsigned int irq;
 402         int status;
 403         int xics_status[2];
 404         int irq_server;
 405
 406         irq = (unsigned int)irq_map[virq].hwirq;
 407         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 408                 return;
 409
 410         status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 411
 412         if (status) {
 413                 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
 414                        "returns %d\n", irq, status);
 415                 return;
 416         }
 417
 418         /*
 419          * For the moment only implement delivery to all cpus or one cpu.
 420          * Get current irq_server for the given irq
 421          */
 422         irq_server = get_irq_server(virq, 1);
 423         if (irq_server == -1) {
 424                 char cpulist[128];
 425                 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
 426                 printk(KERN_WARNING "xics_set_affinity: No online cpus in "
 427                                 "the mask %s for irq %d\n", cpulist, virq);
 428                 return;
 429         }
 430
 431         status = rtas_call(ibm_set_xive, 3, 1, NULL,
 432                                 irq, irq_server, xics_status[1]);
 433
 434         if (status) {
 435                 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
 436                        "returns %d\n", irq, status);
 437                 return;
 438         }
 439 }
 440
 441 void xics_setup_cpu(void)
 442 {
 443         xics_set_cpu_priority(0xff);
 444
 445         /*
 446          * Put the calling processor into the GIQ.  This is really only
 447          * necessary from a secondary thread as the OF start-cpu interface
 448          * performs this function for us on primary threads.
 449          *
 450          * XXX: undo of teardown on kexec needs this too, as may hotplug
 451          */
 452         rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 453                 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
 454 }
 455
 456
 457 static struct irq_chip xics_pic_direct = {
 458         .typename = " XICS     ",
 459         .startup = xics_startup,
 460         .mask = xics_mask_irq,
 461         .unmask = xics_unmask_irq,
 462         .eoi = xics_eoi_direct,
 463         .set_affinity = xics_set_affinity
 464 };
 465
 466
 467 static struct irq_chip xics_pic_lpar = {
 468         .typename = " XICS     ",
 469         .startup = xics_startup,
 470         .mask = xics_mask_irq,
 471         .unmask = xics_unmask_irq,
 472         .eoi = xics_eoi_lpar,
 473         .set_affinity = xics_set_affinity
 474 };
 475
 476
 477 static int xics_host_match(struct irq_host *h, struct device_node *node)
 478 {
 479         /* IBM machines have interrupt parents of various funky types for things
 480          * like vdevices, events, etc... The trick we use here is to match
 481          * everything here except the legacy 8259 which is compatible "chrp,iic"
 482          */
 483         return !of_device_is_compatible(node, "chrp,iic");
 484 }
 485
 486 static int xics_host_map_direct(struct irq_host *h, unsigned int virq,
 487                                 irq_hw_number_t hw)
 488 {
 489         pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
 490
 491         get_irq_desc(virq)->status |= IRQ_LEVEL;
 492         set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq);
 493         return 0;
 494 }
 495
 496 static int xics_host_map_lpar(struct irq_host *h, unsigned int virq,
 497                               irq_hw_number_t hw)
 498 {
 499         pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
 500
 501         get_irq_desc(virq)->status |= IRQ_LEVEL;
 502         set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq);
 503         return 0;
 504 }
 505
 506 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
 507                            u32 *intspec, unsigned int intsize,
 508                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 509
 510 {
 511         /* Current xics implementation translates everything
 512          * to level. It is not technically right for MSIs but this
 513          * is irrelevant at this point. We might get smarter in the future
 514          */
 515         *out_hwirq = intspec[0];
 516         *out_flags = IRQ_TYPE_LEVEL_LOW;
 517
 518         return 0;
 519 }
 520
 521 static struct irq_host_ops xics_host_direct_ops = {
 522         .match = xics_host_match,
 523         .map = xics_host_map_direct,
 524         .xlate = xics_host_xlate,
 525 };
 526
 527 static struct irq_host_ops xics_host_lpar_ops = {
 528         .match = xics_host_match,
 529         .map = xics_host_map_lpar,
 530         .xlate = xics_host_xlate,
 531 };
 532
 533 static void __init xics_init_host(void)
 534 {
 535         struct irq_host_ops *ops;
 536
 537         if (firmware_has_feature(FW_FEATURE_LPAR))
 538                 ops = &xics_host_lpar_ops;
 539         else
 540                 ops = &xics_host_direct_ops;
 541         xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, ops,
 542                                    XICS_IRQ_SPURIOUS);
 543         BUG_ON(xics_host == NULL);
 544         irq_set_default_host(xics_host);
 545 }
 546
 547 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
 548                                      unsigned long size)
 549 {
 550 #ifdef CONFIG_SMP
 551         int i;
 552
 553         /* This may look gross but it's good enough for now, we don't quite
 554          * have a hard -> linux processor id matching.
 555          */
 556         for_each_possible_cpu(i) {
 557                 if (!cpu_present(i))
 558                         continue;
 559                 if (hw_id == get_hard_smp_processor_id(i)) {
 560                         xics_per_cpu[i] = ioremap(addr, size);
 561                         return;
 562                 }
 563         }
 564 #else
 565         if (hw_id != 0)
 566                 return;
 567         xics_per_cpu[0] = ioremap(addr, size);
 568 #endif /* CONFIG_SMP */
 569 }
 570
 571 static void __init xics_init_one_node(struct device_node *np,
 572                                       unsigned int *indx)
 573 {
 574         unsigned int ilen;
 575         const u32 *ireg;
 576
 577         /* This code does the theorically broken assumption that the interrupt
 578          * server numbers are the same as the hard CPU numbers.
 579          * This happens to be the case so far but we are playing with fire...
 580          * should be fixed one of these days. -BenH.
 581          */
 582         ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
 583
 584         /* Do that ever happen ? we'll know soon enough... but even good'old
 585          * f80 does have that property ..
 586          */
 587         WARN_ON(ireg == NULL);
 588         if (ireg) {
 589                 /*
 590                  * set node starting index for this node
 591                  */
 592                 *indx = *ireg;
 593         }
 594         ireg = of_get_property(np, "reg", &ilen);
 595         if (!ireg)
 596                 panic("xics_init_IRQ: can't find interrupt reg property");
 597
 598         while (ilen >= (4 * sizeof(u32))) {
 599                 unsigned long addr, size;
 600
 601                 /* XXX Use proper OF parsing code here !!! */
 602                 addr = (unsigned long)*ireg++ << 32;
 603                 ilen -= sizeof(u32);
 604                 addr |= *ireg++;
 605                 ilen -= sizeof(u32);
 606                 size = (unsigned long)*ireg++ << 32;
 607                 ilen -= sizeof(u32);
 608                 size |= *ireg++;
 609                 ilen -= sizeof(u32);
 610                 xics_map_one_cpu(*indx, addr, size);
 611                 (*indx)++;
 612         }
 613 }
 614
 615
 616 static void __init xics_setup_8259_cascade(void)
 617 {
 618         struct device_node *np, *old, *found = NULL;
 619         int cascade, naddr;
 620         const u32 *addrp;
 621         unsigned long intack = 0;
 622
 623         for_each_node_by_type(np, "interrupt-controller")
 624                 if (of_device_is_compatible(np, "chrp,iic")) {
 625                         found = np;
 626                         break;
 627                 }
 628         if (found == NULL) {
 629                 printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
 630                 return;
 631         }
 632         cascade = irq_of_parse_and_map(found, 0);
 633         if (cascade == NO_IRQ) {
 634                 printk(KERN_ERR "xics: failed to map cascade interrupt");
 635                 return;
 636         }
 637         pr_debug("xics: cascade mapped to irq %d\n", cascade);
 638
 639         for (old = of_node_get(found); old != NULL ; old = np) {
 640                 np = of_get_parent(old);
 641                 of_node_put(old);
 642                 if (np == NULL)
 643                         break;
 644                 if (strcmp(np->name, "pci") != 0)
 645                         continue;
 646                 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
 647                 if (addrp == NULL)
 648                         continue;
 649                 naddr = of_n_addr_cells(np);
 650                 intack = addrp[naddr-1];
 651                 if (naddr > 1)
 652                         intack |= ((unsigned long)addrp[naddr-2]) << 32;
 653         }
 654         if (intack)
 655                 printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack);
 656         i8259_init(found, intack);
 657         of_node_put(found);
 658         set_irq_chained_handler(cascade, pseries_8259_cascade);
 659 }
 660
 661 void __init xics_init_IRQ(void)
 662 {
 663         int i, j;
 664         struct device_node *np;
 665         u32 ilen, indx = 0;
 666         const u32 *ireg, *isize;
 667         int found = 0;
 668         u32 hcpuid;
 669
 670         ppc64_boot_msg(0x20, "XICS Init");
 671
 672         ibm_get_xive = rtas_token("ibm,get-xive");
 673         ibm_set_xive = rtas_token("ibm,set-xive");
 674         ibm_int_on  = rtas_token("ibm,int-on");
 675         ibm_int_off = rtas_token("ibm,int-off");
 676
 677         for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
 678                 found = 1;
 679                 if (firmware_has_feature(FW_FEATURE_LPAR))
 680                         break;
 681                 xics_init_one_node(np, &indx);
 682         }
 683         if (found == 0)
 684                 return;
 685
 686         xics_init_host();
 687
 688         /* Find the server numbers for the boot cpu. */
 689         np = of_get_cpu_node(boot_cpuid, NULL);
 690         BUG_ON(!np);
 691         ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
 692         if (!ireg)
 693                 goto skip_gserver_check;
 694         i = ilen / sizeof(int);
 695         hcpuid = get_hard_smp_processor_id(boot_cpuid);
 696
 697         /* Global interrupt distribution server is specified in the last
 698          * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
 699          * entry fom this property for current boot cpu id and use it as
 700          * default distribution server
 701          */
 702         for (j = 0; j < i; j += 2) {
 703                 if (ireg[j] == hcpuid) {
 704                         default_server = hcpuid;
 705                         default_distrib_server = ireg[j+1];
 706
 707                         isize = of_get_property(np,
 708                                         "ibm,interrupt-server#-size", NULL);
 709                         if (isize)
 710                                 interrupt_server_size = *isize;
 711                 }
 712         }
 713 skip_gserver_check:
 714         of_node_put(np);
 715
 716         if (firmware_has_feature(FW_FEATURE_LPAR))
 717                 ppc_md.get_irq = xics_get_irq_lpar;
 718         else
 719                 ppc_md.get_irq = xics_get_irq_direct;
 720
 721         xics_setup_cpu();
 722
 723         xics_setup_8259_cascade();
 724
 725         ppc64_boot_msg(0x21, "XICS Done");
 726 }
 727
 728
 729 #ifdef CONFIG_SMP
 730 void xics_request_IPIs(void)
 731 {
 732         unsigned int ipi;
 733         int rc;
 734
 735         ipi = irq_create_mapping(xics_host, XICS_IPI);
 736         BUG_ON(ipi == NO_IRQ);
 737
 738         /*
 739          * IPIs are marked IRQF_DISABLED as they must run with irqs
 740          * disabled
 741          */
 742         set_irq_handler(ipi, handle_percpu_irq);
 743         if (firmware_has_feature(FW_FEATURE_LPAR))
 744                 rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
 745                                 "IPI", NULL);
 746         else
 747                 rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
 748                                 "IPI", NULL);
 749         BUG_ON(rc);
 750 }
 751 #endif /* CONFIG_SMP */
 752
 753 void xics_teardown_cpu()
 754 {
 755         int cpu = smp_processor_id();
 756
 757         xics_set_cpu_priority(0);
 758
 759         /*
 760          * Clear IPI
 761          */
 762         if (firmware_has_feature(FW_FEATURE_LPAR))
 763                 lpar_qirr_info(cpu, 0xff);
 764         else
 765                 direct_qirr_info(cpu, 0xff);
 766 }
 767
 768 void xics_kexec_teardown_cpu(int secondary)
 769 {
 770         unsigned int ipi;
 771         struct irq_desc *desc;
 772
 773         xics_teardown_cpu();
 774
 775         /*
 776          * we need to EOI the IPI
 777          *
 778          * probably need to check all the other interrupts too
 779          * should we be flagging idle loop instead?
 780          * or creating some task to be scheduled?
 781          */
 782
 783         ipi = irq_find_mapping(xics_host, XICS_IPI);
 784         if (ipi == XICS_IRQ_SPURIOUS)
 785                 return;
 786         desc = get_irq_desc(ipi);
 787         if (desc->chip && desc->chip->eoi)
 788                 desc->chip->eoi(ipi);
 789
 790         /*
 791          * Some machines need to have at least one cpu in the GIQ,
 792          * so leave the master cpu in the group.
 793          */
 794         if (secondary)
 795                 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 796                                    (1UL << interrupt_server_size) - 1 -
 797                                    default_distrib_server, 0);
 798 }
 799
 800 #ifdef CONFIG_HOTPLUG_CPU
 801
 802 /* Interrupts are disabled. */
 803 void xics_migrate_irqs_away(void)
 804 {
 805         int status;
 806         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
 807         unsigned int irq, virq;
 808
 809         /* Reject any interrupt that was queued to us... */
 810         xics_set_cpu_priority(0);
 811
 812         /* remove ourselves from the global interrupt queue */
 813         status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 814                 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
 815         WARN_ON(status < 0);
 816
 817         /* Allow IPIs again... */
 818         xics_set_cpu_priority(DEFAULT_PRIORITY);
 819
 820         for_each_irq(virq) {
 821                 struct irq_desc *desc;
 822                 int xics_status[2];
 823                 unsigned long flags;
 824
 825                 /* We cant set affinity on ISA interrupts */
 826                 if (virq < NUM_ISA_INTERRUPTS)
 827                         continue;
 828                 if (irq_map[virq].host != xics_host)
 829                         continue;
 830                 irq = (unsigned int)irq_map[virq].hwirq;
 831                 /* We need to get IPIs still. */
 832                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 833                         continue;
 834                 desc = get_irq_desc(virq);
 835
 836                 /* We only need to migrate enabled IRQS */
 837                 if (desc == NULL || desc->chip == NULL
 838                     || desc->action == NULL
 839                     || desc->chip->set_affinity == NULL)
 840                         continue;
 841
 842                 spin_lock_irqsave(&desc->lock, flags);
 843
 844                 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 845                 if (status) {
 846                         printk(KERN_ERR "migrate_irqs_away: irq=%u "
 847                                         "ibm,get-xive returns %d\n",
 848                                         virq, status);
 849                         goto unlock;
 850                 }
 851
 852                 /*
 853                  * We only support delivery to all cpus or to one cpu.
 854                  * The irq has to be migrated only in the single cpu
 855                  * case.
 856                  */
 857                 if (xics_status[0] != hw_cpu)
 858                         goto unlock;
 859
 860                 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
 861                        virq, cpu);
 862
 863                 /* Reset affinity to all cpus */
 864                 irq_desc[virq].affinity = CPU_MASK_ALL;
 865                 desc->chip->set_affinity(virq, CPU_MASK_ALL);
 866 unlock:
 867                 spin_unlock_irqrestore(&desc->lock, flags);
 868         }
 869 }
 870 #endif