2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/iommu.h>
26 #include <asm/ppc-pci.h>
31 #define DBG(x...) printk(x)
36 static struct pci_controller *u3_agp, *u3_ht;
38 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
40 for (; node != 0;node = node->sibling) {
42 unsigned int *class_code;
45 /* For PCI<->PCI bridges or CardBus bridges, we go down */
46 class_code = (unsigned int *) get_property(node, "class-code", NULL);
47 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
48 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
50 bus_range = (int *) get_property(node, "bus-range", &len);
51 if (bus_range != NULL && len > 2 * sizeof(int)) {
52 if (bus_range[1] > higher)
53 higher = bus_range[1];
55 higher = fixup_one_level_bus_range(node->child, higher);
60 /* This routine fixes the "bus-range" property of all bridges in the
61 * system since they tend to have their "last" member wrong on macs
63 * Note that the bus numbers manipulated here are OF bus numbers, they
64 * are not Linux bus numbers.
66 static void __init fixup_bus_range(struct device_node *bridge)
71 /* Lookup the "bus-range" property for the hose */
72 bus_range = (int *) get_property(bridge, "bus-range", &len);
73 if (bus_range == NULL || len < 2 * sizeof(int)) {
74 printk(KERN_WARNING "Can't get bus-range for %s\n",
78 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
82 #define U3_AGP_CFA0(devfn, off) \
83 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
84 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
85 | (((unsigned long)(off)) & 0xFCUL))
87 #define U3_AGP_CFA1(bus, devfn, off) \
88 ((((unsigned long)(bus)) << 16) \
89 |(((unsigned long)(devfn)) << 8) \
90 |(((unsigned long)(off)) & 0xFCUL) \
93 static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
94 u8 bus, u8 dev_fn, u8 offset)
98 if (bus == hose->first_busno) {
99 if (dev_fn < (11 << 3))
101 caddr = U3_AGP_CFA0(dev_fn, offset);
103 caddr = U3_AGP_CFA1(bus, dev_fn, offset);
105 /* Uninorth will return garbage if we don't read back the value ! */
107 out_le32(hose->cfg_addr, caddr);
108 } while (in_le32(hose->cfg_addr) != caddr);
111 return ((unsigned long)hose->cfg_data) + offset;
114 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
115 int offset, int len, u32 *val)
117 struct pci_controller *hose;
120 hose = pci_bus_to_host(bus);
122 return PCIBIOS_DEVICE_NOT_FOUND;
124 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
126 return PCIBIOS_DEVICE_NOT_FOUND;
128 * Note: the caller has already checked that offset is
129 * suitably aligned and that len is 1, 2 or 4.
133 *val = in_8((u8 *)addr);
136 *val = in_le16((u16 *)addr);
139 *val = in_le32((u32 *)addr);
142 return PCIBIOS_SUCCESSFUL;
145 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
146 int offset, int len, u32 val)
148 struct pci_controller *hose;
151 hose = pci_bus_to_host(bus);
153 return PCIBIOS_DEVICE_NOT_FOUND;
155 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
157 return PCIBIOS_DEVICE_NOT_FOUND;
159 * Note: the caller has already checked that offset is
160 * suitably aligned and that len is 1, 2 or 4.
164 out_8((u8 *)addr, val);
165 (void) in_8((u8 *)addr);
168 out_le16((u16 *)addr, val);
169 (void) in_le16((u16 *)addr);
172 out_le32((u32 *)addr, val);
173 (void) in_le32((u32 *)addr);
176 return PCIBIOS_SUCCESSFUL;
179 static struct pci_ops u3_agp_pci_ops =
186 #define U3_HT_CFA0(devfn, off) \
187 ((((unsigned long)devfn) << 8) | offset)
188 #define U3_HT_CFA1(bus, devfn, off) \
189 (U3_HT_CFA0(devfn, off) \
190 + (((unsigned long)bus) << 16) \
193 static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
194 u8 bus, u8 devfn, u8 offset)
196 if (bus == hose->first_busno) {
197 if (PCI_SLOT(devfn) == 0)
199 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
201 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
204 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
205 int offset, int len, u32 *val)
207 struct pci_controller *hose;
210 hose = pci_bus_to_host(bus);
212 return PCIBIOS_DEVICE_NOT_FOUND;
214 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
216 return PCIBIOS_DEVICE_NOT_FOUND;
219 * Note: the caller has already checked that offset is
220 * suitably aligned and that len is 1, 2 or 4.
224 *val = in_8((u8 *)addr);
227 *val = in_le16((u16 *)addr);
230 *val = in_le32((u32 *)addr);
233 return PCIBIOS_SUCCESSFUL;
236 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
237 int offset, int len, u32 val)
239 struct pci_controller *hose;
242 hose = pci_bus_to_host(bus);
244 return PCIBIOS_DEVICE_NOT_FOUND;
246 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
248 return PCIBIOS_DEVICE_NOT_FOUND;
250 * Note: the caller has already checked that offset is
251 * suitably aligned and that len is 1, 2 or 4.
255 out_8((u8 *)addr, val);
256 (void) in_8((u8 *)addr);
259 out_le16((u16 *)addr, val);
260 (void) in_le16((u16 *)addr);
263 out_le32((u32 *)addr, val);
264 (void) in_le32((u32 *)addr);
267 return PCIBIOS_SUCCESSFUL;
270 static struct pci_ops u3_ht_pci_ops =
276 static void __init setup_u3_agp(struct pci_controller* hose)
278 /* On G5, we move AGP up to high bus number so we don't need
279 * to reassign bus numbers for HT. If we ever have P2P bridges
280 * on AGP, we'll have to move pci_assign_all_buses to the
281 * pci_controller structure so we enable it for AGP and not for
283 * We hard code the address because of the different size of
284 * the reg address cell, we shall fix that by killing struct
285 * reg_property and using some accessor functions instead
287 hose->first_busno = 0xf0;
288 hose->last_busno = 0xff;
289 hose->ops = &u3_agp_pci_ops;
290 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
291 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
296 static void __init setup_u3_ht(struct pci_controller* hose)
298 hose->ops = &u3_ht_pci_ops;
300 /* We hard code the address because of the different size of
301 * the reg address cell, we shall fix that by killing struct
302 * reg_property and using some accessor functions instead
304 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
306 hose->first_busno = 0;
307 hose->last_busno = 0xef;
312 static int __init add_bridge(struct device_node *dev)
315 struct pci_controller *hose;
319 struct property *of_prop;
321 DBG("Adding PCI host bridge %s\n", dev->full_name);
323 bus_range = (int *) get_property(dev, "bus-range", &len);
324 if (bus_range == NULL || len < 2 * sizeof(int)) {
325 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
329 hose = alloc_bootmem(sizeof(struct pci_controller));
332 pci_setup_pci_controller(hose);
334 hose->arch_data = dev;
335 hose->first_busno = bus_range ? bus_range[0] : 0;
336 hose->last_busno = bus_range ? bus_range[1] : 0xff;
338 of_prop = alloc_bootmem(sizeof(struct property) +
339 sizeof(hose->global_number));
341 memset(of_prop, 0, sizeof(struct property));
342 of_prop->name = "linux,pci-domain";
343 of_prop->length = sizeof(hose->global_number);
344 of_prop->value = (unsigned char *)&of_prop[1];
345 memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number));
346 prom_add_property(dev, of_prop);
350 if (device_is_compatible(dev, "u3-agp")) {
352 disp_name = "U3-AGP";
354 } else if (device_is_compatible(dev, "u3-ht")) {
359 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
360 disp_name, hose->first_busno, hose->last_busno);
362 /* Interpret the "ranges" property */
363 /* This also maps the I/O region and sets isa_io/mem_base */
364 pci_process_bridge_OF_ranges(hose, dev, primary);
365 pci_setup_phb_io(hose, primary);
367 /* Fixup "bus-range" OF property */
368 fixup_bus_range(dev);
374 void __init maple_pcibios_fixup(void)
376 struct pci_dev *dev = NULL;
378 DBG(" -> maple_pcibios_fixup\n");
380 for_each_pci_dev(dev)
381 pci_read_irq_line(dev);
383 DBG(" <- maple_pcibios_fixup\n");
386 static void __init maple_fixup_phb_resources(void)
388 struct pci_controller *hose, *tmp;
390 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
391 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
392 hose->io_resource.start += offset;
393 hose->io_resource.end += offset;
394 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
396 hose->io_resource.start, hose->io_resource.end);
400 void __init maple_pci_init(void)
402 struct device_node *np, *root;
403 struct device_node *ht = NULL;
405 /* Probe root PCI hosts, that is on U3 the AGP host and the
406 * HyperTransport host. That one is actually "kept" around
407 * and actually added last as it's resource management relies
408 * on the AGP resources to have been setup first
410 root = of_find_node_by_path("/");
412 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
415 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
416 if (np->name == NULL)
418 if (strcmp(np->name, "pci") == 0) {
419 if (add_bridge(np) == 0)
422 if (strcmp(np->name, "ht") == 0) {
429 /* Now setup the HyperTransport host if we found any
431 if (ht && add_bridge(ht) != 0)
434 /* Fixup the IO resources on our host bridges as the common code
435 * does it only for childs of the host bridges
437 maple_fixup_phb_resources();
439 /* Setup the linkage between OF nodes and PHBs */
442 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
443 * assume there is no P2P bridge on the AGP bus, which should be a
444 * safe assumptions hopefully.
447 struct device_node *np = u3_agp->arch_data;
448 PCI_DN(np)->busno = 0xf0;
449 for (np = np->child; np; np = np->sibling)
450 PCI_DN(np)->busno = 0xf0;
453 /* Tell pci.c to use the common resource allocation mecanism */
460 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
462 struct device_node *np;
463 int irq = channel ? 15 : 14;
465 if (pdev->vendor != PCI_VENDOR_ID_AMD ||
466 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
469 np = pci_device_to_OF_node(pdev);
474 return np->intrs[channel & 0x1].line;
477 /* XXX: To remove once all firmwares are ok */
478 static void fixup_maple_ide(struct pci_dev* dev)
480 #if 0 /* Enable this to enable IDE port 0 */
484 pci_read_config_byte(dev, 0x40, &v);
486 pci_write_config_byte(dev, 0x40, v);
489 #if 0 /* fix bus master base */
490 pci_write_config_dword(dev, 0x20, 0xcc01);
491 printk("old ide resource: %lx -> %lx \n",
492 dev->resource[4].start, dev->resource[4].end);
493 dev->resource[4].start = 0xcc00;
494 dev->resource[4].end = 0xcc10;
496 #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
498 struct pci_dev *apicdev;
501 apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
503 printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
505 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
506 pci_read_config_dword(apicdev, 0xf4, &v);
508 pci_write_config_dword(apicdev, 0xf4, v);
509 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
510 pci_read_config_dword(apicdev, 0xf4, &v);
512 pci_write_config_dword(apicdev, 0xf4, v);
513 pci_dev_put(apicdev);
518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,