2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
3 * Copyright (C) 2005,2007 Stephen Rothwell, IBM Corp
5 * iSeries specific routines for PCI.
7 * Based on code from pci.c and iSeries_pci.c 32bit
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/string.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
33 #include <asm/types.h>
37 #include <asm/machdep.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/iommu.h>
40 #include <asm/abs_addr.h>
41 #include <asm/firmware.h>
43 #include <asm/iseries/hv_types.h>
44 #include <asm/iseries/hv_call_xm.h>
45 #include <asm/iseries/mf.h>
46 #include <asm/iseries/iommu.h>
48 #include <asm/ppc-pci.h>
54 #define PCI_RETRY_MAX 3
55 static int limit_pci_retries = 1; /* Set Retry Error on. */
59 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
61 #define IOMM_TABLE_MAX_ENTRIES 1024
62 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
63 #define BASE_IO_MEMORY 0xE000000000000000UL
64 #define END_IO_MEMORY 0xEFFFFFFFFFFFFFFFUL
66 static unsigned long max_io_memory = BASE_IO_MEMORY;
67 static long current_iomm_table_entry;
72 static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
73 static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES];
75 static DEFINE_SPINLOCK(iomm_table_lock);
78 * Generate a Direct Select Address for the Hypervisor
80 static inline u64 iseries_ds_addr(struct device_node *node)
82 struct pci_dn *pdn = PCI_DN(node);
84 return ((u64)pdn->busno << 48) + ((u64)pdn->bussubno << 40)
89 * Size of Bus VPD data
91 #define BUS_VPDSIZE 1024
96 #define VPD_END_OF_AREA 0x79
97 #define VPD_ID_STRING 0x82
98 #define VPD_VENDOR_AREA 0x84
103 #define VPD_FRU_FRAME_ID 0x4649 /* "FI" */
104 #define VPD_SLOT_MAP_FORMAT 0x4D46 /* "MF" */
105 #define VPD_SLOT_MAP 0x534D /* "SM" */
108 * Structures of the areas
110 struct mfg_vpd_area {
116 #define MFG_ENTRY_SIZE 3
122 char card_location[3];
126 #define SLOT_ENTRY_SIZE 16
129 * Parse the Slot Area
131 static void __init iseries_parse_slot_area(struct slot_map *map, int len,
132 HvAgentId agent, u8 *phb, char card[4])
135 * Parse Slot label until we find the one requested
138 if (map->agent == agent) {
140 * If Phb wasn't found, grab the entry first one found.
144 /* Found it, extract the data. */
145 if (map->phb == *phb) {
146 memcpy(card, &map->card_location, 3);
151 /* Point to the next Slot */
152 map = (struct slot_map *)((char *)map + SLOT_ENTRY_SIZE);
153 len -= SLOT_ENTRY_SIZE;
160 static void __init iseries_parse_mfg_area(struct mfg_vpd_area *area, int len,
161 HvAgentId agent, u8 *phb, u8 *frame, char card[4])
163 u16 slot_map_fmt = 0;
167 int mfg_tag_len = area->length;
168 /* Frame ID (FI 4649020310 ) */
169 if (area->tag == VPD_FRU_FRAME_ID)
170 *frame = area->data1;
171 /* Slot Map Format (MF 4D46020004 ) */
172 else if (area->tag == VPD_SLOT_MAP_FORMAT)
173 slot_map_fmt = (area->data1 * 256)
175 /* Slot Map (SM 534D90 */
176 else if (area->tag == VPD_SLOT_MAP) {
177 struct slot_map *slot_map;
179 if (slot_map_fmt == 0x1004)
180 slot_map = (struct slot_map *)((char *)area
181 + MFG_ENTRY_SIZE + 1);
183 slot_map = (struct slot_map *)((char *)area
185 iseries_parse_slot_area(slot_map, mfg_tag_len,
189 * Point to the next Mfg Area
190 * Use defined size, sizeof give wrong answer
192 area = (struct mfg_vpd_area *)((char *)area + mfg_tag_len
194 len -= (mfg_tag_len + MFG_ENTRY_SIZE);
199 * Look for "BUS".. Data is not Null terminated.
200 * PHBID of 0xFF indicates PHB was not found in VPD Data.
202 static u8 __init iseries_parse_phbid(u8 *area, int len)
205 if ((*area == 'B') && (*(area + 1) == 'U')
206 && (*(area + 2) == 'S')) {
219 * Parse out the VPD Areas
221 static void __init iseries_parse_vpd(u8 *data, int data_len,
222 HvAgentId agent, u8 *frame, char card[4])
226 while (data_len > 0) {
230 if (tag == VPD_END_OF_AREA)
232 len = *(data + 1) + (*(data + 2) * 256);
235 if (tag == VPD_ID_STRING)
236 phb = iseries_parse_phbid(data, len);
237 else if (tag == VPD_VENDOR_AREA)
238 iseries_parse_mfg_area((struct mfg_vpd_area *)data, len,
239 agent, &phb, frame, card);
240 /* Point to next Area. */
246 static int __init iseries_get_location_code(u16 bus, HvAgentId agent,
247 u8 *frame, char card[4])
251 u8 *bus_vpd = kmalloc(BUS_VPDSIZE, GFP_KERNEL);
253 if (bus_vpd == NULL) {
254 printk("PCI: Bus VPD Buffer allocation failure.\n");
257 bus_vpd_len = HvCallPci_getBusVpd(bus, iseries_hv_addr(bus_vpd),
259 if (bus_vpd_len == 0) {
260 printk("PCI: Bus VPD Buffer zero length.\n");
263 /* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */
264 /* Make sure this is what I think it is */
265 if (*bus_vpd != VPD_ID_STRING) {
266 printk("PCI: Bus VPD Buffer missing starting tag.\n");
269 iseries_parse_vpd(bus_vpd, bus_vpd_len, agent, frame, card);
277 * Prints the device information.
278 * - Pass in pci_dev* pointer to the device.
279 * - Pass in the device count
282 * PCI: Bus 0, Device 26, Vendor 0x12AE Frame 1, Card C10 Ethernet
285 static void __init iseries_device_information(struct pci_dev *pdev,
286 u16 bus, HvSubBusNumber subbus)
292 agent = ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus),
293 ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus));
295 if (iseries_get_location_code(bus, agent, &frame, card)) {
296 printk(KERN_INFO "PCI: %s, Vendor %04X Frame%3d, "
297 "Card %4s 0x%04X\n", pci_name(pdev), pdev->vendor,
298 frame, card, (int)(pdev->class >> 8));
303 * iomm_table_allocate_entry
305 * Adds pci_dev entry in address translation table
307 * - Allocates the number of entries required in table base on BAR
309 * - Allocates starting at BASE_IO_MEMORY and increases.
310 * - The size is round up to be a multiple of entry size.
311 * - CurrentIndex is incremented to keep track of the last entry.
312 * - Builds the resource entry for allocated BARs.
314 static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
316 struct resource *bar_res = &dev->resource[bar_num];
317 long bar_size = pci_resource_len(dev, bar_num);
320 * No space to allocate, quick exit, skip Allocation.
325 * Set Resource values.
327 spin_lock(&iomm_table_lock);
328 bar_res->start = BASE_IO_MEMORY +
329 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
330 bar_res->end = bar_res->start + bar_size - 1;
332 * Allocate the number of table entries needed for BAR.
334 while (bar_size > 0 ) {
335 iomm_table[current_iomm_table_entry] = dev->sysdata;
336 iobar_table[current_iomm_table_entry] = bar_num;
337 bar_size -= IOMM_TABLE_ENTRY_SIZE;
338 ++current_iomm_table_entry;
340 max_io_memory = BASE_IO_MEMORY +
341 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
342 spin_unlock(&iomm_table_lock);
346 * allocate_device_bars
348 * - Allocates ALL pci_dev BAR's and updates the resources with the
349 * BAR value. BARS with zero length will have the resources
350 * The HvCallPci_getBarParms is used to get the size of the BAR
351 * space. It calls iomm_table_allocate_entry to allocate
353 * - Loops through The Bar resources(0 - 5) including the ROM
356 static void __init allocate_device_bars(struct pci_dev *dev)
360 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
361 iomm_table_allocate_entry(dev, bar_num);
365 * Log error information to system console.
366 * Filter out the device not there errors.
367 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
368 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
369 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
371 static void pci_log_error(char *error, int bus, int subbus,
372 int agent, int hv_res)
374 if (hv_res == 0x0302)
376 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
377 error, bus, subbus, agent, hv_res);
381 * Look down the chain to find the matching Device Device
383 static struct device_node *find_device_node(int bus, int devfn)
385 struct device_node *node;
387 for (node = NULL; (node = of_find_all_nodes(node)); ) {
388 struct pci_dn *pdn = PCI_DN(node);
390 if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn))
397 * iSeries_pcibios_fixup_resources
399 * Fixes up all resources for devices
401 void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev)
405 unsigned char bus = pdev->bus->number;
406 struct device_node *node;
409 node = find_device_node(bus, pdev->devfn);
410 pr_debug("PCI: iSeries %s, pdev %p, node %p\n",
411 pci_name(pdev), pdev, node);
413 printk("PCI: %s disabled, device tree entry not found !\n",
415 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
416 pdev->resource[i].flags = 0;
419 sub_bus = of_get_property(node, "linux,subbus", NULL);
420 agent = of_get_property(node, "linux,agent-id", NULL);
421 if (agent && sub_bus) {
422 u8 irq = iSeries_allocate_IRQ(bus, 0, *sub_bus);
425 err = HvCallXm_connectBusUnit(bus, *sub_bus, *agent, irq);
427 pci_log_error("Connect Bus Unit",
428 bus, *sub_bus, *agent, err);
430 err = HvCallPci_configStore8(bus, *sub_bus,
431 *agent, PCI_INTERRUPT_LINE, irq);
433 pci_log_error("PciCfgStore Irq Failed!",
434 bus, *sub_bus, *agent, err);
440 pdev->sysdata = node;
441 allocate_device_bars(pdev);
442 iseries_device_information(pdev, bus, *sub_bus);
443 iommu_devnode_init_iSeries(pdev, node);
447 * iSeries_pci_final_fixup(void)
449 void __init iSeries_pci_final_fixup(void)
451 /* Fix up at the device node and pci_dev relationship */
452 mf_display_src(0xC9000100);
453 iSeries_activate_IRQs();
454 mf_display_src(0xC9000200);
458 * Config space read and write functions.
459 * For now at least, we look for the device node for the bus and devfn
460 * that we are asked to access. It may be possible to translate the devfn
461 * to a subbus and deviceid more directly.
463 static u64 hv_cfg_read_func[4] = {
464 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
465 HvCallPciConfigLoad32, HvCallPciConfigLoad32
468 static u64 hv_cfg_write_func[4] = {
469 HvCallPciConfigStore8, HvCallPciConfigStore16,
470 HvCallPciConfigStore32, HvCallPciConfigStore32
474 * Read PCI config space
476 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
477 int offset, int size, u32 *val)
479 struct device_node *node = find_device_node(bus->number, devfn);
481 struct HvCallPci_LoadReturn ret;
484 return PCIBIOS_DEVICE_NOT_FOUND;
487 return PCIBIOS_BAD_REGISTER_NUMBER;
490 fn = hv_cfg_read_func[(size - 1) & 3];
491 HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
495 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
503 * Write PCI config space
506 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
507 int offset, int size, u32 val)
509 struct device_node *node = find_device_node(bus->number, devfn);
514 return PCIBIOS_DEVICE_NOT_FOUND;
516 return PCIBIOS_BAD_REGISTER_NUMBER;
518 fn = hv_cfg_write_func[(size - 1) & 3];
519 ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
522 return PCIBIOS_DEVICE_NOT_FOUND;
527 static struct pci_ops iSeries_pci_ops = {
528 .read = iSeries_pci_read_config,
529 .write = iSeries_pci_write_config
534 * -> On Failure, print and log information.
535 * Increment Retry Count, if exceeds max, panic partition.
537 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
538 * PCI: Device 23.90 ReadL Retry( 1)
539 * PCI: Device 23.90 ReadL Retry Successful(1)
541 static int check_return_code(char *type, struct device_node *dn,
545 struct pci_dn *pdn = PCI_DN(dn);
548 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
549 type, pdn->busno, pdn->devfn,
552 * Bump the retry and check for retry count exceeded.
553 * If, Exceeded, panic the system.
555 if (((*retry) > PCI_RETRY_MAX) &&
556 (limit_pci_retries > 0)) {
557 mf_display_src(0xB6000103);
559 panic("PCI: Hardware I/O Error, SRC B6000103, "
560 "Automatic Reboot Disabled.\n");
562 return -1; /* Retry Try */
568 * Translate the I/O Address into a device node, bar, and bar offset.
569 * Note: Make sure the passed variable end up on the stack to avoid
570 * the exposure of being device global.
572 static inline struct device_node *xlate_iomm_address(
573 const volatile void __iomem *addr,
574 u64 *dsaptr, u64 *bar_offset, const char *func)
576 unsigned long orig_addr;
577 unsigned long base_addr;
579 struct device_node *dn;
581 orig_addr = (unsigned long __force)addr;
582 if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) {
583 static unsigned long last_jiffies;
584 static int num_printed;
586 if ((jiffies - last_jiffies) > 60 * HZ) {
587 last_jiffies = jiffies;
590 if (num_printed++ < 10)
592 "iSeries_%s: invalid access at IO address %p\n",
596 base_addr = orig_addr - BASE_IO_MEMORY;
597 ind = base_addr / IOMM_TABLE_ENTRY_SIZE;
598 dn = iomm_table[ind];
601 int barnum = iobar_table[ind];
602 *dsaptr = iseries_ds_addr(dn) | (barnum << 24);
603 *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE;
605 panic("PCI: Invalid PCI IO address detected!\n");
610 * Read MM I/O Instructions for the iSeries
611 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
612 * else, data is returned in Big Endian format.
614 static u8 iseries_readb(const volatile void __iomem *addr)
619 struct HvCallPci_LoadReturn ret;
620 struct device_node *dn =
621 xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte");
626 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0);
627 } while (check_return_code("RDB", dn, &retry, ret.rc) != 0);
632 static u16 iseries_readw_be(const volatile void __iomem *addr)
637 struct HvCallPci_LoadReturn ret;
638 struct device_node *dn =
639 xlate_iomm_address(addr, &dsa, &bar_offset, "read_word");
644 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
646 } while (check_return_code("RDW", dn, &retry, ret.rc) != 0);
651 static u32 iseries_readl_be(const volatile void __iomem *addr)
656 struct HvCallPci_LoadReturn ret;
657 struct device_node *dn =
658 xlate_iomm_address(addr, &dsa, &bar_offset, "read_long");
663 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
665 } while (check_return_code("RDL", dn, &retry, ret.rc) != 0);
671 * Write MM I/O Instructions for the iSeries
674 static void iseries_writeb(u8 data, volatile void __iomem *addr)
680 struct device_node *dn =
681 xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte");
686 rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0);
687 } while (check_return_code("WWB", dn, &retry, rc) != 0);
690 static void iseries_writew_be(u16 data, volatile void __iomem *addr)
696 struct device_node *dn =
697 xlate_iomm_address(addr, &dsa, &bar_offset, "write_word");
702 rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0);
703 } while (check_return_code("WWW", dn, &retry, rc) != 0);
706 static void iseries_writel_be(u32 data, volatile void __iomem *addr)
712 struct device_node *dn =
713 xlate_iomm_address(addr, &dsa, &bar_offset, "write_long");
718 rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0);
719 } while (check_return_code("WWL", dn, &retry, rc) != 0);
722 static u16 iseries_readw(const volatile void __iomem *addr)
724 return le16_to_cpu(iseries_readw_be(addr));
727 static u32 iseries_readl(const volatile void __iomem *addr)
729 return le32_to_cpu(iseries_readl_be(addr));
732 static void iseries_writew(u16 data, volatile void __iomem *addr)
734 iseries_writew_be(cpu_to_le16(data), addr);
737 static void iseries_writel(u32 data, volatile void __iomem *addr)
739 iseries_writel(cpu_to_le32(data), addr);
742 static void iseries_readsb(const volatile void __iomem *addr, void *buf,
747 *(dst++) = iseries_readb(addr);
750 static void iseries_readsw(const volatile void __iomem *addr, void *buf,
755 *(dst++) = iseries_readw_be(addr);
758 static void iseries_readsl(const volatile void __iomem *addr, void *buf,
763 *(dst++) = iseries_readl_be(addr);
766 static void iseries_writesb(volatile void __iomem *addr, const void *buf,
771 iseries_writeb(*(src++), addr);
774 static void iseries_writesw(volatile void __iomem *addr, const void *buf,
777 const u16 *src = buf;
779 iseries_writew_be(*(src++), addr);
782 static void iseries_writesl(volatile void __iomem *addr, const void *buf,
785 const u32 *src = buf;
787 iseries_writel_be(*(src++), addr);
790 static void iseries_memset_io(volatile void __iomem *addr, int c,
793 volatile char __iomem *d = addr;
796 iseries_writeb(c, d++);
799 static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src,
803 const volatile char __iomem *s = src;
806 *d++ = iseries_readb(s++);
809 static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src,
813 volatile char __iomem *d = dest;
816 iseries_writeb(*s++, d++);
819 /* We only set MMIO ops. The default PIO ops will be default
820 * to the MMIO ops + pci_io_base which is 0 on iSeries as
821 * expected so both should work.
823 * Note that we don't implement the readq/writeq versions as
824 * I don't know of an HV call for doing so. Thus, the default
825 * operation will be used instead, which will fault a the value
826 * return by iSeries for MMIO addresses always hits a non mapped
827 * area. This is as good as the BUG() we used to have there.
829 static struct ppc_pci_io __initdata iseries_pci_io = {
830 .readb = iseries_readb,
831 .readw = iseries_readw,
832 .readl = iseries_readl,
833 .readw_be = iseries_readw_be,
834 .readl_be = iseries_readl_be,
835 .writeb = iseries_writeb,
836 .writew = iseries_writew,
837 .writel = iseries_writel,
838 .writew_be = iseries_writew_be,
839 .writel_be = iseries_writel_be,
840 .readsb = iseries_readsb,
841 .readsw = iseries_readsw,
842 .readsl = iseries_readsl,
843 .writesb = iseries_writesb,
844 .writesw = iseries_writesw,
845 .writesl = iseries_writesl,
846 .memset_io = iseries_memset_io,
847 .memcpy_fromio = iseries_memcpy_fromio,
848 .memcpy_toio = iseries_memcpy_toio,
852 * iSeries_pcibios_init
855 * This function checks for all possible system PCI host bridges that connect
856 * PCI buses. The system hypervisor is queried as to the guest partition
857 * ownership status. A pci_controller is built for any bus which is partially
858 * owned or fully owned by this guest partition.
860 void __init iSeries_pcibios_init(void)
862 struct pci_controller *phb;
863 struct device_node *root = of_find_node_by_path("/");
864 struct device_node *node = NULL;
866 /* Install IO hooks */
867 ppc_pci_io = iseries_pci_io;
871 /* iSeries has no IO space in the common sense, it needs to set
877 printk(KERN_CRIT "iSeries_pcibios_init: can't find root "
881 while ((node = of_get_next_child(root, node)) != NULL) {
885 if ((node->type == NULL) || (strcmp(node->type, "pci") != 0))
888 busp = of_get_property(node, "bus-range", NULL);
892 printk("bus %d appears to exist\n", bus);
893 phb = pcibios_alloc_controller(node);
896 /* All legacy iSeries PHBs are in domain zero */
897 phb->global_number = 0;
899 phb->first_busno = bus;
900 phb->last_busno = bus;
901 phb->ops = &iSeries_pci_ops;
902 phb->io_base_virt = (void __iomem *)_IO_BASE;
903 phb->io_resource.flags = IORESOURCE_IO;
904 phb->io_resource.start = BASE_IO_MEMORY;
905 phb->io_resource.end = END_IO_MEMORY;
906 phb->io_resource.name = "iSeries PCI IO";
907 phb->mem_resources[0].flags = IORESOURCE_MEM;
908 phb->mem_resources[0].start = BASE_IO_MEMORY;
909 phb->mem_resources[0].end = END_IO_MEMORY;
910 phb->mem_resources[0].name = "Series PCI MEM";