2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
4 * iSeries specific routines for PCI.
6 * Based on code from pci.c and iSeries_pci.c 32bit
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
32 #include <asm/machdep.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/iommu.h>
35 #include <asm/abs_addr.h>
36 #include <asm/firmware.h>
38 #include <asm/iseries/hv_call_xm.h>
39 #include <asm/iseries/mf.h>
40 #include <asm/iseries/iommu.h>
42 #include <asm/ppc-pci.h>
48 #define PCI_RETRY_MAX 3
49 static int limit_pci_retries = 1; /* Set Retry Error on. */
53 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
55 #define IOMM_TABLE_MAX_ENTRIES 1024
56 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
57 #define BASE_IO_MEMORY 0xE000000000000000UL
59 static unsigned long max_io_memory = BASE_IO_MEMORY;
60 static long current_iomm_table_entry;
65 static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
66 static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES];
68 static const char pci_io_text[] = "iSeries PCI I/O";
69 static DEFINE_SPINLOCK(iomm_table_lock);
72 * iomm_table_allocate_entry
74 * Adds pci_dev entry in address translation table
76 * - Allocates the number of entries required in table base on BAR
78 * - Allocates starting at BASE_IO_MEMORY and increases.
79 * - The size is round up to be a multiple of entry size.
80 * - CurrentIndex is incremented to keep track of the last entry.
81 * - Builds the resource entry for allocated BARs.
83 static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
85 struct resource *bar_res = &dev->resource[bar_num];
86 long bar_size = pci_resource_len(dev, bar_num);
89 * No space to allocate, quick exit, skip Allocation.
94 * Set Resource values.
96 spin_lock(&iomm_table_lock);
97 bar_res->name = pci_io_text;
98 bar_res->start = BASE_IO_MEMORY +
99 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
100 bar_res->end = bar_res->start + bar_size - 1;
102 * Allocate the number of table entries needed for BAR.
104 while (bar_size > 0 ) {
105 iomm_table[current_iomm_table_entry] = dev->sysdata;
106 iobar_table[current_iomm_table_entry] = bar_num;
107 bar_size -= IOMM_TABLE_ENTRY_SIZE;
108 ++current_iomm_table_entry;
110 max_io_memory = BASE_IO_MEMORY +
111 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
112 spin_unlock(&iomm_table_lock);
116 * allocate_device_bars
118 * - Allocates ALL pci_dev BAR's and updates the resources with the
119 * BAR value. BARS with zero length will have the resources
120 * The HvCallPci_getBarParms is used to get the size of the BAR
121 * space. It calls iomm_table_allocate_entry to allocate
123 * - Loops through The Bar resources(0 - 5) including the ROM
126 static void __init allocate_device_bars(struct pci_dev *dev)
130 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
131 iomm_table_allocate_entry(dev, bar_num);
135 * Log error information to system console.
136 * Filter out the device not there errors.
137 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
138 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
139 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
141 static void pci_log_error(char *error, int bus, int subbus,
142 int agent, int hv_res)
144 if (hv_res == 0x0302)
146 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
147 error, bus, subbus, agent, hv_res);
151 * Look down the chain to find the matching Device Device
153 static struct device_node *find_device_node(int bus, int devfn)
155 struct device_node *node;
157 for (node = NULL; (node = of_find_all_nodes(node)); ) {
158 struct pci_dn *pdn = PCI_DN(node);
160 if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn))
167 * iSeries_pci_final_fixup(void)
169 void __init iSeries_pci_final_fixup(void)
171 struct pci_dev *pdev = NULL;
172 struct device_node *node;
175 /* Fix up at the device node and pci_dev relationship */
176 mf_display_src(0xC9000100);
178 printk("pcibios_final_fixup\n");
179 for_each_pci_dev(pdev) {
183 node = find_device_node(pdev->bus->number, pdev->devfn);
184 printk("pci dev %p (%x.%x), node %p\n", pdev,
185 pdev->bus->number, pdev->devfn, node);
187 printk("PCI: Device Tree not found for 0x%016lX\n",
188 (unsigned long)pdev);
193 agent = of_get_property(node, "linux,agent-id", NULL);
195 u8 irq = iSeries_allocate_IRQ(pdn->busno, 0,
199 err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno,
202 pci_log_error("Connect Bus Unit",
203 pdn->busno, pdn->bussubno, *agent, err);
205 err = HvCallPci_configStore8(pdn->busno,
206 pdn->bussubno, *agent,
207 PCI_INTERRUPT_LINE, irq);
209 pci_log_error("PciCfgStore Irq Failed!",
210 pdn->busno, pdn->bussubno,
218 pdev->sysdata = node;
219 PCI_DN(node)->pcidev = pdev;
220 allocate_device_bars(pdev);
221 iSeries_Device_Information(pdev, num_dev);
222 iommu_devnode_init_iSeries(pdev, node);
224 iSeries_activate_IRQs();
225 mf_display_src(0xC9000200);
229 * Config space read and write functions.
230 * For now at least, we look for the device node for the bus and devfn
231 * that we are asked to access. It may be possible to translate the devfn
232 * to a subbus and deviceid more directly.
234 static u64 hv_cfg_read_func[4] = {
235 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
236 HvCallPciConfigLoad32, HvCallPciConfigLoad32
239 static u64 hv_cfg_write_func[4] = {
240 HvCallPciConfigStore8, HvCallPciConfigStore16,
241 HvCallPciConfigStore32, HvCallPciConfigStore32
245 * Read PCI config space
247 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
248 int offset, int size, u32 *val)
250 struct device_node *node = find_device_node(bus->number, devfn);
252 struct HvCallPci_LoadReturn ret;
255 return PCIBIOS_DEVICE_NOT_FOUND;
258 return PCIBIOS_BAD_REGISTER_NUMBER;
261 fn = hv_cfg_read_func[(size - 1) & 3];
262 HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
266 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
274 * Write PCI config space
277 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
278 int offset, int size, u32 val)
280 struct device_node *node = find_device_node(bus->number, devfn);
285 return PCIBIOS_DEVICE_NOT_FOUND;
287 return PCIBIOS_BAD_REGISTER_NUMBER;
289 fn = hv_cfg_write_func[(size - 1) & 3];
290 ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
293 return PCIBIOS_DEVICE_NOT_FOUND;
298 static struct pci_ops iSeries_pci_ops = {
299 .read = iSeries_pci_read_config,
300 .write = iSeries_pci_write_config
305 * -> On Failure, print and log information.
306 * Increment Retry Count, if exceeds max, panic partition.
308 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
309 * PCI: Device 23.90 ReadL Retry( 1)
310 * PCI: Device 23.90 ReadL Retry Successful(1)
312 static int check_return_code(char *type, struct device_node *dn,
316 struct pci_dn *pdn = PCI_DN(dn);
319 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
320 type, pdn->busno, pdn->devfn,
323 * Bump the retry and check for retry count exceeded.
324 * If, Exceeded, panic the system.
326 if (((*retry) > PCI_RETRY_MAX) &&
327 (limit_pci_retries > 0)) {
328 mf_display_src(0xB6000103);
330 panic("PCI: Hardware I/O Error, SRC B6000103, "
331 "Automatic Reboot Disabled.\n");
333 return -1; /* Retry Try */
339 * Translate the I/O Address into a device node, bar, and bar offset.
340 * Note: Make sure the passed variable end up on the stack to avoid
341 * the exposure of being device global.
343 static inline struct device_node *xlate_iomm_address(
344 const volatile void __iomem *addr,
345 u64 *dsaptr, u64 *bar_offset, const char *func)
347 unsigned long orig_addr;
348 unsigned long base_addr;
350 struct device_node *dn;
352 orig_addr = (unsigned long __force)addr;
353 if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) {
354 static unsigned long last_jiffies;
355 static int num_printed;
357 if ((jiffies - last_jiffies) > 60 * HZ) {
358 last_jiffies = jiffies;
361 if (num_printed++ < 10)
363 "iSeries_%s: invalid access at IO address %p\n",
367 base_addr = orig_addr - BASE_IO_MEMORY;
368 ind = base_addr / IOMM_TABLE_ENTRY_SIZE;
369 dn = iomm_table[ind];
372 int barnum = iobar_table[ind];
373 *dsaptr = iseries_ds_addr(dn) | (barnum << 24);
374 *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE;
376 panic("PCI: Invalid PCI IO address detected!\n");
381 * Read MM I/O Instructions for the iSeries
382 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
383 * else, data is returned in Big Endian format.
385 static u8 iSeries_read_byte(const volatile void __iomem *addr)
390 struct HvCallPci_LoadReturn ret;
391 struct device_node *dn =
392 xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte");
397 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0);
398 } while (check_return_code("RDB", dn, &retry, ret.rc) != 0);
403 static u16 iSeries_read_word(const volatile void __iomem *addr)
408 struct HvCallPci_LoadReturn ret;
409 struct device_node *dn =
410 xlate_iomm_address(addr, &dsa, &bar_offset, "read_word");
415 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
417 } while (check_return_code("RDW", dn, &retry, ret.rc) != 0);
422 static u32 iSeries_read_long(const volatile void __iomem *addr)
427 struct HvCallPci_LoadReturn ret;
428 struct device_node *dn =
429 xlate_iomm_address(addr, &dsa, &bar_offset, "read_long");
434 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
436 } while (check_return_code("RDL", dn, &retry, ret.rc) != 0);
442 * Write MM I/O Instructions for the iSeries
445 static void iSeries_write_byte(u8 data, volatile void __iomem *addr)
451 struct device_node *dn =
452 xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte");
457 rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0);
458 } while (check_return_code("WWB", dn, &retry, rc) != 0);
461 static void iSeries_write_word(u16 data, volatile void __iomem *addr)
467 struct device_node *dn =
468 xlate_iomm_address(addr, &dsa, &bar_offset, "write_word");
473 rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0);
474 } while (check_return_code("WWW", dn, &retry, rc) != 0);
477 static void iSeries_write_long(u32 data, volatile void __iomem *addr)
483 struct device_node *dn =
484 xlate_iomm_address(addr, &dsa, &bar_offset, "write_long");
489 rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0);
490 } while (check_return_code("WWL", dn, &retry, rc) != 0);
493 static u8 iseries_readb(const volatile void __iomem *addr)
495 return iSeries_read_byte(addr);
498 static u16 iseries_readw(const volatile void __iomem *addr)
500 return le16_to_cpu(iSeries_read_word(addr));
503 static u32 iseries_readl(const volatile void __iomem *addr)
505 return le32_to_cpu(iSeries_read_long(addr));
508 static u16 iseries_readw_be(const volatile void __iomem *addr)
510 return iSeries_read_word(addr);
513 static u32 iseries_readl_be(const volatile void __iomem *addr)
515 return iSeries_read_long(addr);
518 static void iseries_writeb(u8 data, volatile void __iomem *addr)
520 iSeries_write_byte(data, addr);
523 static void iseries_writew(u16 data, volatile void __iomem *addr)
525 iSeries_write_word(cpu_to_le16(data), addr);
528 static void iseries_writel(u32 data, volatile void __iomem *addr)
530 iSeries_write_long(cpu_to_le32(data), addr);
533 static void iseries_writew_be(u16 data, volatile void __iomem *addr)
535 iSeries_write_word(data, addr);
538 static void iseries_writel_be(u32 data, volatile void __iomem *addr)
540 iSeries_write_long(data, addr);
543 static void iseries_readsb(const volatile void __iomem *addr, void *buf,
548 *(dst++) = iSeries_read_byte(addr);
551 static void iseries_readsw(const volatile void __iomem *addr, void *buf,
556 *(dst++) = iSeries_read_word(addr);
559 static void iseries_readsl(const volatile void __iomem *addr, void *buf,
564 *(dst++) = iSeries_read_long(addr);
567 static void iseries_writesb(volatile void __iomem *addr, const void *buf,
572 iSeries_write_byte(*(src++), addr);
575 static void iseries_writesw(volatile void __iomem *addr, const void *buf,
578 const u16 *src = buf;
580 iSeries_write_word(*(src++), addr);
583 static void iseries_writesl(volatile void __iomem *addr, const void *buf,
586 const u32 *src = buf;
588 iSeries_write_long(*(src++), addr);
591 static void iseries_memset_io(volatile void __iomem *addr, int c,
594 volatile char __iomem *d = addr;
597 iSeries_write_byte(c, d++);
600 static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src,
604 const volatile char __iomem *s = src;
607 *d++ = iSeries_read_byte(s++);
610 static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src,
614 volatile char __iomem *d = dest;
617 iSeries_write_byte(*s++, d++);
620 /* We only set MMIO ops. The default PIO ops will be default
621 * to the MMIO ops + pci_io_base which is 0 on iSeries as
622 * expected so both should work.
624 * Note that we don't implement the readq/writeq versions as
625 * I don't know of an HV call for doing so. Thus, the default
626 * operation will be used instead, which will fault a the value
627 * return by iSeries for MMIO addresses always hits a non mapped
628 * area. This is as good as the BUG() we used to have there.
630 static struct ppc_pci_io __initdata iseries_pci_io = {
631 .readb = iseries_readb,
632 .readw = iseries_readw,
633 .readl = iseries_readl,
634 .readw_be = iseries_readw_be,
635 .readl_be = iseries_readl_be,
636 .writeb = iseries_writeb,
637 .writew = iseries_writew,
638 .writel = iseries_writel,
639 .writew_be = iseries_writew_be,
640 .writel_be = iseries_writel_be,
641 .readsb = iseries_readsb,
642 .readsw = iseries_readsw,
643 .readsl = iseries_readsl,
644 .writesb = iseries_writesb,
645 .writesw = iseries_writesw,
646 .writesl = iseries_writesl,
647 .memset_io = iseries_memset_io,
648 .memcpy_fromio = iseries_memcpy_fromio,
649 .memcpy_toio = iseries_memcpy_toio,
653 * iSeries_pcibios_init
656 * This function checks for all possible system PCI host bridges that connect
657 * PCI buses. The system hypervisor is queried as to the guest partition
658 * ownership status. A pci_controller is built for any bus which is partially
659 * owned or fully owned by this guest partition.
661 void __init iSeries_pcibios_init(void)
663 struct pci_controller *phb;
664 struct device_node *root = of_find_node_by_path("/");
665 struct device_node *node = NULL;
667 /* Install IO hooks */
668 ppc_pci_io = iseries_pci_io;
670 /* iSeries has no IO space in the common sense, it needs to set
676 printk(KERN_CRIT "iSeries_pcibios_init: can't find root "
680 while ((node = of_get_next_child(root, node)) != NULL) {
684 if ((node->type == NULL) || (strcmp(node->type, "pci") != 0))
687 busp = of_get_property(node, "bus-range", NULL);
691 printk("bus %d appears to exist\n", bus);
692 phb = pcibios_alloc_controller(node);
696 phb->pci_mem_offset = bus;
697 phb->first_busno = bus;
698 phb->last_busno = bus;
699 phb->ops = &iSeries_pci_ops;