arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/sched.h>
  38 #include <linux/kernel.h>
  39 #include <linux/mm.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/smp.h>
  42 #include <linux/stddef.h>
  43 #include <linux/unistd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/spu.h>
  47 #include <asm/spu_priv1.h>
  48 #include <asm/spu_csa.h>
  49 #include <asm/mmu_context.h>
  50
  51 #include "spu_save_dump.h"
  52 #include "spu_restore_dump.h"
  53
  54 #if 0
  55 #define POLL_WHILE_TRUE(_c) {                           \
  56     do {                                                \
  57     } while (_c);                                       \
  58   }
  59 #else
  60 #define RELAX_SPIN_COUNT                                1000
  61 #define POLL_WHILE_TRUE(_c) {                           \
  62     do {                                                \
  63         int _i;                                         \
  64         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  65             cpu_relax();                                \
  66         }                                               \
  67         if (unlikely(_c)) yield();                      \
  68         else break;                                     \
  69     } while (_c);                                       \
  70   }
  71 #endif                          /* debug */
  72
  73 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  74
  75 static inline void acquire_spu_lock(struct spu *spu)
  76 {
  77         /* Save, Step 1:
  78          * Restore, Step 1:
  79          *    Acquire SPU-specific mutual exclusion lock.
  80          *    TBD.
  81          */
  82 }
  83
  84 static inline void release_spu_lock(struct spu *spu)
  85 {
  86         /* Restore, Step 76:
  87          *    Release SPU-specific mutual exclusion lock.
  88          *    TBD.
  89          */
  90 }
  91
  92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  93 {
  94         struct spu_problem __iomem *prob = spu->problem;
  95         u32 isolate_state;
  96
  97         /* Save, Step 2:
  98          * Save, Step 6:
  99          *     If SPU_Status[E,L,IS] any field is '1', this
 100          *     SPU is in isolate state and cannot be context
 101          *     saved at this time.
 102          */
 103         isolate_state = SPU_STATUS_ISOLATED_STATE |
 104             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 105         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 106 }
 107
 108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 109 {
 110         /* Save, Step 3:
 111          * Restore, Step 2:
 112          *     Save INT_Mask_class0 in CSA.
 113          *     Write INT_MASK_class0 with value of 0.
 114          *     Save INT_Mask_class1 in CSA.
 115          *     Write INT_MASK_class1 with value of 0.
 116          *     Save INT_Mask_class2 in CSA.
 117          *     Write INT_MASK_class2 with value of 0.
 118          */
 119         spin_lock_irq(&spu->register_lock);
 120         if (csa) {
 121                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 122                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 123                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 124         }
 125         spu_int_mask_set(spu, 0, 0ul);
 126         spu_int_mask_set(spu, 1, 0ul);
 127         spu_int_mask_set(spu, 2, 0ul);
 128         eieio();
 129         spin_unlock_irq(&spu->register_lock);
 130 }
 131
 132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 133 {
 134         /* Save, Step 4:
 135          * Restore, Step 25.
 136          *    Set a software watchdog timer, which specifies the
 137          *    maximum allowable time for a context save sequence.
 138          *
 139          *    For present, this implementation will not set a global
 140          *    watchdog timer, as virtualization & variable system load
 141          *    may cause unpredictable execution times.
 142          */
 143 }
 144
 145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 146 {
 147         /* Save, Step 5:
 148          * Restore, Step 3:
 149          *     Inhibit user-space access (if provided) to this
 150          *     SPU by unmapping the virtual pages assigned to
 151          *     the SPU memory-mapped I/O (MMIO) for problem
 152          *     state. TBD.
 153          */
 154 }
 155
 156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 157 {
 158         /* Save, Step 7:
 159          * Restore, Step 5:
 160          *     Set a software context switch pending flag.
 161          */
 162         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 163         mb();
 164 }
 165
 166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 167 {
 168         struct spu_priv2 __iomem *priv2 = spu->priv2;
 169
 170         /* Save, Step 8:
 171          *     Suspend DMA and save MFC_CNTL.
 172          */
 173         switch (in_be64(&priv2->mfc_control_RW) &
 174                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 175         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 176                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 177                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 178                                  MFC_CNTL_SUSPEND_COMPLETE);
 179                 /* fall through */
 180         case MFC_CNTL_SUSPEND_COMPLETE:
 181                 if (csa) {
 182                         csa->priv2.mfc_control_RW =
 183                                 in_be64(&priv2->mfc_control_RW) |
 184                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 185                 }
 186                 break;
 187         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 188                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 189                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 190                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 191                                  MFC_CNTL_SUSPEND_COMPLETE);
 192                 if (csa) {
 193                         csa->priv2.mfc_control_RW =
 194                                 in_be64(&priv2->mfc_control_RW) &
 195                                 ~MFC_CNTL_SUSPEND_DMA_QUEUE;
 196                 }
 197                 break;
 198         }
 199 }
 200
 201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 202 {
 203         struct spu_problem __iomem *prob = spu->problem;
 204
 205         /* Save, Step 9:
 206          *     Save SPU_Runcntl in the CSA.  This value contains
 207          *     the "Application Desired State".
 208          */
 209         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 210 }
 211
 212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 213 {
 214         /* Save, Step 10:
 215          *     Save MFC_SR1 in the CSA.
 216          */
 217         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 218 }
 219
 220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 221 {
 222         struct spu_problem __iomem *prob = spu->problem;
 223
 224         /* Save, Step 11:
 225          *     Read SPU_Status[R], and save to CSA.
 226          */
 227         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 228                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 229         } else {
 230                 u32 stopped;
 231
 232                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 233                 eieio();
 234                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 235                                 SPU_STATUS_RUNNING);
 236                 stopped =
 237                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 238                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 239                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 240                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 241                 else
 242                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 243         }
 244 }
 245
 246 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 247 {
 248         struct spu_priv2 __iomem *priv2 = spu->priv2;
 249
 250         /* Save, Step 12:
 251          *     Read MFC_CNTL[Ds].  Update saved copy of
 252          *     CSA.MFC_CNTL[Ds].
 253          */
 254         if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
 255                 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
 256                 csa->suspend_time = get_cycles();
 257                 out_be64(&priv2->spu_chnlcntptr_RW, 7ULL);
 258                 eieio();
 259                 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
 260                 eieio();
 261         } else {
 262                 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
 263         }
 264 }
 265
 266 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 267 {
 268         struct spu_priv2 __iomem *priv2 = spu->priv2;
 269
 270         /* Save, Step 13:
 271          *     Write MFC_CNTL[Dh] set to a '1' to halt
 272          *     the decrementer.
 273          */
 274         out_be64(&priv2->mfc_control_RW,
 275                  MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
 276         eieio();
 277 }
 278
 279 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 280 {
 281         /* Save, Step 14:
 282          *    Read PPE Timebase High and Timebase low registers
 283          *    and save in CSA.  TBD.
 284          */
 285         csa->suspend_time = get_cycles();
 286 }
 287
 288 static inline void remove_other_spu_access(struct spu_state *csa,
 289                                            struct spu *spu)
 290 {
 291         /* Save, Step 15:
 292          *     Remove other SPU access to this SPU by unmapping
 293          *     this SPU's pages from their address space.  TBD.
 294          */
 295 }
 296
 297 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 298 {
 299         struct spu_problem __iomem *prob = spu->problem;
 300
 301         /* Save, Step 16:
 302          * Restore, Step 11.
 303          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 304          *     for a value of 0.
 305          */
 306         out_be64(&prob->spc_mssync_RW, 1UL);
 307         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 308 }
 309
 310 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 311 {
 312         /* Save, Step 17:
 313          * Restore, Step 12.
 314          * Restore, Step 48.
 315          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 316          *     Then issue a PPE sync instruction.
 317          */
 318         spu_tlb_invalidate(spu);
 319         mb();
 320 }
 321
 322 static inline void handle_pending_interrupts(struct spu_state *csa,
 323                                              struct spu *spu)
 324 {
 325         /* Save, Step 18:
 326          *     Handle any pending interrupts from this SPU
 327          *     here.  This is OS or hypervisor specific.  One
 328          *     option is to re-enable interrupts to handle any
 329          *     pending interrupts, with the interrupt handlers
 330          *     recognizing the software Context Switch Pending
 331          *     flag, to ensure the SPU execution or MFC command
 332          *     queue is not restarted.  TBD.
 333          */
 334 }
 335
 336 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 337 {
 338         struct spu_priv2 __iomem *priv2 = spu->priv2;
 339         int i;
 340
 341         /* Save, Step 19:
 342          *     If MFC_Cntl[Se]=0 then save
 343          *     MFC command queues.
 344          */
 345         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 346                 for (i = 0; i < 8; i++) {
 347                         csa->priv2.puq[i].mfc_cq_data0_RW =
 348                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 349                         csa->priv2.puq[i].mfc_cq_data1_RW =
 350                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 351                         csa->priv2.puq[i].mfc_cq_data2_RW =
 352                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 353                         csa->priv2.puq[i].mfc_cq_data3_RW =
 354                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 355                 }
 356                 for (i = 0; i < 16; i++) {
 357                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 358                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 359                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 360                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 361                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 362                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 363                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 364                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 365                 }
 366         }
 367 }
 368
 369 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 370 {
 371         struct spu_problem __iomem *prob = spu->problem;
 372
 373         /* Save, Step 20:
 374          *     Save the PPU_QueryMask register
 375          *     in the CSA.
 376          */
 377         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 378 }
 379
 380 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 381 {
 382         struct spu_problem __iomem *prob = spu->problem;
 383
 384         /* Save, Step 21:
 385          *     Save the PPU_QueryType register
 386          *     in the CSA.
 387          */
 388         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 389 }
 390
 391 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
 392 {
 393         struct spu_problem __iomem *prob = spu->problem;
 394
 395         /* Save the Prxy_TagStatus register in the CSA.
 396          *
 397          * It is unnecessary to restore dma_tagstatus_R, however,
 398          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
 399          * we must save it.
 400          */
 401         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
 402 }
 403
 404 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 405 {
 406         struct spu_priv2 __iomem *priv2 = spu->priv2;
 407
 408         /* Save, Step 22:
 409          *     Save the MFC_CSR_TSQ register
 410          *     in the LSCSA.
 411          */
 412         csa->priv2.spu_tag_status_query_RW =
 413             in_be64(&priv2->spu_tag_status_query_RW);
 414 }
 415
 416 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 417 {
 418         struct spu_priv2 __iomem *priv2 = spu->priv2;
 419
 420         /* Save, Step 23:
 421          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 422          *     registers in the CSA.
 423          */
 424         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 425         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 426 }
 427
 428 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 429 {
 430         struct spu_priv2 __iomem *priv2 = spu->priv2;
 431
 432         /* Save, Step 24:
 433          *     Save the MFC_CSR_ATO register in
 434          *     the CSA.
 435          */
 436         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 437 }
 438
 439 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 440 {
 441         /* Save, Step 25:
 442          *     Save the MFC_TCLASS_ID register in
 443          *     the CSA.
 444          */
 445         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 446 }
 447
 448 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 449 {
 450         /* Save, Step 26:
 451          * Restore, Step 23.
 452          *     Write the MFC_TCLASS_ID register with
 453          *     the value 0x10000000.
 454          */
 455         spu_mfc_tclass_id_set(spu, 0x10000000);
 456         eieio();
 457 }
 458
 459 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 460 {
 461         struct spu_priv2 __iomem *priv2 = spu->priv2;
 462
 463         /* Save, Step 27:
 464          * Restore, Step 14.
 465          *     Write MFC_CNTL[Pc]=1 (purge queue).
 466          */
 467         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
 468         eieio();
 469 }
 470
 471 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 472 {
 473         struct spu_priv2 __iomem *priv2 = spu->priv2;
 474
 475         /* Save, Step 28:
 476          *     Poll MFC_CNTL[Ps] until value '11' is read
 477          *     (purge complete).
 478          */
 479         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 480                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 481                          MFC_CNTL_PURGE_DMA_COMPLETE);
 482 }
 483
 484 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 485 {
 486         /* Save, Step 30:
 487          * Restore, Step 18:
 488          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 489          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 490          *     OS specific environment.
 491          *
 492          *     Implementation note: The SPU-side code
 493          *     for save/restore is privileged, so the
 494          *     MFC_SR1[Pr] bit is not set.
 495          *
 496          */
 497         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 498                               MFC_STATE1_RELOCATE_MASK |
 499                               MFC_STATE1_BUS_TLBIE_MASK));
 500 }
 501
 502 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 503 {
 504         struct spu_problem __iomem *prob = spu->problem;
 505
 506         /* Save, Step 31:
 507          *     Save SPU_NPC in the CSA.
 508          */
 509         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 510 }
 511
 512 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 513 {
 514         struct spu_priv2 __iomem *priv2 = spu->priv2;
 515
 516         /* Save, Step 32:
 517          *     Save SPU_PrivCntl in the CSA.
 518          */
 519         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 520 }
 521
 522 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 523 {
 524         struct spu_priv2 __iomem *priv2 = spu->priv2;
 525
 526         /* Save, Step 33:
 527          * Restore, Step 16:
 528          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 529          */
 530         out_be64(&priv2->spu_privcntl_RW, 0UL);
 531         eieio();
 532 }
 533
 534 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 535 {
 536         struct spu_priv2 __iomem *priv2 = spu->priv2;
 537
 538         /* Save, Step 34:
 539          *     Save SPU_LSLR in the CSA.
 540          */
 541         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 542 }
 543
 544 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 545 {
 546         struct spu_priv2 __iomem *priv2 = spu->priv2;
 547
 548         /* Save, Step 35:
 549          * Restore, Step 17.
 550          *     Reset SPU_LSLR.
 551          */
 552         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 553         eieio();
 554 }
 555
 556 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 557 {
 558         struct spu_priv2 __iomem *priv2 = spu->priv2;
 559
 560         /* Save, Step 36:
 561          *     Save SPU_Cfg in the CSA.
 562          */
 563         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 564 }
 565
 566 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 567 {
 568         /* Save, Step 37:
 569          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 570          *     Not performed by this implementation.
 571          */
 572 }
 573
 574 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 575 {
 576         /* Save, Step 38:
 577          *     Save RA_GROUP_ID register and the
 578          *     RA_ENABLE reigster in the CSA.
 579          */
 580         csa->priv1.resource_allocation_groupID_RW =
 581                 spu_resource_allocation_groupID_get(spu);
 582         csa->priv1.resource_allocation_enable_RW =
 583                 spu_resource_allocation_enable_get(spu);
 584 }
 585
 586 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 587 {
 588         struct spu_problem __iomem *prob = spu->problem;
 589
 590         /* Save, Step 39:
 591          *     Save MB_Stat register in the CSA.
 592          */
 593         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 594 }
 595
 596 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 597 {
 598         struct spu_problem __iomem *prob = spu->problem;
 599
 600         /* Save, Step 40:
 601          *     Save the PPU_MB register in the CSA.
 602          */
 603         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 604 }
 605
 606 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 607 {
 608         struct spu_priv2 __iomem *priv2 = spu->priv2;
 609
 610         /* Save, Step 41:
 611          *     Save the PPUINT_MB register in the CSA.
 612          */
 613         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 614 }
 615
 616 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 617 {
 618         struct spu_priv2 __iomem *priv2 = spu->priv2;
 619         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 620         int i;
 621
 622         /* Save, Step 42:
 623          */
 624
 625         /* Save CH 1, without channel count */
 626         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 627         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 628
 629         /* Save the following CH: [0,3,4,24,25,27] */
 630         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
 631                 idx = ch_indices[i];
 632                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 633                 eieio();
 634                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 635                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 636                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 637                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 638                 eieio();
 639         }
 640 }
 641
 642 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 643 {
 644         struct spu_priv2 __iomem *priv2 = spu->priv2;
 645         int i;
 646
 647         /* Save, Step 43:
 648          *     Save SPU Read Mailbox Channel.
 649          */
 650         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 651         eieio();
 652         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 653         for (i = 0; i < 4; i++) {
 654                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 655         }
 656         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 657         eieio();
 658 }
 659
 660 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 661 {
 662         struct spu_priv2 __iomem *priv2 = spu->priv2;
 663
 664         /* Save, Step 44:
 665          *     Save MFC_CMD Channel.
 666          */
 667         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 668         eieio();
 669         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 670         eieio();
 671 }
 672
 673 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 674 {
 675         struct spu_priv2 __iomem *priv2 = spu->priv2;
 676         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 677         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 678         u64 idx;
 679         int i;
 680
 681         /* Save, Step 45:
 682          *     Reset the following CH: [21, 23, 28, 30]
 683          */
 684         for (i = 0; i < 4; i++) {
 685                 idx = ch_indices[i];
 686                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 687                 eieio();
 688                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 689                 eieio();
 690         }
 691 }
 692
 693 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 694 {
 695         struct spu_priv2 __iomem *priv2 = spu->priv2;
 696
 697         /* Save, Step 46:
 698          * Restore, Step 25.
 699          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 700          */
 701         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 702 }
 703
 704 static inline void get_kernel_slb(u64 ea, u64 slb[2])
 705 {
 706         u64 llp;
 707
 708         if (REGION_ID(ea) == KERNEL_REGION_ID)
 709                 llp = mmu_psize_defs[mmu_linear_psize].sllp;
 710         else
 711                 llp = mmu_psize_defs[mmu_virtual_psize].sllp;
 712         slb[0] = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
 713                 SLB_VSID_KERNEL | llp;
 714         slb[1] = (ea & ESID_MASK) | SLB_ESID_V;
 715 }
 716
 717 static inline void load_mfc_slb(struct spu *spu, u64 slb[2], int slbe)
 718 {
 719         struct spu_priv2 __iomem *priv2 = spu->priv2;
 720
 721         out_be64(&priv2->slb_index_W, slbe);
 722         eieio();
 723         out_be64(&priv2->slb_vsid_RW, slb[0]);
 724         out_be64(&priv2->slb_esid_RW, slb[1]);
 725         eieio();
 726 }
 727
 728 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
 729 {
 730         u64 code_slb[2];
 731         u64 lscsa_slb[2];
 732
 733         /* Save, Step 47:
 734          * Restore, Step 30.
 735          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 736          *     register, then initialize SLB_VSID and SLB_ESID
 737          *     to provide access to SPU context save code and
 738          *     LSCSA.
 739          *
 740          *     This implementation places both the context
 741          *     switch code and LSCSA in kernel address space.
 742          *
 743          *     Further this implementation assumes that the
 744          *     MFC_SR1[R]=1 (in other words, assume that
 745          *     translation is desired by OS environment).
 746          */
 747         spu_invalidate_slbs(spu);
 748         get_kernel_slb((unsigned long)&spu_save_code[0], code_slb);
 749         get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
 750         load_mfc_slb(spu, code_slb, 0);
 751         if ((lscsa_slb[0] != code_slb[0]) || (lscsa_slb[1] != code_slb[1]))
 752                 load_mfc_slb(spu, lscsa_slb, 1);
 753 }
 754
 755 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 756 {
 757         /* Save, Step 48:
 758          * Restore, Step 23.
 759          *     Change the software context switch pending flag
 760          *     to context switch active.
 761          */
 762         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
 763         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 764         mb();
 765 }
 766
 767 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 768 {
 769         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 770             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 771
 772         /* Save, Step 49:
 773          * Restore, Step 22:
 774          *     Reset and then enable interrupts, as
 775          *     needed by OS.
 776          *
 777          *     This implementation enables only class1
 778          *     (translation) interrupts.
 779          */
 780         spin_lock_irq(&spu->register_lock);
 781         spu_int_stat_clear(spu, 0, ~0ul);
 782         spu_int_stat_clear(spu, 1, ~0ul);
 783         spu_int_stat_clear(spu, 2, ~0ul);
 784         spu_int_mask_set(spu, 0, 0ul);
 785         spu_int_mask_set(spu, 1, class1_mask);
 786         spu_int_mask_set(spu, 2, 0ul);
 787         spin_unlock_irq(&spu->register_lock);
 788 }
 789
 790 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 791                                unsigned int ls_offset, unsigned int size,
 792                                unsigned int tag, unsigned int rclass,
 793                                unsigned int cmd)
 794 {
 795         struct spu_problem __iomem *prob = spu->problem;
 796         union mfc_tag_size_class_cmd command;
 797         unsigned int transfer_size;
 798         volatile unsigned int status = 0x0;
 799
 800         while (size > 0) {
 801                 transfer_size =
 802                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 803                 command.u.mfc_size = transfer_size;
 804                 command.u.mfc_tag = tag;
 805                 command.u.mfc_rclassid = rclass;
 806                 command.u.mfc_cmd = cmd;
 807                 do {
 808                         out_be32(&prob->mfc_lsa_W, ls_offset);
 809                         out_be64(&prob->mfc_ea_W, ea);
 810                         out_be64(&prob->mfc_union_W.all64, command.all64);
 811                         status =
 812                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 813                         if (unlikely(status & 0x2)) {
 814                                 cpu_relax();
 815                         }
 816                 } while (status & 0x3);
 817                 size -= transfer_size;
 818                 ea += transfer_size;
 819                 ls_offset += transfer_size;
 820         }
 821         return 0;
 822 }
 823
 824 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 825 {
 826         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 827         unsigned int ls_offset = 0x0;
 828         unsigned int size = 16384;
 829         unsigned int tag = 0;
 830         unsigned int rclass = 0;
 831         unsigned int cmd = MFC_PUT_CMD;
 832
 833         /* Save, Step 50:
 834          *     Issue a DMA command to copy the first 16K bytes
 835          *     of local storage to the CSA.
 836          */
 837         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 838 }
 839
 840 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 841 {
 842         struct spu_problem __iomem *prob = spu->problem;
 843
 844         /* Save, Step 51:
 845          * Restore, Step 31.
 846          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 847          *     point address of context save code in local
 848          *     storage.
 849          *
 850          *     This implementation uses SPU-side save/restore
 851          *     programs with entry points at LSA of 0.
 852          */
 853         out_be32(&prob->spu_npc_RW, 0);
 854         eieio();
 855 }
 856
 857 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 858 {
 859         struct spu_problem __iomem *prob = spu->problem;
 860         union {
 861                 u64 ull;
 862                 u32 ui[2];
 863         } addr64;
 864
 865         /* Save, Step 52:
 866          * Restore, Step 32:
 867          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 868          *    of the CSA.LSCSA effective address.
 869          */
 870         addr64.ull = (u64) csa->lscsa;
 871         out_be32(&prob->signal_notify1, addr64.ui[0]);
 872         eieio();
 873 }
 874
 875 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 876 {
 877         struct spu_problem __iomem *prob = spu->problem;
 878         union {
 879                 u64 ull;
 880                 u32 ui[2];
 881         } addr64;
 882
 883         /* Save, Step 53:
 884          * Restore, Step 33:
 885          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 886          *    of the CSA.LSCSA effective address.
 887          */
 888         addr64.ull = (u64) csa->lscsa;
 889         out_be32(&prob->signal_notify2, addr64.ui[1]);
 890         eieio();
 891 }
 892
 893 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 894 {
 895         unsigned long addr = (unsigned long)&spu_save_code[0];
 896         unsigned int ls_offset = 0x0;
 897         unsigned int size = sizeof(spu_save_code);
 898         unsigned int tag = 0;
 899         unsigned int rclass = 0;
 900         unsigned int cmd = MFC_GETFS_CMD;
 901
 902         /* Save, Step 54:
 903          *     Issue a DMA command to copy context save code
 904          *     to local storage and start SPU.
 905          */
 906         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 907 }
 908
 909 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 910 {
 911         struct spu_problem __iomem *prob = spu->problem;
 912
 913         /* Save, Step 55:
 914          * Restore, Step 38.
 915          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 916          *     and issue eieio instruction.
 917          */
 918         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 919         eieio();
 920 }
 921
 922 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 923 {
 924         struct spu_problem __iomem *prob = spu->problem;
 925         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 926         unsigned long flags;
 927
 928         /* Save, Step 56:
 929          * Restore, Step 39.
 930          * Restore, Step 39.
 931          * Restore, Step 46.
 932          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 933          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 934          *     Complete Interrupt.  Write INT_Stat_Class0 or
 935          *     INT_Stat_Class2 with value of 'handled'.
 936          */
 937         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 938
 939         local_irq_save(flags);
 940         spu_int_stat_clear(spu, 0, ~(0ul));
 941         spu_int_stat_clear(spu, 2, ~(0ul));
 942         local_irq_restore(flags);
 943 }
 944
 945 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 946 {
 947         struct spu_problem __iomem *prob = spu->problem;
 948         unsigned long flags;
 949
 950         /* Save, Step 57:
 951          * Restore, Step 40.
 952          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 953          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 954          *     or INT_Stat_class2 with value of handled.
 955          */
 956         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 957
 958         local_irq_save(flags);
 959         spu_int_stat_clear(spu, 0, ~(0ul));
 960         spu_int_stat_clear(spu, 2, ~(0ul));
 961         local_irq_restore(flags);
 962 }
 963
 964 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 965 {
 966         struct spu_problem __iomem *prob = spu->problem;
 967         u32 complete;
 968
 969         /* Save, Step 54:
 970          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 971          *     context save succeeded, otherwise context save
 972          *     failed.
 973          */
 974         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 975                     SPU_STATUS_STOPPED_BY_STOP);
 976         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 977 }
 978
 979 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 980 {
 981         /* Restore, Step 4:
 982          *    If required, notify the "using application" that
 983          *    the SPU task has been terminated.  TBD.
 984          */
 985 }
 986
 987 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
 988 {
 989         struct spu_priv2 __iomem *priv2 = spu->priv2;
 990
 991         /* Restore, Step 7:
 992          * Restore, Step 47.
 993          *     Write MFC_Cntl[Dh,Sc]='1','1' to suspend
 994          *     the queue and halt the decrementer.
 995          */
 996         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 997                  MFC_CNTL_DECREMENTER_HALTED);
 998         eieio();
 999 }
1000
1001 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
1002                                              struct spu *spu)
1003 {
1004         struct spu_priv2 __iomem *priv2 = spu->priv2;
1005
1006         /* Restore, Step 8:
1007          * Restore, Step 47.
1008          *     Poll MFC_CNTL[Ss] until 11 is returned.
1009          */
1010         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1011                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
1012                          MFC_CNTL_SUSPEND_COMPLETE);
1013 }
1014
1015 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1016 {
1017         struct spu_problem __iomem *prob = spu->problem;
1018
1019         /* Restore, Step 9:
1020          *    If SPU_Status[R]=1, stop SPU execution
1021          *    and wait for stop to complete.
1022          *
1023          *    Returns       1 if SPU_Status[R]=1 on entry.
1024          *                  0 otherwise
1025          */
1026         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1027                 if (in_be32(&prob->spu_status_R) &
1028                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1029                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1030                                         SPU_STATUS_RUNNING);
1031                 }
1032                 if ((in_be32(&prob->spu_status_R) &
1033                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1034                     || (in_be32(&prob->spu_status_R) &
1035                         SPU_STATUS_ISOLATED_STATE)) {
1036                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1037                         eieio();
1038                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1039                                         SPU_STATUS_RUNNING);
1040                         out_be32(&prob->spu_runcntl_RW, 0x2);
1041                         eieio();
1042                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1043                                         SPU_STATUS_RUNNING);
1044                 }
1045                 if (in_be32(&prob->spu_status_R) &
1046                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1047                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1048                         eieio();
1049                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1050                                         SPU_STATUS_RUNNING);
1051                 }
1052                 return 1;
1053         }
1054         return 0;
1055 }
1056
1057 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1058 {
1059         struct spu_problem __iomem *prob = spu->problem;
1060
1061         /* Restore, Step 10:
1062          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1063          *    release SPU from isolate state.
1064          */
1065         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1066                 if (in_be32(&prob->spu_status_R) &
1067                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1068                         spu_mfc_sr1_set(spu,
1069                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1070                         eieio();
1071                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1072                         eieio();
1073                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1074                                         SPU_STATUS_RUNNING);
1075                 }
1076                 if ((in_be32(&prob->spu_status_R) &
1077                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1078                     || (in_be32(&prob->spu_status_R) &
1079                         SPU_STATUS_ISOLATED_STATE)) {
1080                         spu_mfc_sr1_set(spu,
1081                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1082                         eieio();
1083                         out_be32(&prob->spu_runcntl_RW, 0x2);
1084                         eieio();
1085                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1086                                         SPU_STATUS_RUNNING);
1087                 }
1088         }
1089 }
1090
1091 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1092 {
1093         struct spu_priv2 __iomem *priv2 = spu->priv2;
1094         u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1095         u64 idx;
1096         int i;
1097
1098         /* Restore, Step 20:
1099          */
1100
1101         /* Reset CH 1 */
1102         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1103         out_be64(&priv2->spu_chnldata_RW, 0UL);
1104
1105         /* Reset the following CH: [0,3,4,24,25,27] */
1106         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1107                 idx = ch_indices[i];
1108                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1109                 eieio();
1110                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1111                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1112                 eieio();
1113         }
1114 }
1115
1116 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1117 {
1118         struct spu_priv2 __iomem *priv2 = spu->priv2;
1119         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1120         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1121         u64 idx;
1122         int i;
1123
1124         /* Restore, Step 21:
1125          *     Reset the following CH: [21, 23, 28, 29, 30]
1126          */
1127         for (i = 0; i < 5; i++) {
1128                 idx = ch_indices[i];
1129                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1130                 eieio();
1131                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1132                 eieio();
1133         }
1134 }
1135
1136 static inline void setup_spu_status_part1(struct spu_state *csa,
1137                                           struct spu *spu)
1138 {
1139         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1140         u32 status_I = SPU_STATUS_INVALID_INSTR;
1141         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1142         u32 status_S = SPU_STATUS_SINGLE_STEP;
1143         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1144         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1145         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1146         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1147         u32 status_code;
1148
1149         /* Restore, Step 27:
1150          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1151          *     instruction sequence to the end of the SPU based restore
1152          *     code (after the "context restored" stop and signal) to
1153          *     restore the correct SPU status.
1154          *
1155          *     NOTE: Rather than modifying the SPU executable, we
1156          *     instead add a new 'stopped_status' field to the
1157          *     LSCSA.  The SPU-side restore reads this field and
1158          *     takes the appropriate action when exiting.
1159          */
1160
1161         status_code =
1162             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1163         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1164
1165                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1166                  * by Stop and Signal instruction, followed by 'br -4'.
1167                  *
1168                  */
1169                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1170                 csa->lscsa->stopped_status.slot[1] = status_code;
1171
1172         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1173
1174                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1175                  * by Stop and Signal instruction, followed by
1176                  * 'br -4'.
1177                  */
1178                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1179                 csa->lscsa->stopped_status.slot[1] = status_code;
1180
1181         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1182
1183                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1184                  * followed by 'br -4'.
1185                  */
1186                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1187                 csa->lscsa->stopped_status.slot[1] = status_code;
1188
1189         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1190
1191                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1192                  * by 'br -4'.
1193                  */
1194                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1195                 csa->lscsa->stopped_status.slot[1] = status_code;
1196
1197         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1198
1199                 /* SPU_Status[P]=1 - Stop and Signal instruction
1200                  * followed by 'br -4'.
1201                  */
1202                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1203                 csa->lscsa->stopped_status.slot[1] = status_code;
1204
1205         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1206
1207                 /* SPU_Status[H]=1 - Halt Conditional, followed
1208                  * by 'br -4'.
1209                  */
1210                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1211
1212         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1213
1214                 /* SPU_Status[S]=1 - Two nop instructions.
1215                  */
1216                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1217
1218         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1219
1220                 /* SPU_Status[I]=1 - Illegal instruction followed
1221                  * by 'br -4'.
1222                  */
1223                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1224
1225         }
1226 }
1227
1228 static inline void setup_spu_status_part2(struct spu_state *csa,
1229                                           struct spu *spu)
1230 {
1231         u32 mask;
1232
1233         /* Restore, Step 28:
1234          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1235          *     add a 'br *' instruction to the end of
1236          *     the SPU based restore code.
1237          *
1238          *     NOTE: Rather than modifying the SPU executable, we
1239          *     instead add a new 'stopped_status' field to the
1240          *     LSCSA.  The SPU-side restore reads this field and
1241          *     takes the appropriate action when exiting.
1242          */
1243         mask = SPU_STATUS_INVALID_INSTR |
1244             SPU_STATUS_SINGLE_STEP |
1245             SPU_STATUS_STOPPED_BY_HALT |
1246             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1247         if (!(csa->prob.spu_status_R & mask)) {
1248                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1249         }
1250 }
1251
1252 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1253 {
1254         /* Restore, Step 29:
1255          *     Restore RA_GROUP_ID register and the
1256          *     RA_ENABLE reigster from the CSA.
1257          */
1258         spu_resource_allocation_groupID_set(spu,
1259                         csa->priv1.resource_allocation_groupID_RW);
1260         spu_resource_allocation_enable_set(spu,
1261                         csa->priv1.resource_allocation_enable_RW);
1262 }
1263
1264 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1265 {
1266         unsigned long addr = (unsigned long)&spu_restore_code[0];
1267         unsigned int ls_offset = 0x0;
1268         unsigned int size = sizeof(spu_restore_code);
1269         unsigned int tag = 0;
1270         unsigned int rclass = 0;
1271         unsigned int cmd = MFC_GETFS_CMD;
1272
1273         /* Restore, Step 37:
1274          *     Issue MFC DMA command to copy context
1275          *     restore code to local storage.
1276          */
1277         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1278 }
1279
1280 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1281 {
1282         /* Restore, Step 34:
1283          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1284          *     running) then adjust decrementer, set
1285          *     decrementer running status in LSCSA,
1286          *     and set decrementer "wrapped" status
1287          *     in LSCSA.
1288          */
1289         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1290                 cycles_t resume_time = get_cycles();
1291                 cycles_t delta_time = resume_time - csa->suspend_time;
1292
1293                 csa->lscsa->decr.slot[0] -= delta_time;
1294         }
1295 }
1296
1297 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1298 {
1299         /* Restore, Step 35:
1300          *     Copy the CSA.PU_MB data into the LSCSA.
1301          */
1302         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1303 }
1304
1305 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1306 {
1307         /* Restore, Step 36:
1308          *     Copy the CSA.PUINT_MB data into the LSCSA.
1309          */
1310         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1311 }
1312
1313 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1314 {
1315         struct spu_problem __iomem *prob = spu->problem;
1316         u32 complete;
1317
1318         /* Restore, Step 40:
1319          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1320          *     context restore succeeded, otherwise context restore
1321          *     failed.
1322          */
1323         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1324                     SPU_STATUS_STOPPED_BY_STOP);
1325         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1326 }
1327
1328 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1329 {
1330         struct spu_priv2 __iomem *priv2 = spu->priv2;
1331
1332         /* Restore, Step 41:
1333          *     Restore SPU_PrivCntl from the CSA.
1334          */
1335         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1336         eieio();
1337 }
1338
1339 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1340 {
1341         struct spu_problem __iomem *prob = spu->problem;
1342         u32 mask;
1343
1344         /* Restore, Step 42:
1345          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1346          *     restore the error or single step state.
1347          */
1348         mask = SPU_STATUS_INVALID_INSTR |
1349             SPU_STATUS_SINGLE_STEP |
1350             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1351         if (csa->prob.spu_status_R & mask) {
1352                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1353                 eieio();
1354                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1355                                 SPU_STATUS_RUNNING);
1356         }
1357 }
1358
1359 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1360 {
1361         struct spu_problem __iomem *prob = spu->problem;
1362         u32 mask;
1363
1364         /* Restore, Step 43:
1365          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1366          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1367          *     then write '00' to SPU_RunCntl[R0R1] and wait
1368          *     for SPU_Status[R]=0.
1369          */
1370         mask = SPU_STATUS_INVALID_INSTR |
1371             SPU_STATUS_SINGLE_STEP |
1372             SPU_STATUS_STOPPED_BY_HALT |
1373             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1374         if (!(csa->prob.spu_status_R & mask)) {
1375                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1376                 eieio();
1377                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1378                                  SPU_STATUS_RUNNING);
1379                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1380                 eieio();
1381                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1382                                 SPU_STATUS_RUNNING);
1383         }
1384 }
1385
1386 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1387 {
1388         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1389         unsigned int ls_offset = 0x0;
1390         unsigned int size = 16384;
1391         unsigned int tag = 0;
1392         unsigned int rclass = 0;
1393         unsigned int cmd = MFC_GET_CMD;
1394
1395         /* Restore, Step 44:
1396          *     Issue a DMA command to restore the first
1397          *     16kb of local storage from CSA.
1398          */
1399         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1400 }
1401
1402 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1403 {
1404         /* Restore, Step 49:
1405          *     Write INT_MASK_class0 with value of 0.
1406          *     Write INT_MASK_class1 with value of 0.
1407          *     Write INT_MASK_class2 with value of 0.
1408          *     Write INT_STAT_class0 with value of -1.
1409          *     Write INT_STAT_class1 with value of -1.
1410          *     Write INT_STAT_class2 with value of -1.
1411          */
1412         spin_lock_irq(&spu->register_lock);
1413         spu_int_mask_set(spu, 0, 0ul);
1414         spu_int_mask_set(spu, 1, 0ul);
1415         spu_int_mask_set(spu, 2, 0ul);
1416         spu_int_stat_clear(spu, 0, ~0ul);
1417         spu_int_stat_clear(spu, 1, ~0ul);
1418         spu_int_stat_clear(spu, 2, ~0ul);
1419         spin_unlock_irq(&spu->register_lock);
1420 }
1421
1422 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1423 {
1424         struct spu_priv2 __iomem *priv2 = spu->priv2;
1425         int i;
1426
1427         /* Restore, Step 50:
1428          *     If MFC_Cntl[Se]!=0 then restore
1429          *     MFC command queues.
1430          */
1431         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1432                 for (i = 0; i < 8; i++) {
1433                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1434                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1435                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1436                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1437                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1438                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1439                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1440                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1441                 }
1442                 for (i = 0; i < 16; i++) {
1443                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1444                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1445                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1446                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1447                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1448                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1449                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1450                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1451                 }
1452         }
1453         eieio();
1454 }
1455
1456 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1457 {
1458         struct spu_problem __iomem *prob = spu->problem;
1459
1460         /* Restore, Step 51:
1461          *     Restore the PPU_QueryMask register from CSA.
1462          */
1463         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1464         eieio();
1465 }
1466
1467 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1468 {
1469         struct spu_problem __iomem *prob = spu->problem;
1470
1471         /* Restore, Step 52:
1472          *     Restore the PPU_QueryType register from CSA.
1473          */
1474         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1475         eieio();
1476 }
1477
1478 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1479 {
1480         struct spu_priv2 __iomem *priv2 = spu->priv2;
1481
1482         /* Restore, Step 53:
1483          *     Restore the MFC_CSR_TSQ register from CSA.
1484          */
1485         out_be64(&priv2->spu_tag_status_query_RW,
1486                  csa->priv2.spu_tag_status_query_RW);
1487         eieio();
1488 }
1489
1490 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1491 {
1492         struct spu_priv2 __iomem *priv2 = spu->priv2;
1493
1494         /* Restore, Step 54:
1495          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1496          *     registers from CSA.
1497          */
1498         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1499         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1500         eieio();
1501 }
1502
1503 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1504 {
1505         struct spu_priv2 __iomem *priv2 = spu->priv2;
1506
1507         /* Restore, Step 55:
1508          *     Restore the MFC_CSR_ATO register from CSA.
1509          */
1510         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1511 }
1512
1513 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1514 {
1515         /* Restore, Step 56:
1516          *     Restore the MFC_TCLASS_ID register from CSA.
1517          */
1518         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1519         eieio();
1520 }
1521
1522 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1523 {
1524         u64 ch0_cnt, ch0_data;
1525         u64 ch1_data;
1526
1527         /* Restore, Step 57:
1528          *    Set the Lock Line Reservation Lost Event by:
1529          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1530          *      2. If CSA.SPU_Channel_0_Count=0 and
1531          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1532          *         CSA.SPU_Event_Status[Lr]=0 then set
1533          *         CSA.SPU_Event_Status_Count=1.
1534          */
1535         ch0_cnt = csa->spu_chnlcnt_RW[0];
1536         ch0_data = csa->spu_chnldata_RW[0];
1537         ch1_data = csa->spu_chnldata_RW[1];
1538         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1539         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1540             (ch1_data & MFC_LLR_LOST_EVENT)) {
1541                 csa->spu_chnlcnt_RW[0] = 1;
1542         }
1543 }
1544
1545 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1546 {
1547         /* Restore, Step 58:
1548          *     If the status of the CSA software decrementer
1549          *     "wrapped" flag is set, OR in a '1' to
1550          *     CSA.SPU_Event_Status[Tm].
1551          */
1552         if (csa->lscsa->decr_status.slot[0] == 1) {
1553                 csa->spu_chnldata_RW[0] |= 0x20;
1554         }
1555         if ((csa->lscsa->decr_status.slot[0] == 1) &&
1556             (csa->spu_chnlcnt_RW[0] == 0 &&
1557              ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1558              ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1559                 csa->spu_chnlcnt_RW[0] = 1;
1560         }
1561 }
1562
1563 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1564 {
1565         struct spu_priv2 __iomem *priv2 = spu->priv2;
1566         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1567         int i;
1568
1569         /* Restore, Step 59:
1570          */
1571
1572         /* Restore CH 1 without count */
1573         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1574         out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1575
1576         /* Restore the following CH: [0,3,4,24,25,27] */
1577         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1578                 idx = ch_indices[i];
1579                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1580                 eieio();
1581                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1582                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1583                 eieio();
1584         }
1585 }
1586
1587 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1588 {
1589         struct spu_priv2 __iomem *priv2 = spu->priv2;
1590         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1591         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1592         u64 idx;
1593         int i;
1594
1595         /* Restore, Step 60:
1596          *     Restore the following CH: [9,21,23].
1597          */
1598         ch_counts[0] = 1UL;
1599         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1600         ch_counts[2] = 1UL;
1601         for (i = 0; i < 3; i++) {
1602                 idx = ch_indices[i];
1603                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1604                 eieio();
1605                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1606                 eieio();
1607         }
1608 }
1609
1610 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1611 {
1612         struct spu_priv2 __iomem *priv2 = spu->priv2;
1613
1614         /* Restore, Step 61:
1615          *     Restore the SPU_LSLR register from CSA.
1616          */
1617         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1618         eieio();
1619 }
1620
1621 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1622 {
1623         struct spu_priv2 __iomem *priv2 = spu->priv2;
1624
1625         /* Restore, Step 62:
1626          *     Restore the SPU_Cfg register from CSA.
1627          */
1628         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1629         eieio();
1630 }
1631
1632 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1633 {
1634         /* Restore, Step 63:
1635          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1636          *     Not performed by this implementation.
1637          */
1638 }
1639
1640 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1641 {
1642         struct spu_problem __iomem *prob = spu->problem;
1643
1644         /* Restore, Step 64:
1645          *     Restore SPU_NPC from CSA.
1646          */
1647         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1648         eieio();
1649 }
1650
1651 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1652 {
1653         struct spu_priv2 __iomem *priv2 = spu->priv2;
1654         int i;
1655
1656         /* Restore, Step 65:
1657          *     Restore MFC_RdSPU_MB from CSA.
1658          */
1659         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1660         eieio();
1661         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1662         for (i = 0; i < 4; i++) {
1663                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1664         }
1665         eieio();
1666 }
1667
1668 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1669 {
1670         struct spu_problem __iomem *prob = spu->problem;
1671         u32 dummy = 0;
1672
1673         /* Restore, Step 66:
1674          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1675          *     read from the PPU_MB register.
1676          */
1677         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1678                 dummy = in_be32(&prob->pu_mb_R);
1679                 eieio();
1680         }
1681 }
1682
1683 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1684 {
1685         struct spu_priv2 __iomem *priv2 = spu->priv2;
1686         u64 dummy = 0UL;
1687
1688         /* Restore, Step 66:
1689          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1690          *     read from the PPUINT_MB register.
1691          */
1692         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1693                 dummy = in_be64(&priv2->puint_mb_R);
1694                 eieio();
1695                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1696                 eieio();
1697         }
1698 }
1699
1700 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1701 {
1702         /* Restore, Step 69:
1703          *     Restore the MFC_SR1 register from CSA.
1704          */
1705         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1706         eieio();
1707 }
1708
1709 static inline void restore_other_spu_access(struct spu_state *csa,
1710                                             struct spu *spu)
1711 {
1712         /* Restore, Step 70:
1713          *     Restore other SPU mappings to this SPU. TBD.
1714          */
1715 }
1716
1717 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1718 {
1719         struct spu_problem __iomem *prob = spu->problem;
1720
1721         /* Restore, Step 71:
1722          *     If CSA.SPU_Status[R]=1 then write
1723          *     SPU_RunCntl[R0R1]='01'.
1724          */
1725         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1726                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1727                 eieio();
1728         }
1729 }
1730
1731 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1732 {
1733         struct spu_priv2 __iomem *priv2 = spu->priv2;
1734
1735         /* Restore, Step 72:
1736          *    Restore the MFC_CNTL register for the CSA.
1737          */
1738         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1739         eieio();
1740         /*
1741          * FIXME: this is to restart a DMA that we were processing
1742          *        before the save. better remember the fault information
1743          *        in the csa instead.
1744          */
1745         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1746                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1747                 eieio();
1748         }
1749 }
1750
1751 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1752 {
1753         /* Restore, Step 73:
1754          *     Enable user-space access (if provided) to this
1755          *     SPU by mapping the virtual pages assigned to
1756          *     the SPU memory-mapped I/O (MMIO) for problem
1757          *     state. TBD.
1758          */
1759 }
1760
1761 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1762 {
1763         /* Restore, Step 74:
1764          *     Reset the "context switch active" flag.
1765          */
1766         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1767         mb();
1768 }
1769
1770 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1771 {
1772         /* Restore, Step 75:
1773          *     Re-enable SPU interrupts.
1774          */
1775         spin_lock_irq(&spu->register_lock);
1776         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1777         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1778         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1779         spin_unlock_irq(&spu->register_lock);
1780 }
1781
1782 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1783 {
1784         /*
1785          * Combined steps 2-18 of SPU context save sequence, which
1786          * quiesce the SPU state (disable SPU execution, MFC command
1787          * queues, decrementer, SPU interrupts, etc.).
1788          *
1789          * Returns      0 on success.
1790          *              2 if failed step 2.
1791          *              6 if failed step 6.
1792          */
1793
1794         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1795                 return 2;
1796         }
1797         disable_interrupts(prev, spu);          /* Step 3. */
1798         set_watchdog_timer(prev, spu);          /* Step 4. */
1799         inhibit_user_access(prev, spu);         /* Step 5. */
1800         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1801                 return 6;
1802         }
1803         set_switch_pending(prev, spu);          /* Step 7. */
1804         save_mfc_cntl(prev, spu);               /* Step 8. */
1805         save_spu_runcntl(prev, spu);            /* Step 9. */
1806         save_mfc_sr1(prev, spu);                /* Step 10. */
1807         save_spu_status(prev, spu);             /* Step 11. */
1808         save_mfc_decr(prev, spu);               /* Step 12. */
1809         halt_mfc_decr(prev, spu);               /* Step 13. */
1810         save_timebase(prev, spu);               /* Step 14. */
1811         remove_other_spu_access(prev, spu);     /* Step 15. */
1812         do_mfc_mssync(prev, spu);               /* Step 16. */
1813         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1814         handle_pending_interrupts(prev, spu);   /* Step 18. */
1815
1816         return 0;
1817 }
1818
1819 static void save_csa(struct spu_state *prev, struct spu *spu)
1820 {
1821         /*
1822          * Combine steps 19-44 of SPU context save sequence, which
1823          * save regions of the privileged & problem state areas.
1824          */
1825
1826         save_mfc_queues(prev, spu);     /* Step 19. */
1827         save_ppu_querymask(prev, spu);  /* Step 20. */
1828         save_ppu_querytype(prev, spu);  /* Step 21. */
1829         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1830         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1831         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1832         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1833         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1834         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1835         purge_mfc_queue(prev, spu);     /* Step 27. */
1836         wait_purge_complete(prev, spu); /* Step 28. */
1837         setup_mfc_sr1(prev, spu);       /* Step 30. */
1838         save_spu_npc(prev, spu);        /* Step 31. */
1839         save_spu_privcntl(prev, spu);   /* Step 32. */
1840         reset_spu_privcntl(prev, spu);  /* Step 33. */
1841         save_spu_lslr(prev, spu);       /* Step 34. */
1842         reset_spu_lslr(prev, spu);      /* Step 35. */
1843         save_spu_cfg(prev, spu);        /* Step 36. */
1844         save_pm_trace(prev, spu);       /* Step 37. */
1845         save_mfc_rag(prev, spu);        /* Step 38. */
1846         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1847         save_ppu_mb(prev, spu);         /* Step 40. */
1848         save_ppuint_mb(prev, spu);      /* Step 41. */
1849         save_ch_part1(prev, spu);       /* Step 42. */
1850         save_spu_mb(prev, spu);         /* Step 43. */
1851         save_mfc_cmd(prev, spu);        /* Step 44. */
1852         reset_ch(prev, spu);            /* Step 45. */
1853 }
1854
1855 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1856 {
1857         /*
1858          * Perform steps 46-57 of SPU context save sequence,
1859          * which save regions of the local store and register
1860          * file.
1861          */
1862
1863         resume_mfc_queue(prev, spu);    /* Step 46. */
1864         setup_mfc_slbs(prev, spu);      /* Step 47. */
1865         set_switch_active(prev, spu);   /* Step 48. */
1866         enable_interrupts(prev, spu);   /* Step 49. */
1867         save_ls_16kb(prev, spu);        /* Step 50. */
1868         set_spu_npc(prev, spu);         /* Step 51. */
1869         set_signot1(prev, spu);         /* Step 52. */
1870         set_signot2(prev, spu);         /* Step 53. */
1871         send_save_code(prev, spu);      /* Step 54. */
1872         set_ppu_querymask(prev, spu);   /* Step 55. */
1873         wait_tag_complete(prev, spu);   /* Step 56. */
1874         wait_spu_stopped(prev, spu);    /* Step 57. */
1875 }
1876
1877 static void force_spu_isolate_exit(struct spu *spu)
1878 {
1879         struct spu_problem __iomem *prob = spu->problem;
1880         struct spu_priv2 __iomem *priv2 = spu->priv2;
1881
1882         /* Stop SPE execution and wait for completion. */
1883         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1884         iobarrier_rw();
1885         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1886
1887         /* Restart SPE master runcntl. */
1888         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1889         iobarrier_w();
1890
1891         /* Initiate isolate exit request and wait for completion. */
1892         out_be64(&priv2->spu_privcntl_RW, 4LL);
1893         iobarrier_w();
1894         out_be32(&prob->spu_runcntl_RW, 2);
1895         iobarrier_rw();
1896         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1897                                 & SPU_STATUS_STOPPED_BY_STOP));
1898
1899         /* Reset load request to normal. */
1900         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1901         iobarrier_w();
1902 }
1903
1904 /**
1905  * stop_spu_isolate
1906  *      Check SPU run-control state and force isolated
1907  *      exit function as necessary.
1908  */
1909 static void stop_spu_isolate(struct spu *spu)
1910 {
1911         struct spu_problem __iomem *prob = spu->problem;
1912
1913         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1914                 /* The SPU is in isolated state; the only way
1915                  * to get it out is to perform an isolated
1916                  * exit (clean) operation.
1917                  */
1918                 force_spu_isolate_exit(spu);
1919         }
1920 }
1921
1922 static void harvest(struct spu_state *prev, struct spu *spu)
1923 {
1924         /*
1925          * Perform steps 2-25 of SPU context restore sequence,
1926          * which resets an SPU either after a failed save, or
1927          * when using SPU for first time.
1928          */
1929
1930         disable_interrupts(prev, spu);          /* Step 2.  */
1931         inhibit_user_access(prev, spu);         /* Step 3.  */
1932         terminate_spu_app(prev, spu);           /* Step 4.  */
1933         set_switch_pending(prev, spu);          /* Step 5.  */
1934         stop_spu_isolate(spu);                  /* NEW.     */
1935         remove_other_spu_access(prev, spu);     /* Step 6.  */
1936         suspend_mfc(prev, spu);                 /* Step 7.  */
1937         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1938         if (!suspend_spe(prev, spu))            /* Step 9.  */
1939                 clear_spu_status(prev, spu);    /* Step 10. */
1940         do_mfc_mssync(prev, spu);               /* Step 11. */
1941         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1942         handle_pending_interrupts(prev, spu);   /* Step 13. */
1943         purge_mfc_queue(prev, spu);             /* Step 14. */
1944         wait_purge_complete(prev, spu);         /* Step 15. */
1945         reset_spu_privcntl(prev, spu);          /* Step 16. */
1946         reset_spu_lslr(prev, spu);              /* Step 17. */
1947         setup_mfc_sr1(prev, spu);               /* Step 18. */
1948         spu_invalidate_slbs(spu);               /* Step 19. */
1949         reset_ch_part1(prev, spu);              /* Step 20. */
1950         reset_ch_part2(prev, spu);              /* Step 21. */
1951         enable_interrupts(prev, spu);           /* Step 22. */
1952         set_switch_active(prev, spu);           /* Step 23. */
1953         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1954         resume_mfc_queue(prev, spu);            /* Step 25. */
1955 }
1956
1957 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1958 {
1959         /*
1960          * Perform steps 26-40 of SPU context restore sequence,
1961          * which restores regions of the local store and register
1962          * file.
1963          */
1964
1965         set_watchdog_timer(next, spu);          /* Step 26. */
1966         setup_spu_status_part1(next, spu);      /* Step 27. */
1967         setup_spu_status_part2(next, spu);      /* Step 28. */
1968         restore_mfc_rag(next, spu);             /* Step 29. */
1969         setup_mfc_slbs(next, spu);              /* Step 30. */
1970         set_spu_npc(next, spu);                 /* Step 31. */
1971         set_signot1(next, spu);                 /* Step 32. */
1972         set_signot2(next, spu);                 /* Step 33. */
1973         setup_decr(next, spu);                  /* Step 34. */
1974         setup_ppu_mb(next, spu);                /* Step 35. */
1975         setup_ppuint_mb(next, spu);             /* Step 36. */
1976         send_restore_code(next, spu);           /* Step 37. */
1977         set_ppu_querymask(next, spu);           /* Step 38. */
1978         wait_tag_complete(next, spu);           /* Step 39. */
1979         wait_spu_stopped(next, spu);            /* Step 40. */
1980 }
1981
1982 static void restore_csa(struct spu_state *next, struct spu *spu)
1983 {
1984         /*
1985          * Combine steps 41-76 of SPU context restore sequence, which
1986          * restore regions of the privileged & problem state areas.
1987          */
1988
1989         restore_spu_privcntl(next, spu);        /* Step 41. */
1990         restore_status_part1(next, spu);        /* Step 42. */
1991         restore_status_part2(next, spu);        /* Step 43. */
1992         restore_ls_16kb(next, spu);             /* Step 44. */
1993         wait_tag_complete(next, spu);           /* Step 45. */
1994         suspend_mfc(next, spu);                 /* Step 46. */
1995         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1996         issue_mfc_tlbie(next, spu);             /* Step 48. */
1997         clear_interrupts(next, spu);            /* Step 49. */
1998         restore_mfc_queues(next, spu);          /* Step 50. */
1999         restore_ppu_querymask(next, spu);       /* Step 51. */
2000         restore_ppu_querytype(next, spu);       /* Step 52. */
2001         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
2002         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
2003         restore_mfc_csr_ato(next, spu);         /* Step 55. */
2004         restore_mfc_tclass_id(next, spu);       /* Step 56. */
2005         set_llr_event(next, spu);               /* Step 57. */
2006         restore_decr_wrapped(next, spu);        /* Step 58. */
2007         restore_ch_part1(next, spu);            /* Step 59. */
2008         restore_ch_part2(next, spu);            /* Step 60. */
2009         restore_spu_lslr(next, spu);            /* Step 61. */
2010         restore_spu_cfg(next, spu);             /* Step 62. */
2011         restore_pm_trace(next, spu);            /* Step 63. */
2012         restore_spu_npc(next, spu);             /* Step 64. */
2013         restore_spu_mb(next, spu);              /* Step 65. */
2014         check_ppu_mb_stat(next, spu);           /* Step 66. */
2015         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2016         spu_invalidate_slbs(spu);               /* Modified Step 68. */
2017         restore_mfc_sr1(next, spu);             /* Step 69. */
2018         restore_other_spu_access(next, spu);    /* Step 70. */
2019         restore_spu_runcntl(next, spu);         /* Step 71. */
2020         restore_mfc_cntl(next, spu);            /* Step 72. */
2021         enable_user_access(next, spu);          /* Step 73. */
2022         reset_switch_active(next, spu);         /* Step 74. */
2023         reenable_interrupts(next, spu);         /* Step 75. */
2024 }
2025
2026 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2027 {
2028         int rc;
2029
2030         /*
2031          * SPU context save can be broken into three phases:
2032          *
2033          *     (a) quiesce [steps 2-16].
2034          *     (b) save of CSA, performed by PPE [steps 17-42]
2035          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2036          *
2037          * Returns      0 on success.
2038          *              2,6 if failed to quiece SPU
2039          *              53 if SPU-side of save failed.
2040          */
2041
2042         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2043         switch (rc) {
2044         default:
2045         case 2:
2046         case 6:
2047                 harvest(prev, spu);
2048                 return rc;
2049                 break;
2050         case 0:
2051                 break;
2052         }
2053         save_csa(prev, spu);                    /* Steps 17-43. */
2054         save_lscsa(prev, spu);                  /* Steps 44-53. */
2055         return check_save_status(prev, spu);    /* Step 54.     */
2056 }
2057
2058 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2059 {
2060         int rc;
2061
2062         /*
2063          * SPU context restore can be broken into three phases:
2064          *
2065          *    (a) harvest (or reset) SPU [steps 2-24].
2066          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2067          *    (c) restore CSA [steps 41-76], performed by PPE.
2068          *
2069          * The 'harvest' step is not performed here, but rather
2070          * as needed below.
2071          */
2072
2073         restore_lscsa(next, spu);               /* Steps 24-39. */
2074         rc = check_restore_status(next, spu);   /* Step 40.     */
2075         switch (rc) {
2076         default:
2077                 /* Failed. Return now. */
2078                 return rc;
2079                 break;
2080         case 0:
2081                 /* Fall through to next step. */
2082                 break;
2083         }
2084         restore_csa(next, spu);
2085
2086         return 0;
2087 }
2088
2089 /**
2090  * spu_save - SPU context save, with locking.
2091  * @prev: pointer to SPU context save area, to be saved.
2092  * @spu: pointer to SPU iomem structure.
2093  *
2094  * Acquire locks, perform the save operation then return.
2095  */
2096 int spu_save(struct spu_state *prev, struct spu *spu)
2097 {
2098         int rc;
2099
2100         acquire_spu_lock(spu);          /* Step 1.     */
2101         prev->dar = spu->dar;
2102         prev->dsisr = spu->dsisr;
2103         spu->dar = 0;
2104         spu->dsisr = 0;
2105         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2106         release_spu_lock(spu);
2107         if (rc != 0 && rc != 2 && rc != 6) {
2108                 panic("%s failed on SPU[%d], rc=%d.\n",
2109                       __func__, spu->number, rc);
2110         }
2111         return 0;
2112 }
2113 EXPORT_SYMBOL_GPL(spu_save);
2114
2115 /**
2116  * spu_restore - SPU context restore, with harvest and locking.
2117  * @new: pointer to SPU context save area, to be restored.
2118  * @spu: pointer to SPU iomem structure.
2119  *
2120  * Perform harvest + restore, as we may not be coming
2121  * from a previous successful save operation, and the
2122  * hardware state is unknown.
2123  */
2124 int spu_restore(struct spu_state *new, struct spu *spu)
2125 {
2126         int rc;
2127
2128         acquire_spu_lock(spu);
2129         harvest(NULL, spu);
2130         spu->slb_replace = 0;
2131         new->dar = 0;
2132         new->dsisr = 0;
2133         spu->class_0_pending = 0;
2134         rc = __do_spu_restore(new, spu);
2135         release_spu_lock(spu);
2136         if (rc) {
2137                 panic("%s failed on SPU[%d] rc=%d.\n",
2138                        __func__, spu->number, rc);
2139         }
2140         return rc;
2141 }
2142 EXPORT_SYMBOL_GPL(spu_restore);
2143
2144 /**
2145  * spu_harvest - SPU harvest (reset) operation
2146  * @spu: pointer to SPU iomem structure.
2147  *
2148  * Perform SPU harvest (reset) operation.
2149  */
2150 void spu_harvest(struct spu *spu)
2151 {
2152         acquire_spu_lock(spu);
2153         harvest(NULL, spu);
2154         release_spu_lock(spu);
2155 }
2156
2157 static void init_prob(struct spu_state *csa)
2158 {
2159         csa->spu_chnlcnt_RW[9] = 1;
2160         csa->spu_chnlcnt_RW[21] = 16;
2161         csa->spu_chnlcnt_RW[23] = 1;
2162         csa->spu_chnlcnt_RW[28] = 1;
2163         csa->spu_chnlcnt_RW[30] = 1;
2164         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2165         csa->prob.mb_stat_R = 0x000400;
2166 }
2167
2168 static void init_priv1(struct spu_state *csa)
2169 {
2170         /* Enable decode, relocate, tlbie response, master runcntl. */
2171         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2172             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2173             MFC_STATE1_PROBLEM_STATE_MASK |
2174             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2175
2176         /* Enable OS-specific set of interrupts. */
2177         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2178             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2179             CLASS0_ENABLE_SPU_ERROR_INTR;
2180         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2181             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2182         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2183             CLASS2_ENABLE_SPU_HALT_INTR |
2184             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2185 }
2186
2187 static void init_priv2(struct spu_state *csa)
2188 {
2189         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2190         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2191             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2192             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2193 }
2194
2195 /**
2196  * spu_alloc_csa - allocate and initialize an SPU context save area.
2197  *
2198  * Allocate and initialize the contents of an SPU context save area.
2199  * This includes enabling address translation, interrupt masks, etc.,
2200  * as appropriate for the given OS environment.
2201  *
2202  * Note that storage for the 'lscsa' is allocated separately,
2203  * as it is by far the largest of the context save regions,
2204  * and may need to be pinned or otherwise specially aligned.
2205  */
2206 int spu_init_csa(struct spu_state *csa)
2207 {
2208         int rc;
2209
2210         if (!csa)
2211                 return -EINVAL;
2212         memset(csa, 0, sizeof(struct spu_state));
2213
2214         rc = spu_alloc_lscsa(csa);
2215         if (rc)
2216                 return rc;
2217
2218         spin_lock_init(&csa->register_lock);
2219
2220         init_prob(csa);
2221         init_priv1(csa);
2222         init_priv2(csa);
2223
2224         return 0;
2225 }
2226 EXPORT_SYMBOL_GPL(spu_init_csa);
2227
2228 void spu_fini_csa(struct spu_state *csa)
2229 {
2230         spu_free_lscsa(csa);
2231 }
2232 EXPORT_SYMBOL_GPL(spu_fini_csa);