2 * IOMMU implementation for Cell Broadband Processor Architecture
4 * (C) Copyright IBM Corporation 2006-2008
6 * Author: Jeremy Kerr <jk@ozlabs.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/notifier.h>
30 #include <linux/of_platform.h>
31 #include <linux/lmb.h>
34 #include <asm/iommu.h>
35 #include <asm/machdep.h>
36 #include <asm/pci-bridge.h>
38 #include <asm/firmware.h>
39 #include <asm/cell-regs.h>
41 #include "interrupt.h"
43 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
44 * instead of leaving them mapped to some dummy page. This can be
45 * enabled once the appropriate workarounds for spider bugs have
48 #define CELL_IOMMU_REAL_UNMAP
50 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of
51 * IO PTEs based on the transfer direction. That can be enabled
52 * once spider-net has been fixed to pass the correct direction
53 * to the DMA mapping functions
55 #define CELL_IOMMU_STRICT_PROTECTION
60 /* IOC mmap registers */
61 #define IOC_Reg_Size 0x2000
63 #define IOC_IOPT_CacheInvd 0x908
64 #define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul
65 #define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul
66 #define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul
68 #define IOC_IOST_Origin 0x918
69 #define IOC_IOST_Origin_E 0x8000000000000000ul
70 #define IOC_IOST_Origin_HW 0x0000000000000800ul
71 #define IOC_IOST_Origin_HL 0x0000000000000400ul
73 #define IOC_IO_ExcpStat 0x920
74 #define IOC_IO_ExcpStat_V 0x8000000000000000ul
75 #define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul
76 #define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul
77 #define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul
78 #define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul
79 #define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul
80 #define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful
82 #define IOC_IO_ExcpMask 0x928
83 #define IOC_IO_ExcpMask_SFE 0x4000000000000000ul
84 #define IOC_IO_ExcpMask_PFE 0x2000000000000000ul
86 #define IOC_IOCmd_Offset 0x1000
88 #define IOC_IOCmd_Cfg 0xc00
89 #define IOC_IOCmd_Cfg_TE 0x0000800000000000ul
92 /* Segment table entries */
93 #define IOSTE_V 0x8000000000000000ul /* valid */
94 #define IOSTE_H 0x4000000000000000ul /* cache hint */
95 #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */
96 #define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */
97 #define IOSTE_PS_Mask 0x0000000000000007ul /* page size */
98 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */
99 #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */
100 #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */
101 #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */
103 /* Page table entries */
104 #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */
105 #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */
106 #define IOPTE_M 0x2000000000000000ul /* coherency required */
107 #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
108 #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
109 #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
110 #define IOPTE_H 0x0000000000000800ul /* cache hint */
111 #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
115 #define IO_SEGMENT_SHIFT 28
116 #define IO_PAGENO_BITS(shift) (IO_SEGMENT_SHIFT - (shift))
118 /* The high bit needs to be set on every DMA address */
119 #define SPIDER_DMA_OFFSET 0x80000000ul
121 struct iommu_window {
122 struct list_head list;
123 struct cbe_iommu *iommu;
124 unsigned long offset;
127 struct iommu_table table;
134 void __iomem *xlate_regs;
135 void __iomem *cmd_regs;
139 struct list_head windows;
142 /* Static array of iommus, one per node
143 * each contains a list of windows, keyed from dma_window property
144 * - on bus setup, look for a matching window, or create one
145 * - on dev setup, assign iommu_table ptr
147 static struct cbe_iommu iommus[NR_IOMMUS];
148 static int cbe_nr_iommus;
150 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
153 unsigned long __iomem *reg;
157 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd;
160 /* we can invalidate up to 1 << 11 PTEs at once */
161 n = min(n_ptes, 1l << 11);
162 val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask)
163 | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask)
164 | IOC_IOPT_CacheInvd_Busy;
167 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
175 static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
176 unsigned long uaddr, enum dma_data_direction direction,
177 struct dma_attrs *attrs)
180 unsigned long *io_pte, base_pte;
181 struct iommu_window *window =
182 container_of(tbl, struct iommu_window, table);
184 /* implementing proper protection causes problems with the spidernet
185 * driver - check mapping directions later, but allow read & write by
187 #ifdef CELL_IOMMU_STRICT_PROTECTION
188 /* to avoid referencing a global, we use a trick here to setup the
189 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended
190 * together for each of the 3 supported direction values. It is then
191 * shifted left so that the fields matching the desired direction
192 * lands on the appropriate bits, and other bits are masked out.
194 const unsigned long prot = 0xc48;
196 ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R))
197 | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask);
199 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
200 (window->ioid & IOPTE_IOID_Mask);
203 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
205 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
206 io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask);
210 invalidate_tce_cache(window->iommu, io_pte, npages);
212 pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n",
213 index, npages, direction, base_pte);
216 static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
220 unsigned long *io_pte, pte;
221 struct iommu_window *window =
222 container_of(tbl, struct iommu_window, table);
224 pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages);
226 #ifdef CELL_IOMMU_REAL_UNMAP
229 /* spider bridge does PCI reads after freeing - insert a mapping
230 * to a scratch page instead of an invalid entry */
231 pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page)
232 | (window->ioid & IOPTE_IOID_Mask);
235 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
237 for (i = 0; i < npages; i++)
242 invalidate_tce_cache(window->iommu, io_pte, npages);
245 static irqreturn_t ioc_interrupt(int irq, void *data)
248 struct cbe_iommu *iommu = data;
250 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
252 /* Might want to rate limit it */
253 printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat);
254 printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n",
255 !!(stat & IOC_IO_ExcpStat_V),
256 (stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ',
257 (stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ',
258 (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write",
259 (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask));
260 printk(KERN_ERR " page=0x%016lx\n",
261 stat & IOC_IO_ExcpStat_ADDR_Mask);
263 /* clear interrupt */
264 stat &= ~IOC_IO_ExcpStat_V;
265 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
270 static int cell_iommu_find_ioc(int nid, unsigned long *base)
272 struct device_node *np;
277 /* First look for new style /be nodes */
278 for_each_node_by_name(np, "ioc") {
279 if (of_node_to_nid(np) != nid)
281 if (of_address_to_resource(np, 0, &r)) {
282 printk(KERN_ERR "iommu: can't get address for %s\n",
291 /* Ok, let's try the old way */
292 for_each_node_by_type(np, "cpu") {
293 const unsigned int *nidp;
294 const unsigned long *tmp;
296 nidp = of_get_property(np, "node-id", NULL);
297 if (nidp && *nidp == nid) {
298 tmp = of_get_property(np, "ioc-translation", NULL);
310 static void cell_iommu_setup_stab(struct cbe_iommu *iommu,
311 unsigned long dbase, unsigned long dsize,
312 unsigned long fbase, unsigned long fsize)
315 unsigned long segments, stab_size;
317 segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
319 pr_debug("%s: iommu[%d]: segments: %lu\n",
320 __func__, iommu->nid, segments);
322 /* set up the segment table */
323 stab_size = segments * sizeof(unsigned long);
324 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size));
326 iommu->stab = page_address(page);
327 memset(iommu->stab, 0, stab_size);
330 static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
331 unsigned long base, unsigned long size, unsigned long gap_base,
332 unsigned long gap_size, unsigned long page_shift)
336 unsigned long reg, segments, pages_per_segment, ptab_size,
337 n_pte_pages, start_seg, *ptab;
339 start_seg = base >> IO_SEGMENT_SHIFT;
340 segments = size >> IO_SEGMENT_SHIFT;
341 pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift);
342 /* PTEs for each segment must start on a 4K bounday */
343 pages_per_segment = max(pages_per_segment,
344 (1 << 12) / sizeof(unsigned long));
346 ptab_size = segments * pages_per_segment * sizeof(unsigned long);
347 pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__,
348 iommu->nid, ptab_size, get_order(ptab_size));
349 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
352 ptab = page_address(page);
353 memset(ptab, 0, ptab_size);
355 /* number of 4K pages needed for a page table */
356 n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
358 pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
359 __func__, iommu->nid, iommu->stab, ptab,
362 /* initialise the STEs */
363 reg = IOSTE_V | ((n_pte_pages - 1) << 5);
365 switch (page_shift) {
366 case 12: reg |= IOSTE_PS_4K; break;
367 case 16: reg |= IOSTE_PS_64K; break;
368 case 20: reg |= IOSTE_PS_1M; break;
369 case 24: reg |= IOSTE_PS_16M; break;
373 gap_base = gap_base >> IO_SEGMENT_SHIFT;
374 gap_size = gap_size >> IO_SEGMENT_SHIFT;
376 pr_debug("Setting up IOMMU stab:\n");
377 for (i = start_seg; i < (start_seg + segments); i++) {
378 if (i >= gap_base && i < (gap_base + gap_size)) {
379 pr_debug("\toverlap at %d, skipping\n", i);
382 iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) *
384 pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
390 static void cell_iommu_enable_hardware(struct cbe_iommu *iommu)
393 unsigned long reg, xlate_base;
396 if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
397 panic("%s: missing IOC register mappings for node %d\n",
398 __func__, iommu->nid);
400 iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
401 iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
403 /* ensure that the STEs have updated */
406 /* setup interrupts for the iommu. */
407 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
408 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
409 reg & ~IOC_IO_ExcpStat_V);
410 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
411 IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE);
413 virq = irq_create_mapping(NULL,
414 IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT));
415 BUG_ON(virq == NO_IRQ);
417 ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED,
421 /* set the IOC segment table origin register (and turn on the iommu) */
422 reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW;
423 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
424 in_be64(iommu->xlate_regs + IOC_IOST_Origin);
426 /* turn on IO translation */
427 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
428 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
431 static void cell_iommu_setup_hardware(struct cbe_iommu *iommu,
432 unsigned long base, unsigned long size)
434 cell_iommu_setup_stab(iommu, base, size, 0, 0);
435 iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0,
437 cell_iommu_enable_hardware(iommu);
440 #if 0/* Unused for now */
441 static struct iommu_window *find_window(struct cbe_iommu *iommu,
442 unsigned long offset, unsigned long size)
444 struct iommu_window *window;
446 /* todo: check for overlapping (but not equal) windows) */
448 list_for_each_entry(window, &(iommu->windows), list) {
449 if (window->offset == offset && window->size == size)
457 static inline u32 cell_iommu_get_ioid(struct device_node *np)
461 ioid = of_get_property(np, "ioid", NULL);
463 printk(KERN_WARNING "iommu: missing ioid for %s using 0\n",
471 static struct iommu_window * __init
472 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
473 unsigned long offset, unsigned long size,
474 unsigned long pte_offset)
476 struct iommu_window *window;
480 ioid = cell_iommu_get_ioid(np);
482 window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid);
483 BUG_ON(window == NULL);
485 window->offset = offset;
488 window->iommu = iommu;
490 window->table.it_blocksize = 16;
491 window->table.it_base = (unsigned long)iommu->ptab;
492 window->table.it_index = iommu->nid;
493 window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset;
494 window->table.it_size = size >> IOMMU_PAGE_SHIFT;
496 iommu_init_table(&window->table, iommu->nid);
498 pr_debug("\tioid %d\n", window->ioid);
499 pr_debug("\tblocksize %ld\n", window->table.it_blocksize);
500 pr_debug("\tbase 0x%016lx\n", window->table.it_base);
501 pr_debug("\toffset 0x%lx\n", window->table.it_offset);
502 pr_debug("\tsize %ld\n", window->table.it_size);
504 list_add(&window->list, &iommu->windows);
509 /* We need to map and reserve the first IOMMU page since it's used
510 * by the spider workaround. In theory, we only need to do that when
511 * running on spider but it doesn't really matter.
513 * This code also assumes that we have a window that starts at 0,
514 * which is the case on all spider based blades.
516 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
518 iommu->pad_page = page_address(page);
519 clear_page(iommu->pad_page);
521 __set_bit(0, window->table.it_map);
522 tce_build_cell(&window->table, window->table.it_offset, 1,
523 (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL);
524 window->table.it_hint = window->table.it_blocksize;
529 static struct cbe_iommu *cell_iommu_for_node(int nid)
533 for (i = 0; i < cbe_nr_iommus; i++)
534 if (iommus[i].nid == nid)
539 static unsigned long cell_dma_direct_offset;
541 static unsigned long dma_iommu_fixed_base;
542 struct dma_mapping_ops dma_iommu_fixed_ops;
544 static struct iommu_table *cell_get_iommu_table(struct device *dev)
546 struct iommu_window *window;
547 struct cbe_iommu *iommu;
548 struct dev_archdata *archdata = &dev->archdata;
550 /* Current implementation uses the first window available in that
551 * node's iommu. We -might- do something smarter later though it may
554 iommu = cell_iommu_for_node(archdata->numa_node);
555 if (iommu == NULL || list_empty(&iommu->windows)) {
556 printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n",
557 archdata->of_node ? archdata->of_node->full_name : "?",
558 archdata->numa_node);
561 window = list_entry(iommu->windows.next, struct iommu_window, list);
563 return &window->table;
566 static void cell_dma_dev_setup_fixed(struct device *dev);
568 static void cell_dma_dev_setup(struct device *dev)
570 struct dev_archdata *archdata = &dev->archdata;
572 /* Order is important here, these are not mutually exclusive */
573 if (get_dma_ops(dev) == &dma_iommu_fixed_ops)
574 cell_dma_dev_setup_fixed(dev);
575 else if (get_pci_dma_ops() == &dma_iommu_ops)
576 archdata->dma_data = cell_get_iommu_table(dev);
577 else if (get_pci_dma_ops() == &dma_direct_ops)
578 archdata->dma_data = (void *)cell_dma_direct_offset;
583 static void cell_pci_dma_dev_setup(struct pci_dev *dev)
585 cell_dma_dev_setup(&dev->dev);
588 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action,
591 struct device *dev = data;
593 /* We are only intereted in device addition */
594 if (action != BUS_NOTIFY_ADD_DEVICE)
597 /* We use the PCI DMA ops */
598 dev->archdata.dma_ops = get_pci_dma_ops();
600 cell_dma_dev_setup(dev);
605 static struct notifier_block cell_of_bus_notifier = {
606 .notifier_call = cell_of_bus_notify
609 static int __init cell_iommu_get_window(struct device_node *np,
613 const void *dma_window;
616 /* Use ibm,dma-window if available, else, hard code ! */
617 dma_window = of_get_property(np, "ibm,dma-window", NULL);
618 if (dma_window == NULL) {
624 of_parse_dma_window(np, dma_window, &index, base, size);
628 static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np)
630 struct cbe_iommu *iommu;
634 nid = of_node_to_nid(np);
636 printk(KERN_ERR "iommu: failed to get node for %s\n",
640 pr_debug("iommu: setting up iommu for node %d (%s)\n",
643 /* XXX todo: If we can have multiple windows on the same IOMMU, which
644 * isn't the case today, we probably want here to check wether the
645 * iommu for that node is already setup.
646 * However, there might be issue with getting the size right so let's
647 * ignore that for now. We might want to completely get rid of the
648 * multiple window support since the cell iommu supports per-page ioids
651 if (cbe_nr_iommus >= NR_IOMMUS) {
652 printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n",
657 /* Init base fields */
662 snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i);
663 INIT_LIST_HEAD(&iommu->windows);
668 static void __init cell_iommu_init_one(struct device_node *np,
669 unsigned long offset)
671 struct cbe_iommu *iommu;
672 unsigned long base, size;
674 iommu = cell_iommu_alloc(np);
678 /* Obtain a window for it */
679 cell_iommu_get_window(np, &base, &size);
681 pr_debug("\ttranslating window 0x%lx...0x%lx\n",
682 base, base + size - 1);
684 /* Initialize the hardware */
685 cell_iommu_setup_hardware(iommu, base, size);
687 /* Setup the iommu_table */
688 cell_iommu_setup_window(iommu, np, base, size,
689 offset >> IOMMU_PAGE_SHIFT);
692 static void __init cell_disable_iommus(void)
695 unsigned long base, val;
696 void __iomem *xregs, *cregs;
698 /* Make sure IOC translation is disabled on all nodes */
699 for_each_online_node(node) {
700 if (cell_iommu_find_ioc(node, &base))
702 xregs = ioremap(base, IOC_Reg_Size);
705 cregs = xregs + IOC_IOCmd_Offset;
707 pr_debug("iommu: cleaning up iommu on node %d\n", node);
709 out_be64(xregs + IOC_IOST_Origin, 0);
710 (void)in_be64(xregs + IOC_IOST_Origin);
711 val = in_be64(cregs + IOC_IOCmd_Cfg);
712 val &= ~IOC_IOCmd_Cfg_TE;
713 out_be64(cregs + IOC_IOCmd_Cfg, val);
714 (void)in_be64(cregs + IOC_IOCmd_Cfg);
720 static int __init cell_iommu_init_disabled(void)
722 struct device_node *np = NULL;
723 unsigned long base = 0, size;
725 /* When no iommu is present, we use direct DMA ops */
726 set_pci_dma_ops(&dma_direct_ops);
728 /* First make sure all IOC translation is turned off */
729 cell_disable_iommus();
731 /* If we have no Axon, we set up the spider DMA magic offset */
732 if (of_find_node_by_name(NULL, "axon") == NULL)
733 cell_dma_direct_offset = SPIDER_DMA_OFFSET;
735 /* Now we need to check to see where the memory is mapped
736 * in PCI space. We assume that all busses use the same dma
737 * window which is always the case so far on Cell, thus we
738 * pick up the first pci-internal node we can find and check
739 * the DMA window from there.
741 for_each_node_by_name(np, "axon") {
742 if (np->parent == NULL || np->parent->parent != NULL)
744 if (cell_iommu_get_window(np, &base, &size) == 0)
748 for_each_node_by_name(np, "pci-internal") {
749 if (np->parent == NULL || np->parent->parent != NULL)
751 if (cell_iommu_get_window(np, &base, &size) == 0)
757 /* If we found a DMA window, we check if it's big enough to enclose
758 * all of physical memory. If not, we force enable IOMMU
760 if (np && size < lmb_end_of_DRAM()) {
761 printk(KERN_WARNING "iommu: force-enabled, dma window"
762 " (%ldMB) smaller than total memory (%ldMB)\n",
763 size >> 20, lmb_end_of_DRAM() >> 20);
767 cell_dma_direct_offset += base;
769 if (cell_dma_direct_offset != 0)
770 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
772 printk("iommu: disabled, direct DMA offset is 0x%lx\n",
773 cell_dma_direct_offset);
779 * Fixed IOMMU mapping support
781 * This code adds support for setting up a fixed IOMMU mapping on certain
782 * cell machines. For 64-bit devices this avoids the performance overhead of
783 * mapping and unmapping pages at runtime. 32-bit devices are unable to use
786 * The fixed mapping is established at boot, and maps all of physical memory
787 * 1:1 into device space at some offset. On machines with < 30 GB of memory
788 * we setup the fixed mapping immediately above the normal IOMMU window.
790 * For example a machine with 4GB of memory would end up with the normal
791 * IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In
792 * this case a 64-bit device wishing to DMA to 1GB would be told to DMA to
793 * 3GB, plus any offset required by firmware. The firmware offset is encoded
794 * in the "dma-ranges" property.
796 * On machines with 30GB or more of memory, we are unable to place the fixed
797 * mapping above the normal IOMMU window as we would run out of address space.
798 * Instead we move the normal IOMMU window to coincide with the hash page
799 * table, this region does not need to be part of the fixed mapping as no
800 * device should ever be DMA'ing to it. We then setup the fixed mapping
804 static u64 cell_iommu_get_fixed_address(struct device *dev)
806 u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR;
807 struct device_node *np;
808 const u32 *ranges = NULL;
809 int i, len, best, naddr, nsize, pna, range_size;
811 np = of_node_get(dev->archdata.of_node);
813 naddr = of_n_addr_cells(np);
814 nsize = of_n_size_cells(np);
815 np = of_get_next_parent(np);
819 ranges = of_get_property(np, "dma-ranges", &len);
821 /* Ignore empty ranges, they imply no translation required */
822 if (ranges && len > 0)
827 dev_dbg(dev, "iommu: no dma-ranges found\n");
833 pna = of_n_addr_cells(np);
834 range_size = naddr + nsize + pna;
836 /* dma-ranges format:
837 * child addr : naddr cells
838 * parent addr : pna cells
841 for (i = 0, best = -1, best_size = 0; i < len; i += range_size) {
842 cpu_addr = of_translate_dma_address(np, ranges + i + naddr);
843 size = of_read_number(ranges + i + naddr + pna, nsize);
845 if (cpu_addr == 0 && size > best_size) {
852 dev_addr = of_read_number(ranges + best, naddr);
854 dev_dbg(dev, "iommu: no suitable range found!\n");
862 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask)
864 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
867 if (dma_mask == DMA_BIT_MASK(64) &&
868 cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR)
870 dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
871 set_dma_ops(dev, &dma_iommu_fixed_ops);
873 dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
874 set_dma_ops(dev, get_pci_dma_ops());
877 cell_dma_dev_setup(dev);
879 *dev->dma_mask = dma_mask;
884 static void cell_dma_dev_setup_fixed(struct device *dev)
886 struct dev_archdata *archdata = &dev->archdata;
889 addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base;
890 archdata->dma_data = (void *)addr;
892 dev_dbg(dev, "iommu: fixed addr = %lx\n", addr);
895 static void insert_16M_pte(unsigned long addr, unsigned long *ptab,
896 unsigned long base_pte)
898 unsigned long segment, offset;
900 segment = addr >> IO_SEGMENT_SHIFT;
901 offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24));
902 ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long));
904 pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
905 addr, ptab, segment, offset);
907 ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask);
910 static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
911 struct device_node *np, unsigned long dbase, unsigned long dsize,
912 unsigned long fbase, unsigned long fsize)
914 unsigned long base_pte, uaddr, ioaddr, *ptab;
916 ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24);
918 dma_iommu_fixed_base = fbase;
920 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
922 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW
923 | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask);
925 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
926 /* Don't touch the dynamic region */
927 ioaddr = uaddr + fbase;
928 if (ioaddr >= dbase && ioaddr < (dbase + dsize)) {
929 pr_debug("iommu: fixed/dynamic overlap, skipping\n");
933 insert_16M_pte(uaddr, ptab, base_pte);
939 static int __init cell_iommu_fixed_mapping_init(void)
941 unsigned long dbase, dsize, fbase, fsize, hbase, hend;
942 struct cbe_iommu *iommu;
943 struct device_node *np;
945 /* The fixed mapping is only supported on axon machines */
946 np = of_find_node_by_name(NULL, "axon");
948 pr_debug("iommu: fixed mapping disabled, no axons found\n");
952 /* We must have dma-ranges properties for fixed mapping to work */
953 for (np = NULL; (np = of_find_all_nodes(np));) {
954 if (of_find_property(np, "dma-ranges", NULL))
960 pr_debug("iommu: no dma-ranges found, no fixed mapping\n");
964 /* The default setup is to have the fixed mapping sit after the
965 * dynamic region, so find the top of the largest IOMMU window
966 * on any axon, then add the size of RAM and that's our max value.
967 * If that is > 32GB we have to do other shennanigans.
970 for_each_node_by_name(np, "axon") {
971 cell_iommu_get_window(np, &dbase, &dsize);
972 fbase = max(fbase, dbase + dsize);
975 fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT);
976 fsize = lmb_phys_mem_size();
978 if ((fbase + fsize) <= 0x800000000)
979 hbase = 0; /* use the device tree window */
981 /* If we're over 32 GB we need to cheat. We can't map all of
982 * RAM with the fixed mapping, and also fit the dynamic
983 * region. So try to place the dynamic region where the hash
984 * table sits, drivers never need to DMA to it, we don't
985 * need a fixed mapping for that area.
988 pr_debug("iommu: htab is NULL, on LPAR? Huh?\n");
991 hbase = __pa(htab_address);
992 hend = hbase + htab_size_bytes;
994 /* The window must start and end on a segment boundary */
995 if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) ||
996 (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) {
997 pr_debug("iommu: hash window not segment aligned\n");
1001 /* Check the hash window fits inside the real DMA window */
1002 for_each_node_by_name(np, "axon") {
1003 cell_iommu_get_window(np, &dbase, &dsize);
1005 if (hbase < dbase || (hend > (dbase + dsize))) {
1006 pr_debug("iommu: hash window doesn't fit in"
1007 "real DMA window\n");
1015 /* Setup the dynamic regions */
1016 for_each_node_by_name(np, "axon") {
1017 iommu = cell_iommu_alloc(np);
1021 cell_iommu_get_window(np, &dbase, &dsize);
1024 dsize = htab_size_bytes;
1027 printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx "
1028 "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase,
1029 dbase + dsize, fbase, fbase + fsize);
1031 cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize);
1032 iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0,
1034 cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize,
1036 cell_iommu_enable_hardware(iommu);
1037 cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
1040 dma_iommu_fixed_ops = dma_direct_ops;
1041 dma_iommu_fixed_ops.set_dma_mask = dma_set_mask_and_switch;
1043 dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch;
1044 set_pci_dma_ops(&dma_iommu_ops);
1049 static int iommu_fixed_disabled;
1051 static int __init setup_iommu_fixed(char *str)
1053 if (strcmp(str, "off") == 0)
1054 iommu_fixed_disabled = 1;
1058 __setup("iommu_fixed=", setup_iommu_fixed);
1060 static int __init cell_iommu_init(void)
1062 struct device_node *np;
1064 /* If IOMMU is disabled or we have little enough RAM to not need
1065 * to enable it, we setup a direct mapping.
1067 * Note: should we make sure we have the IOMMU actually disabled ?
1070 (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull))
1071 if (cell_iommu_init_disabled() == 0)
1074 /* Setup various ppc_md. callbacks */
1075 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
1076 ppc_md.tce_build = tce_build_cell;
1077 ppc_md.tce_free = tce_free_cell;
1079 if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0)
1082 /* Create an iommu for each /axon node. */
1083 for_each_node_by_name(np, "axon") {
1084 if (np->parent == NULL || np->parent->parent != NULL)
1086 cell_iommu_init_one(np, 0);
1089 /* Create an iommu for each toplevel /pci-internal node for
1090 * old hardware/firmware
1092 for_each_node_by_name(np, "pci-internal") {
1093 if (np->parent == NULL || np->parent->parent != NULL)
1095 cell_iommu_init_one(np, SPIDER_DMA_OFFSET);
1098 /* Setup default PCI iommu ops */
1099 set_pci_dma_ops(&dma_iommu_ops);
1102 /* Register callbacks on OF platform device addition/removal
1103 * to handle linking them to the right DMA operations
1105 bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier);
1109 machine_arch_initcall(cell, cell_iommu_init);
1110 machine_arch_initcall(celleb_native, cell_iommu_init);