2 * MPC8610 HPCD board specific routines
4 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
5 * Recode: Jason Jin <jason.jin@freescale.com>
6 * York Sun <yorksun@freescale.com>
8 * Rewrite the interrupt routing. remove the 8259PIC support,
9 * All the integrated device in ULI use sideband interrupt.
11 * Copyright 2008 Freescale Semiconductor Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
27 #include <asm/system.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/mpc86xx.h>
33 #include <mm/mmu_decl.h>
38 #include <linux/of_platform.h>
39 #include <sysdev/fsl_pci.h>
40 #include <sysdev/fsl_soc.h>
42 static unsigned char *pixis_bdcfg0, *pixis_arch;
44 static struct of_device_id __initdata mpc8610_ids[] = {
45 { .compatible = "fsl,mpc8610-immr", },
46 { .compatible = "simple-bus", },
50 static int __init mpc8610_declare_of_platform_devices(void)
52 /* Without this call, the SSI device driver won't get probed. */
53 of_platform_bus_probe(NULL, mpc8610_ids, NULL);
57 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
59 static void __init mpc86xx_hpcd_init_irq(void)
62 struct device_node *np;
65 /* Determine PIC address. */
66 np = of_find_node_by_type(NULL, "open-pic");
69 of_address_to_resource(np, 0, &res);
71 /* Alloc mpic structure and per isu has 16 INT entries. */
72 mpic1 = mpic_alloc(np, res.start,
73 MPIC_PRIMARY | MPIC_WANTS_RESET |
74 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
76 BUG_ON(mpic1 == NULL);
82 static void __devinit quirk_uli1575(struct pci_dev *dev)
87 pci_read_config_dword(dev, 0x48, &temp32);
88 pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
90 /* Enable sideband interrupt */
91 pci_read_config_dword(dev, 0x90, &temp32);
92 pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
95 static void __devinit quirk_uli5288(struct pci_dev *dev)
100 /* Interrupt Disable, Needed when SATA disabled */
101 pci_read_config_word(dev, PCI_COMMAND, &temp);
103 pci_write_config_word(dev, PCI_COMMAND, temp);
105 pci_read_config_byte(dev, 0x83, &c);
107 pci_write_config_byte(dev, 0x83, c);
109 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
110 pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
112 pci_read_config_byte(dev, 0x83, &c);
114 pci_write_config_byte(dev, 0x83, c);
118 * Since 8259PIC was disabled on the board, the IDE device can not
119 * use the legacy IRQ, we need to let the IDE device work under
120 * native mode and use the interrupt line like other PCI devices.
121 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
122 * as the interrupt for IDE device.
124 static void __devinit quirk_uli5229(struct pci_dev *dev)
128 pci_read_config_byte(dev, 0x4b, &c);
130 pci_write_config_byte(dev, 0x4b, c);
134 * SATA interrupt pin bug fix
135 * There's a chip bug for 5288, The interrupt pin should be 2,
136 * not the read only value 1, So it use INTB#, not INTA# which
137 * actually used by the IDE device 5229.
138 * As of this bug, during the PCI initialization, 5288 read the
139 * irq of IDE device from the device tree, this function fix this
140 * bug by re-assigning a correct irq to 5288.
143 static void __devinit final_uli5288(struct pci_dev *dev)
145 struct pci_controller *hose = pci_bus_to_host(dev->bus);
146 struct device_node *hosenode = hose ? hose->dn : NULL;
154 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
155 laddr[1] = laddr[2] = 0;
156 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
157 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
166 #endif /* CONFIG_PCI */
168 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
170 static u32 get_busfreq(void)
172 struct device_node *node;
175 node = of_find_node_by_type(NULL, "cpu");
178 const unsigned int *prop =
179 of_get_property(node, "bus-frequency", &size);
187 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
190 static const unsigned long pixelformat[][3] = {
191 {0x88882317, 0x88083218, 0x65052119},
192 {0x88883316, 0x88082219, 0x65053118},
194 unsigned int pix_fmt, arch_monitor;
196 arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
197 /* DVI port for board version 0x01 */
199 if (bits_per_pixel == 32)
200 pix_fmt = pixelformat[arch_monitor][0];
201 else if (bits_per_pixel == 24)
202 pix_fmt = pixelformat[arch_monitor][1];
203 else if (bits_per_pixel == 16)
204 pix_fmt = pixelformat[arch_monitor][2];
206 pix_fmt = pixelformat[1][0];
211 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
214 if (monitor_port == 2) { /* dual link LVDS */
215 for (i = 0; i < 256*3; i++)
216 gamma_table_base[i] = (gamma_table_base[i] << 2) |
217 ((gamma_table_base[i] >> 6) & 0x03);
221 #define PX_BRDCFG0_DVISEL (1 << 3)
222 #define PX_BRDCFG0_DLINK (1 << 4)
223 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
225 void mpc8610hpcd_set_monitor_port(int monitor_port)
227 static const u8 bdcfg[] = {
228 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
233 if (monitor_port < 3)
234 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
235 bdcfg[monitor_port]);
238 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
240 u32 __iomem *clkdvdr;
242 /* variables for pixel clock calcs */
243 ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
248 clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
250 printk(KERN_ERR "Err: can't map clock divider register!\n");
254 /* Pixel Clock configuration */
255 pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
256 speed_ccb = get_busfreq();
258 /* Calculate the pixel clock with the smallest error */
259 /* calculate the following in steps to avoid overflow */
260 pr_debug("DIU pixclock in ps - %d\n", pixclock);
261 temp = 1000000000/pixclock;
264 pr_debug("DIU pixclock freq - %u\n", pixclock);
266 temp = pixclock * 5 / 100;
267 pr_debug("deviation = %d\n", temp);
268 minpixclock = pixclock - temp;
269 maxpixclock = pixclock + temp;
270 pr_debug("DIU minpixclock - %lu\n", minpixclock);
271 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
272 pixval = speed_ccb/pixclock;
273 pr_debug("DIU pixval = %lu\n", pixval);
277 pr_debug("DIU bestval = %lu\n", bestval);
280 for (i = -1; i <= 1; i++) {
281 temp = speed_ccb / ((pixval+i) + 1);
282 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
284 if ((temp < minpixclock) || (temp > maxpixclock))
285 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
286 minpixclock, maxpixclock);
287 else if (abs(temp - pixclock) < err) {
288 pr_debug("Entered the else if block %d\n", i);
289 err = abs(temp - pixclock);
295 pr_debug("DIU chose = %lx\n", bestval);
296 pr_debug("DIU error = %ld\n NomPixClk ", err);
297 pr_debug("DIU: Best Freq = %lx\n", bestfreq);
298 /* Modify PXCLK in GUTS CLKDVDR */
299 pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
300 temp = (*clkdvdr) & 0x2000FFFF;
301 *clkdvdr = temp; /* turn off clock */
302 *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
303 pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
307 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
309 return snprintf(buf, PAGE_SIZE,
311 "%c1 - Single link LVDS\n"
312 "%c2 - Dual link LVDS\n",
313 monitor_port == 0 ? '*' : ' ',
314 monitor_port == 1 ? '*' : ' ',
315 monitor_port == 2 ? '*' : ' ');
318 int mpc8610hpcd_set_sysfs_monitor_port(int val)
320 return val < 3 ? val : 0;
325 static void __init mpc86xx_hpcd_setup_arch(void)
328 struct device_node *np;
329 unsigned char *pixis;
332 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
335 for_each_node_by_type(np, "pci") {
336 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
337 || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
338 struct resource rsrc;
339 of_address_to_resource(np, 0, &rsrc);
340 if ((rsrc.start & 0xfffff) == 0xa000)
341 fsl_add_bridge(np, 1);
343 fsl_add_bridge(np, 0);
347 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
348 preallocate_diu_videomemory();
349 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
350 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
351 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
352 diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
353 diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
354 diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
357 np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
359 of_address_to_resource(np, 0, &r);
361 pixis = ioremap(r.start, 32);
363 printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
366 pixis_bdcfg0 = pixis + 8;
367 pixis_arch = pixis + 1;
369 printk(KERN_ERR "Err: "
370 "can't find device node 'fsl,fpga-pixis'\n");
372 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
376 * Called very early, device-tree isn't unflattened
378 static int __init mpc86xx_hpcd_probe(void)
380 unsigned long root = of_get_flat_dt_root();
382 if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
383 return 1; /* Looks good */
388 static long __init mpc86xx_time_init(void)
392 /* Set the time base to zero */
396 temp = mfspr(SPRN_HID0);
398 mtspr(SPRN_HID0, temp);
399 asm volatile("isync");
404 define_machine(mpc86xx_hpcd) {
405 .name = "MPC86xx HPCD",
406 .probe = mpc86xx_hpcd_probe,
407 .setup_arch = mpc86xx_hpcd_setup_arch,
408 .init_IRQ = mpc86xx_hpcd_init_irq,
409 .get_irq = mpic_get_irq,
410 .restart = fsl_rstcr_restart,
411 .time_init = mpc86xx_time_init,
412 .calibrate_decr = generic_calibrate_decr,
413 .progress = udbg_progress,
414 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,