2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
4 * Author: Andy Fleming <afleming@freescale.com>
6 * Based on 83xx/mpc8360e_pb.c by:
7 * Li Yang <LeoLi@freescale.com>
8 * Yin Olivia <Hong-hua.Yin@freescale.com>
11 * MPC85xx MDS board specific routines.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/initrd.h>
31 #include <linux/module.h>
32 #include <linux/fsl_devices.h>
34 #include <asm/of_device.h>
35 #include <asm/of_platform.h>
36 #include <asm/system.h>
37 #include <asm/atomic.h>
40 #include <asm/machdep.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/mpc85xx.h>
44 #include <mm/mmu_decl.h>
47 #include <sysdev/fsl_soc.h>
48 #include <sysdev/fsl_pci.h>
50 #include <asm/qe_ic.h>
55 #define DBG(fmt...) udbg_printf(fmt)
60 /* ************************************************************************
62 * Setup the architecture
65 static void __init mpc85xx_mds_setup_arch(void)
67 struct device_node *np;
68 static u8 *bcsr_regs = NULL;
71 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
74 np = of_find_node_by_name(NULL, "bcsr");
78 of_address_to_resource(np, 0, &res);
79 bcsr_regs = ioremap(res.start, res.end - res.start +1);
84 for_each_node_by_type(np, "pci") {
85 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
86 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
88 of_address_to_resource(np, 0, &rsrc);
89 if ((rsrc.start & 0xfffff) == 0x8000)
90 fsl_add_bridge(np, 1);
92 fsl_add_bridge(np, 0);
97 #ifdef CONFIG_QUICC_ENGINE
98 if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
103 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
104 struct device_node *ucc = NULL;
109 for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
110 par_io_of_config(ucc);
118 /* Reset the Ethernet PHY */
119 bcsr_phy = in_be8(&bcsr_regs[9]);
121 out_be8(&bcsr_regs[9], bcsr_phy);
125 bcsr_phy = in_be8(&bcsr_regs[9]);
127 out_be8(&bcsr_regs[9], bcsr_phy);
132 #endif /* CONFIG_QUICC_ENGINE */
135 static struct of_device_id mpc85xx_ids[] = {
137 { .compatible = "soc", },
142 static int __init mpc85xx_publish_devices(void)
144 if (!machine_is(mpc85xx_mds))
147 /* Publish the QE devices */
148 of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
152 device_initcall(mpc85xx_publish_devices);
154 static void __init mpc85xx_mds_pic_init(void)
158 struct device_node *np = NULL;
160 np = of_find_node_by_type(NULL, "open-pic");
164 if (of_address_to_resource(np, 0, &r)) {
165 printk(KERN_ERR "Failed to map mpic register space\n");
170 mpic = mpic_alloc(np, r.start,
171 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
172 0, 256, " OpenPIC ");
173 BUG_ON(mpic == NULL);
178 #ifdef CONFIG_QUICC_ENGINE
179 np = of_find_node_by_type(NULL, "qeic");
185 #endif /* CONFIG_QUICC_ENGINE */
188 static int __init mpc85xx_mds_probe(void)
190 unsigned long root = of_get_flat_dt_root();
192 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
195 define_machine(mpc85xx_mds) {
196 .name = "MPC85xx MDS",
197 .probe = mpc85xx_mds_probe,
198 .setup_arch = mpc85xx_mds_setup_arch,
199 .init_IRQ = mpc85xx_mds_pic_init,
200 .get_irq = mpic_get_irq,
201 .restart = fsl_rstcr_restart,
202 .calibrate_decr = generic_calibrate_decr,
203 .progress = udbg_progress,
205 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,