arch/powerpc/oprofile/op_model_cell.c

   1 /*
   2  * Cell Broadband Engine OProfile Support
   3  *
   4  * (C) Copyright IBM Corporation 2006
   5  *
   6  * Author: David Erb (djerb@us.ibm.com)
   7  * Modifications:
   8  *         Carl Love <carll@us.ibm.com>
   9  *         Maynard Johnson <maynardj@us.ibm.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version
  14  * 2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/cpufreq.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/kthread.h>
  22 #include <linux/oprofile.h>
  23 #include <linux/percpu.h>
  24 #include <linux/smp.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/timer.h>
  27 #include <asm/cell-pmu.h>
  28 #include <asm/cputable.h>
  29 #include <asm/firmware.h>
  30 #include <asm/io.h>
  31 #include <asm/oprofile_impl.h>
  32 #include <asm/processor.h>
  33 #include <asm/prom.h>
  34 #include <asm/ptrace.h>
  35 #include <asm/reg.h>
  36 #include <asm/rtas.h>
  37 #include <asm/system.h>
  38
  39 #include "../platforms/cell/interrupt.h"
  40
  41 #define PPU_CYCLES_EVENT_NUM 1  /*  event number for CYCLES */
  42 #define CBE_COUNT_ALL_CYCLES 0x42800000 /* PPU cycle event specifier */
  43
  44 #define NUM_THREADS 2         /* number of physical threads in
  45                                * physical processor
  46                                */
  47 #define NUM_TRACE_BUS_WORDS 4
  48 #define NUM_INPUT_BUS_WORDS 2
  49
  50
  51 struct pmc_cntrl_data {
  52         unsigned long vcntr;
  53         unsigned long evnts;
  54         unsigned long masks;
  55         unsigned long enabled;
  56 };
  57
  58 /*
  59  * ibm,cbe-perftools rtas parameters
  60  */
  61
  62 struct pm_signal {
  63         u16 cpu;                /* Processor to modify */
  64         u16 sub_unit;           /* hw subunit this applies to (if applicable) */
  65         u16 signal_group;       /* Signal Group to Enable/Disable */
  66         u8 bus_word;            /* Enable/Disable on this Trace/Trigger/Event
  67                                  * Bus Word(s) (bitmask)
  68                                  */
  69         u8 bit;                 /* Trigger/Event bit (if applicable) */
  70 };
  71
  72 /*
  73  * rtas call arguments
  74  */
  75 enum {
  76         SUBFUNC_RESET = 1,
  77         SUBFUNC_ACTIVATE = 2,
  78         SUBFUNC_DEACTIVATE = 3,
  79
  80         PASSTHRU_IGNORE = 0,
  81         PASSTHRU_ENABLE = 1,
  82         PASSTHRU_DISABLE = 2,
  83 };
  84
  85 struct pm_cntrl {
  86         u16 enable;
  87         u16 stop_at_max;
  88         u16 trace_mode;
  89         u16 freeze;
  90         u16 count_mode;
  91 };
  92
  93 static struct {
  94         u32 group_control;
  95         u32 debug_bus_control;
  96         struct pm_cntrl pm_cntrl;
  97         u32 pm07_cntrl[NR_PHYS_CTRS];
  98 } pm_regs;
  99
 100 #define GET_SUB_UNIT(x) ((x & 0x0000f000) >> 12)
 101 #define GET_BUS_WORD(x) ((x & 0x000000f0) >> 4)
 102 #define GET_BUS_TYPE(x) ((x & 0x00000300) >> 8)
 103 #define GET_POLARITY(x) ((x & 0x00000002) >> 1)
 104 #define GET_COUNT_CYCLES(x) (x & 0x00000001)
 105 #define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2)
 106
 107 static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values);
 108
 109 static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS];
 110
 111 /* Interpetation of hdw_thread:
 112  * 0 - even virtual cpus 0, 2, 4,...
 113  * 1 - odd virtual cpus 1, 3, 5, ...
 114  */
 115 static u32 hdw_thread;
 116
 117 static u32 virt_cntr_inter_mask;
 118 static struct timer_list timer_virt_cntr;
 119
 120 /* pm_signal needs to be global since it is initialized in
 121  * cell_reg_setup at the time when the necessary information
 122  * is available.
 123  */
 124 static struct pm_signal pm_signal[NR_PHYS_CTRS];
 125 static int pm_rtas_token;
 126
 127 static u32 reset_value[NR_PHYS_CTRS];
 128 static int num_counters;
 129 static int oprofile_running;
 130 static spinlock_t virt_cntr_lock = SPIN_LOCK_UNLOCKED;
 131
 132 static u32 ctr_enabled;
 133
 134 static unsigned char trace_bus[NUM_TRACE_BUS_WORDS];
 135 static unsigned char input_bus[NUM_INPUT_BUS_WORDS];
 136
 137 /*
 138  * Firmware interface functions
 139  */
 140 static int
 141 rtas_ibm_cbe_perftools(int subfunc, int passthru,
 142                        void *address, unsigned long length)
 143 {
 144         u64 paddr = __pa(address);
 145
 146         return rtas_call(pm_rtas_token, 5, 1, NULL, subfunc, passthru,
 147                          paddr >> 32, paddr & 0xffffffff, length);
 148 }
 149
 150 static void pm_rtas_reset_signals(u32 node)
 151 {
 152         int ret;
 153         struct pm_signal pm_signal_local;
 154
 155         /*  The debug bus is being set to the passthru disable state.
 156          *  However, the FW still expects atleast one legal signal routing
 157          *  entry or it will return an error on the arguments.  If we don't
 158          *  supply a valid entry, we must ignore all return values.  Ignoring
 159          *  all return values means we might miss an error we should be
 160          *  concerned about.
 161          */
 162
 163         /*  fw expects physical cpu #. */
 164         pm_signal_local.cpu = node;
 165         pm_signal_local.signal_group = 21;
 166         pm_signal_local.bus_word = 1;
 167         pm_signal_local.sub_unit = 0;
 168         pm_signal_local.bit = 0;
 169
 170         ret = rtas_ibm_cbe_perftools(SUBFUNC_RESET, PASSTHRU_DISABLE,
 171                                      &pm_signal_local,
 172                                      sizeof(struct pm_signal));
 173
 174         if (ret)
 175                 printk(KERN_WARNING "%s: rtas returned: %d\n",
 176                        __FUNCTION__, ret);
 177 }
 178
 179 static void pm_rtas_activate_signals(u32 node, u32 count)
 180 {
 181         int ret;
 182         int j;
 183         struct pm_signal pm_signal_local[NR_PHYS_CTRS];
 184
 185         for (j = 0; j < count; j++) {
 186                 /* fw expects physical cpu # */
 187                 pm_signal_local[j].cpu = node;
 188                 pm_signal_local[j].signal_group
 189                         = pm_signal[j].signal_group;
 190                 pm_signal_local[j].bus_word = pm_signal[j].bus_word;
 191                 pm_signal_local[j].sub_unit = pm_signal[j].sub_unit;
 192                 pm_signal_local[j].bit = pm_signal[j].bit;
 193         }
 194
 195         ret = rtas_ibm_cbe_perftools(SUBFUNC_ACTIVATE, PASSTHRU_ENABLE,
 196                                      pm_signal_local,
 197                                      count * sizeof(struct pm_signal));
 198
 199         if (ret)
 200                 printk(KERN_WARNING "%s: rtas returned: %d\n",
 201                        __FUNCTION__, ret);
 202 }
 203
 204 /*
 205  * PM Signal functions
 206  */
 207 static void set_pm_event(u32 ctr, int event, u32 unit_mask)
 208 {
 209         struct pm_signal *p;
 210         u32 signal_bit;
 211         u32 bus_word, bus_type, count_cycles, polarity, input_control;
 212         int j, i;
 213
 214         if (event == PPU_CYCLES_EVENT_NUM) {
 215                 /* Special Event: Count all cpu cycles */
 216                 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
 217                 p = &(pm_signal[ctr]);
 218                 p->signal_group = 21;
 219                 p->bus_word = 1;
 220                 p->sub_unit = 0;
 221                 p->bit = 0;
 222                 goto out;
 223         } else {
 224                 pm_regs.pm07_cntrl[ctr] = 0;
 225         }
 226
 227         bus_word = GET_BUS_WORD(unit_mask);
 228         bus_type = GET_BUS_TYPE(unit_mask);
 229         count_cycles = GET_COUNT_CYCLES(unit_mask);
 230         polarity = GET_POLARITY(unit_mask);
 231         input_control = GET_INPUT_CONTROL(unit_mask);
 232         signal_bit = (event % 100);
 233
 234         p = &(pm_signal[ctr]);
 235
 236         p->signal_group = event / 100;
 237         p->bus_word = bus_word;
 238         p->sub_unit = (unit_mask & 0x0000f000) >> 12;
 239
 240         pm_regs.pm07_cntrl[ctr] = 0;
 241         pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
 242         pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
 243         pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
 244
 245         /* Some of the islands signal selection is based on 64 bit words.
 246          * The debug bus words are 32 bits, the input words to the performance
 247          * counters are defined as 32 bits.  Need to convert the 64 bit island
 248          * specification to the appropriate 32 input bit and bus word for the
 249          * performance counter event selection.  See the CELL Performance
 250          * monitoring signals manual and the Perf cntr hardware descriptions
 251          * for the details.
 252          */
 253         if (input_control == 0) {
 254                 if (signal_bit > 31) {
 255                         signal_bit -= 32;
 256                         if (bus_word == 0x3)
 257                                 bus_word = 0x2;
 258                         else if (bus_word == 0xc)
 259                                 bus_word = 0x8;
 260                 }
 261
 262                 if ((bus_type == 0) && p->signal_group >= 60)
 263                         bus_type = 2;
 264                 if ((bus_type == 1) && p->signal_group >= 50)
 265                         bus_type = 0;
 266
 267                 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
 268         } else {
 269                 pm_regs.pm07_cntrl[ctr] = 0;
 270                 p->bit = signal_bit;
 271         }
 272
 273         for (i = 0; i < NUM_TRACE_BUS_WORDS; i++) {
 274                 if (bus_word & (1 << i)) {
 275                         pm_regs.debug_bus_control |=
 276                             (bus_type << (31 - (2 * i) + 1));
 277
 278                         for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) {
 279                                 if (input_bus[j] == 0xff) {
 280                                         input_bus[j] = i;
 281                                         pm_regs.group_control |=
 282                                             (i << (31 - i));
 283                                         break;
 284                                 }
 285                         }
 286                 }
 287         }
 288 out:
 289         ;
 290 }
 291
 292 static void write_pm_cntrl(int cpu)
 293 {
 294         /* Oprofile will use 32 bit counters, set bits 7:10 to 0
 295          * pmregs.pm_cntrl is a global
 296          */
 297
 298         u32 val = 0;
 299         if (pm_regs.pm_cntrl.enable == 1)
 300                 val |= CBE_PM_ENABLE_PERF_MON;
 301
 302         if (pm_regs.pm_cntrl.stop_at_max == 1)
 303                 val |= CBE_PM_STOP_AT_MAX;
 304
 305         if (pm_regs.pm_cntrl.trace_mode == 1)
 306                 val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);
 307
 308         if (pm_regs.pm_cntrl.freeze == 1)
 309                 val |= CBE_PM_FREEZE_ALL_CTRS;
 310
 311         /* Routine set_count_mode must be called previously to set
 312          * the count mode based on the user selection of user and kernel.
 313          */
 314         val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode);
 315         cbe_write_pm(cpu, pm_control, val);
 316 }
 317
 318 static inline void
 319 set_count_mode(u32 kernel, u32 user)
 320 {
 321         /* The user must specify user and kernel if they want them. If
 322          *  neither is specified, OProfile will count in hypervisor mode.
 323          *  pm_regs.pm_cntrl is a global
 324          */
 325         if (kernel) {
 326                 if (user)
 327                         pm_regs.pm_cntrl.count_mode = CBE_COUNT_ALL_MODES;
 328                 else
 329                         pm_regs.pm_cntrl.count_mode =
 330                                 CBE_COUNT_SUPERVISOR_MODE;
 331         } else {
 332                 if (user)
 333                         pm_regs.pm_cntrl.count_mode = CBE_COUNT_PROBLEM_MODE;
 334                 else
 335                         pm_regs.pm_cntrl.count_mode =
 336                                 CBE_COUNT_HYPERVISOR_MODE;
 337         }
 338 }
 339
 340 static inline void enable_ctr(u32 cpu, u32 ctr, u32 * pm07_cntrl)
 341 {
 342
 343         pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
 344         cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
 345 }
 346
 347 /*
 348  * Oprofile is expected to collect data on all CPUs simultaneously.
 349  * However, there is one set of performance counters per node.  There are
 350  * two hardware threads or virtual CPUs on each node.  Hence, OProfile must
 351  * multiplex in time the performance counter collection on the two virtual
 352  * CPUs.  The multiplexing of the performance counters is done by this
 353  * virtual counter routine.
 354  *
 355  * The pmc_values used below is defined as 'per-cpu' but its use is
 356  * more akin to 'per-node'.  We need to store two sets of counter
 357  * values per node -- one for the previous run and one for the next.
 358  * The per-cpu[NR_PHYS_CTRS] gives us the storage we need.  Each odd/even
 359  * pair of per-cpu arrays is used for storing the previous and next
 360  * pmc values for a given node.
 361  * NOTE: We use the per-cpu variable to improve cache performance.
 362  */
 363 static void cell_virtual_cntr(unsigned long data)
 364 {
 365         /* This routine will alternate loading the virtual counters for
 366          * virtual CPUs
 367          */
 368         int i, prev_hdw_thread, next_hdw_thread;
 369         u32 cpu;
 370         unsigned long flags;
 371
 372         /* Make sure that the interrupt_hander and
 373          * the virt counter are not both playing with
 374          * the counters on the same node.
 375          */
 376
 377         spin_lock_irqsave(&virt_cntr_lock, flags);
 378
 379         prev_hdw_thread = hdw_thread;
 380
 381         /* switch the cpu handling the interrupts */
 382         hdw_thread = 1 ^ hdw_thread;
 383         next_hdw_thread = hdw_thread;
 384
 385         for (i = 0; i < num_counters; i++)
 386         /* There are some per thread events.  Must do the
 387          * set event, for the thread that is being started
 388          */
 389                 set_pm_event(i,
 390                         pmc_cntrl[next_hdw_thread][i].evnts,
 391                         pmc_cntrl[next_hdw_thread][i].masks);
 392
 393         /* The following is done only once per each node, but
 394          * we need cpu #, not node #, to pass to the cbe_xxx functions.
 395          */
 396         for_each_online_cpu(cpu) {
 397                 if (cbe_get_hw_thread_id(cpu))
 398                         continue;
 399
 400                 /* stop counters, save counter values, restore counts
 401                  * for previous thread
 402                  */
 403                 cbe_disable_pm(cpu);
 404                 cbe_disable_pm_interrupts(cpu);
 405                 for (i = 0; i < num_counters; i++) {
 406                         per_cpu(pmc_values, cpu + prev_hdw_thread)[i]
 407                             = cbe_read_ctr(cpu, i);
 408
 409                         if (per_cpu(pmc_values, cpu + next_hdw_thread)[i]
 410                             == 0xFFFFFFFF)
 411                                 /* If the cntr value is 0xffffffff, we must
 412                                  * reset that to 0xfffffff0 when the current
 413                                  * thread is restarted.  This will generate a
 414                                  * new interrupt and make sure that we never
 415                                  * restore the counters to the max value.  If
 416                                  * the counters were restored to the max value,
 417                                  * they do not increment and no interrupts are
 418                                  * generated.  Hence no more samples will be
 419                                  * collected on that cpu.
 420                                  */
 421                                 cbe_write_ctr(cpu, i, 0xFFFFFFF0);
 422                         else
 423                                 cbe_write_ctr(cpu, i,
 424                                               per_cpu(pmc_values,
 425                                                       cpu +
 426                                                       next_hdw_thread)[i]);
 427                 }
 428
 429                 /* Switch to the other thread. Change the interrupt
 430                  * and control regs to be scheduled on the CPU
 431                  * corresponding to the thread to execute.
 432                  */
 433                 for (i = 0; i < num_counters; i++) {
 434                         if (pmc_cntrl[next_hdw_thread][i].enabled) {
 435                                 /* There are some per thread events.
 436                                  * Must do the set event, enable_cntr
 437                                  * for each cpu.
 438                                  */
 439                                 enable_ctr(cpu, i,
 440                                            pm_regs.pm07_cntrl);
 441                         } else {
 442                                 cbe_write_pm07_control(cpu, i, 0);
 443                         }
 444                 }
 445
 446                 /* Enable interrupts on the CPU thread that is starting */
 447                 cbe_enable_pm_interrupts(cpu, next_hdw_thread,
 448                                          virt_cntr_inter_mask);
 449                 cbe_enable_pm(cpu);
 450         }
 451
 452         spin_unlock_irqrestore(&virt_cntr_lock, flags);
 453
 454         mod_timer(&timer_virt_cntr, jiffies + HZ / 10);
 455 }
 456
 457 static void start_virt_cntrs(void)
 458 {
 459         init_timer(&timer_virt_cntr);
 460         timer_virt_cntr.function = cell_virtual_cntr;
 461         timer_virt_cntr.data = 0UL;
 462         timer_virt_cntr.expires = jiffies + HZ / 10;
 463         add_timer(&timer_virt_cntr);
 464 }
 465
 466 /* This function is called once for all cpus combined */
 467 static void
 468 cell_reg_setup(struct op_counter_config *ctr,
 469                struct op_system_config *sys, int num_ctrs)
 470 {
 471         int i, j, cpu;
 472
 473         pm_rtas_token = rtas_token("ibm,cbe-perftools");
 474         if (pm_rtas_token == RTAS_UNKNOWN_SERVICE) {
 475                 printk(KERN_WARNING "%s: RTAS_UNKNOWN_SERVICE\n",
 476                        __FUNCTION__);
 477                 goto out;
 478         }
 479
 480         num_counters = num_ctrs;
 481
 482         pm_regs.group_control = 0;
 483         pm_regs.debug_bus_control = 0;
 484
 485         /* setup the pm_control register */
 486         memset(&pm_regs.pm_cntrl, 0, sizeof(struct pm_cntrl));
 487         pm_regs.pm_cntrl.stop_at_max = 1;
 488         pm_regs.pm_cntrl.trace_mode = 0;
 489         pm_regs.pm_cntrl.freeze = 1;
 490
 491         set_count_mode(sys->enable_kernel, sys->enable_user);
 492
 493         /* Setup the thread 0 events */
 494         for (i = 0; i < num_ctrs; ++i) {
 495
 496                 pmc_cntrl[0][i].evnts = ctr[i].event;
 497                 pmc_cntrl[0][i].masks = ctr[i].unit_mask;
 498                 pmc_cntrl[0][i].enabled = ctr[i].enabled;
 499                 pmc_cntrl[0][i].vcntr = i;
 500
 501                 for_each_possible_cpu(j)
 502                         per_cpu(pmc_values, j)[i] = 0;
 503         }
 504
 505         /* Setup the thread 1 events, map the thread 0 event to the
 506          * equivalent thread 1 event.
 507          */
 508         for (i = 0; i < num_ctrs; ++i) {
 509                 if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))
 510                         pmc_cntrl[1][i].evnts = ctr[i].event + 19;
 511                 else if (ctr[i].event == 2203)
 512                         pmc_cntrl[1][i].evnts = ctr[i].event;
 513                 else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))
 514                         pmc_cntrl[1][i].evnts = ctr[i].event + 16;
 515                 else
 516                         pmc_cntrl[1][i].evnts = ctr[i].event;
 517
 518                 pmc_cntrl[1][i].masks = ctr[i].unit_mask;
 519                 pmc_cntrl[1][i].enabled = ctr[i].enabled;
 520                 pmc_cntrl[1][i].vcntr = i;
 521         }
 522
 523         for (i = 0; i < NUM_TRACE_BUS_WORDS; i++)
 524                 trace_bus[i] = 0xff;
 525
 526         for (i = 0; i < NUM_INPUT_BUS_WORDS; i++)
 527                 input_bus[i] = 0xff;
 528
 529         /* Our counters count up, and "count" refers to
 530          * how much before the next interrupt, and we interrupt
 531          * on overflow.  So we calculate the starting value
 532          * which will give us "count" until overflow.
 533          * Then we set the events on the enabled counters.
 534          */
 535         for (i = 0; i < num_counters; ++i) {
 536                 /* start with virtual counter set 0 */
 537                 if (pmc_cntrl[0][i].enabled) {
 538                         /* Using 32bit counters, reset max - count */
 539                         reset_value[i] = 0xFFFFFFFF - ctr[i].count;
 540                         set_pm_event(i,
 541                                      pmc_cntrl[0][i].evnts,
 542                                      pmc_cntrl[0][i].masks);
 543
 544                         /* global, used by cell_cpu_setup */
 545                         ctr_enabled |= (1 << i);
 546                 }
 547         }
 548
 549         /* initialize the previous counts for the virtual cntrs */
 550         for_each_online_cpu(cpu)
 551                 for (i = 0; i < num_counters; ++i) {
 552                         per_cpu(pmc_values, cpu)[i] = reset_value[i];
 553                 }
 554 out:
 555         ;
 556 }
 557
 558 /* This function is called once for each cpu */
 559 static void cell_cpu_setup(struct op_counter_config *cntr)
 560 {
 561         u32 cpu = smp_processor_id();
 562         u32 num_enabled = 0;
 563         int i;
 564
 565         /* There is one performance monitor per processor chip (i.e. node),
 566          * so we only need to perform this function once per node.
 567          */
 568         if (cbe_get_hw_thread_id(cpu))
 569                 goto out;
 570
 571         if (pm_rtas_token == RTAS_UNKNOWN_SERVICE) {
 572                 printk(KERN_WARNING "%s: RTAS_UNKNOWN_SERVICE\n",
 573                        __FUNCTION__);
 574                 goto out;
 575         }
 576
 577         /* Stop all counters */
 578         cbe_disable_pm(cpu);
 579         cbe_disable_pm_interrupts(cpu);
 580
 581         cbe_write_pm(cpu, pm_interval, 0);
 582         cbe_write_pm(cpu, pm_start_stop, 0);
 583         cbe_write_pm(cpu, group_control, pm_regs.group_control);
 584         cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
 585         write_pm_cntrl(cpu);
 586
 587         for (i = 0; i < num_counters; ++i) {
 588                 if (ctr_enabled & (1 << i)) {
 589                         pm_signal[num_enabled].cpu = cbe_cpu_to_node(cpu);
 590                         num_enabled++;
 591                 }
 592         }
 593
 594         pm_rtas_activate_signals(cbe_cpu_to_node(cpu), num_enabled);
 595 out:
 596         ;
 597 }
 598
 599 static void cell_global_start(struct op_counter_config *ctr)
 600 {
 601         u32 cpu;
 602         u32 interrupt_mask = 0;
 603         u32 i;
 604
 605         /* This routine gets called once for the system.
 606          * There is one performance monitor per node, so we
 607          * only need to perform this function once per node.
 608          */
 609         for_each_online_cpu(cpu) {
 610                 if (cbe_get_hw_thread_id(cpu))
 611                         continue;
 612
 613                 interrupt_mask = 0;
 614
 615                 for (i = 0; i < num_counters; ++i) {
 616                         if (ctr_enabled & (1 << i)) {
 617                                 cbe_write_ctr(cpu, i, reset_value[i]);
 618                                 enable_ctr(cpu, i, pm_regs.pm07_cntrl);
 619                                 interrupt_mask |=
 620                                     CBE_PM_CTR_OVERFLOW_INTR(i);
 621                         } else {
 622                                 /* Disable counter */
 623                                 cbe_write_pm07_control(cpu, i, 0);
 624                         }
 625                 }
 626
 627                 cbe_get_and_clear_pm_interrupts(cpu);
 628                 cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
 629                 cbe_enable_pm(cpu);
 630         }
 631
 632         virt_cntr_inter_mask = interrupt_mask;
 633         oprofile_running = 1;
 634         smp_wmb();
 635
 636         /* NOTE: start_virt_cntrs will result in cell_virtual_cntr() being
 637          * executed which manipulates the PMU.  We start the "virtual counter"
 638          * here so that we do not need to synchronize access to the PMU in
 639          * the above for-loop.
 640          */
 641         start_virt_cntrs();
 642 }
 643
 644 static void cell_global_stop(void)
 645 {
 646         int cpu;
 647
 648         /* This routine will be called once for the system.
 649          * There is one performance monitor per node, so we
 650          * only need to perform this function once per node.
 651          */
 652         del_timer_sync(&timer_virt_cntr);
 653         oprofile_running = 0;
 654         smp_wmb();
 655
 656         for_each_online_cpu(cpu) {
 657                 if (cbe_get_hw_thread_id(cpu))
 658                         continue;
 659
 660                 cbe_sync_irq(cbe_cpu_to_node(cpu));
 661                 /* Stop the counters */
 662                 cbe_disable_pm(cpu);
 663
 664                 /* Deactivate the signals */
 665                 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
 666
 667                 /* Deactivate interrupts */
 668                 cbe_disable_pm_interrupts(cpu);
 669         }
 670 }
 671
 672 static void
 673 cell_handle_interrupt(struct pt_regs *regs, struct op_counter_config *ctr)
 674 {
 675         u32 cpu;
 676         u64 pc;
 677         int is_kernel;
 678         unsigned long flags = 0;
 679         u32 interrupt_mask;
 680         int i;
 681
 682         cpu = smp_processor_id();
 683
 684         /* Need to make sure the interrupt handler and the virt counter
 685          * routine are not running at the same time. See the
 686          * cell_virtual_cntr() routine for additional comments.
 687          */
 688         spin_lock_irqsave(&virt_cntr_lock, flags);
 689
 690         /* Need to disable and reenable the performance counters
 691          * to get the desired behavior from the hardware.  This
 692          * is hardware specific.
 693          */
 694
 695         cbe_disable_pm(cpu);
 696
 697         interrupt_mask = cbe_get_and_clear_pm_interrupts(cpu);
 698
 699         /* If the interrupt mask has been cleared, then the virt cntr
 700          * has cleared the interrupt.  When the thread that generated
 701          * the interrupt is restored, the data count will be restored to
 702          * 0xffffff0 to cause the interrupt to be regenerated.
 703          */
 704
 705         if ((oprofile_running == 1) && (interrupt_mask != 0)) {
 706                 pc = regs->nip;
 707                 is_kernel = is_kernel_addr(pc);
 708
 709                 for (i = 0; i < num_counters; ++i) {
 710                         if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(i))
 711                             && ctr[i].enabled) {
 712                                 oprofile_add_pc(pc, is_kernel, i);
 713                                 cbe_write_ctr(cpu, i, reset_value[i]);
 714                         }
 715                 }
 716
 717                 /* The counters were frozen by the interrupt.
 718                  * Reenable the interrupt and restart the counters.
 719                  * If there was a race between the interrupt handler and
 720                  * the virtual counter routine.  The virutal counter
 721                  * routine may have cleared the interrupts.  Hence must
 722                  * use the virt_cntr_inter_mask to re-enable the interrupts.
 723                  */
 724                 cbe_enable_pm_interrupts(cpu, hdw_thread,
 725                                          virt_cntr_inter_mask);
 726
 727                 /* The writes to the various performance counters only writes
 728                  * to a latch.  The new values (interrupt setting bits, reset
 729                  * counter value etc.) are not copied to the actual registers
 730                  * until the performance monitor is enabled.  In order to get
 731                  * this to work as desired, the permormance monitor needs to
 732                  * be disabled while writting to the latches.  This is a
 733                  * HW design issue.
 734                  */
 735                 cbe_enable_pm(cpu);
 736         }
 737         spin_unlock_irqrestore(&virt_cntr_lock, flags);
 738 }
 739
 740 struct op_powerpc_model op_model_cell = {
 741         .reg_setup = cell_reg_setup,
 742         .cpu_setup = cell_cpu_setup,
 743         .global_start = cell_global_start,
 744         .global_stop = cell_global_stop,
 745         .handle_interrupt = cell_handle_interrupt,
 746 };