2 * PowerPC64 SLB support.
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 * Based on earlier code writteh by:
6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
7 * Copyright (c) 2001 Dave Engebretsen
8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
19 #include <asm/pgtable.h>
21 #include <asm/mmu_context.h>
23 #include <asm/cputable.h>
24 #include <asm/cacheflush.h>
26 #include <asm/firmware.h>
27 #include <linux/compiler.h>
30 #define DBG(fmt...) udbg_printf(fmt)
35 extern void slb_allocate_realmode(unsigned long ea);
36 extern void slb_allocate_user(unsigned long ea);
38 static void slb_allocate(unsigned long ea)
40 /* Currently, we do real mode for all SLBs including user, but
41 * that will change if we bring back dynamic VSIDs
43 slb_allocate_realmode(ea);
46 static inline unsigned long mk_esid_data(unsigned long ea, unsigned long slot)
48 return (ea & ESID_MASK) | SLB_ESID_V | slot;
51 static inline unsigned long mk_vsid_data(unsigned long ea, unsigned long flags)
53 return (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | flags;
56 static inline void slb_shadow_update(unsigned long ea,
61 * Clear the ESID first so the entry is not valid while we are
64 get_slb_shadow()->save_area[entry].esid = 0;
66 get_slb_shadow()->save_area[entry].vsid = mk_vsid_data(ea, flags);
68 get_slb_shadow()->save_area[entry].esid = mk_esid_data(ea, entry);
72 static inline void create_shadowed_slbe(unsigned long ea, unsigned long flags,
76 * Updating the shadow buffer before writing the SLB ensures
77 * we don't get a stale entry here if we get preempted by PHYP
78 * between these two statements.
80 slb_shadow_update(ea, flags, entry);
82 asm volatile("slbmte %0,%1" :
83 : "r" (mk_vsid_data(ea, flags)),
84 "r" (mk_esid_data(ea, entry))
88 void slb_flush_and_rebolt(void)
90 /* If you change this make sure you change SLB_NUM_BOLTED
91 * appropriately too. */
92 unsigned long linear_llp, vmalloc_llp, lflags, vflags;
93 unsigned long ksp_esid_data;
95 WARN_ON(!irqs_disabled());
97 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
98 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
99 lflags = SLB_VSID_KERNEL | linear_llp;
100 vflags = SLB_VSID_KERNEL | vmalloc_llp;
102 ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
103 if ((ksp_esid_data & ESID_MASK) == PAGE_OFFSET)
104 ksp_esid_data &= ~SLB_ESID_V;
106 /* Only third entry (stack) may change here so only resave that */
107 slb_shadow_update(get_paca()->kstack, lflags, 2);
109 /* We need to do this all in asm, so we're sure we don't touch
110 * the stack between the slbia and rebolting it. */
111 asm volatile("isync\n"
113 /* Slot 1 - first VMALLOC segment */
115 /* Slot 2 - kernel stack */
118 :: "r"(mk_vsid_data(VMALLOC_START, vflags)),
119 "r"(mk_esid_data(VMALLOC_START, 1)),
120 "r"(mk_vsid_data(ksp_esid_data, lflags)),
125 void slb_vmalloc_update(void)
127 unsigned long vflags;
129 vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
130 slb_shadow_update(VMALLOC_START, vflags, 1);
131 slb_flush_and_rebolt();
134 /* Flush all user entries from the segment table of the current processor. */
135 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
137 unsigned long offset = get_paca()->slb_cache_ptr;
138 unsigned long esid_data = 0;
139 unsigned long pc = KSTK_EIP(tsk);
140 unsigned long stack = KSTK_ESP(tsk);
141 unsigned long unmapped_base;
143 if (offset <= SLB_CACHE_ENTRIES) {
145 asm volatile("isync" : : : "memory");
146 for (i = 0; i < offset; i++) {
147 esid_data = ((unsigned long)get_paca()->slb_cache[i]
148 << SID_SHIFT) | SLBIE_C;
149 asm volatile("slbie %0" : : "r" (esid_data));
151 asm volatile("isync" : : : "memory");
153 slb_flush_and_rebolt();
156 /* Workaround POWER5 < DD2.1 issue */
157 if (offset == 1 || offset > SLB_CACHE_ENTRIES)
158 asm volatile("slbie %0" : : "r" (esid_data));
160 get_paca()->slb_cache_ptr = 0;
161 get_paca()->context = mm->context;
164 * preload some userspace segments into the SLB.
166 if (test_tsk_thread_flag(tsk, TIF_32BIT))
167 unmapped_base = TASK_UNMAPPED_BASE_USER32;
169 unmapped_base = TASK_UNMAPPED_BASE_USER64;
171 if (is_kernel_addr(pc))
175 if (GET_ESID(pc) == GET_ESID(stack))
178 if (is_kernel_addr(stack))
182 if ((GET_ESID(pc) == GET_ESID(unmapped_base))
183 || (GET_ESID(stack) == GET_ESID(unmapped_base)))
186 if (is_kernel_addr(unmapped_base))
188 slb_allocate(unmapped_base);
191 static inline void patch_slb_encoding(unsigned int *insn_addr,
194 /* Assume the instruction had a "0" immediate value, just
195 * "or" in the new value
198 flush_icache_range((unsigned long)insn_addr, 4+
199 (unsigned long)insn_addr);
202 void slb_initialize(void)
204 unsigned long linear_llp, vmalloc_llp, io_llp;
205 unsigned long lflags, vflags;
206 static int slb_encoding_inited;
207 extern unsigned int *slb_miss_kernel_load_linear;
208 extern unsigned int *slb_miss_kernel_load_io;
210 /* Prepare our SLB miss handler based on our page size */
211 linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
212 io_llp = mmu_psize_defs[mmu_io_psize].sllp;
213 vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
214 get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
216 if (!slb_encoding_inited) {
217 slb_encoding_inited = 1;
218 patch_slb_encoding(slb_miss_kernel_load_linear,
219 SLB_VSID_KERNEL | linear_llp);
220 patch_slb_encoding(slb_miss_kernel_load_io,
221 SLB_VSID_KERNEL | io_llp);
223 DBG("SLB: linear LLP = %04x\n", linear_llp);
224 DBG("SLB: io LLP = %04x\n", io_llp);
227 get_paca()->stab_rr = SLB_NUM_BOLTED;
229 /* On iSeries the bolted entries have already been set up by
230 * the hypervisor from the lparMap data in head.S */
231 if (firmware_has_feature(FW_FEATURE_ISERIES))
234 lflags = SLB_VSID_KERNEL | linear_llp;
235 vflags = SLB_VSID_KERNEL | vmalloc_llp;
237 /* Invalidate the entire SLB (even slot 0) & all the ERATS */
238 asm volatile("isync":::"memory");
239 asm volatile("slbmte %0,%0"::"r" (0) : "memory");
240 asm volatile("isync; slbia; isync":::"memory");
241 create_shadowed_slbe(PAGE_OFFSET, lflags, 0);
243 create_shadowed_slbe(VMALLOC_START, vflags, 1);
245 /* We don't bolt the stack for the time being - we're in boot,
246 * so the stack is in the bolted segment. By the time it goes
247 * elsewhere, we'll call _switch() which will bolt in the new
249 asm volatile("isync":::"memory");